pyedb 0.53.0__py3-none-any.whl → 0.55.0__py3-none-any.whl

pyedb/grpc/database/source_excitations.py

@@ -20,7 +20,7 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-from typing import List, Set, Union
+from typing import Any, Dict, List, Optional, Set, Tuple, Union
 
 from ansys.edb.core.database import ProductIdType as GrpcProductIdType
 from ansys.edb.core.geometry.point_data import PointData as GrpcPointData
@@ -29,7 +29,6 @@ from ansys.edb.core.terminal.edge_terminal import EdgeTerminal as GrpcEdgeTermin
 from ansys.edb.core.terminal.edge_terminal import PrimitiveEdge as GrpcPrimitiveEdge
 from ansys.edb.core.terminal.terminal import BoundaryType as GrpcBoundaryType
 from ansys.edb.core.utility.rlc import Rlc as GrpcRlc
-from ansys.edb.core.utility.value import Value as GrpcValue
 
 from pyedb.generic.general_methods import generate_unique_name
 from pyedb.grpc.database.components import Component
@@ -39,12 +38,15 @@ from pyedb.grpc.database.ports.ports import BundleWavePort, WavePort
 from pyedb.grpc.database.primitive.padstack_instance import PadstackInstance
 from pyedb.grpc.database.primitive.primitive import Primitive
 from pyedb.grpc.database.terminal.bundle_terminal import BundleTerminal
+from pyedb.grpc.database.terminal.edge_terminal import EdgeTerminal
 from pyedb.grpc.database.terminal.padstack_instance_terminal import (
     PadstackInstanceTerminal,
 )
 from pyedb.grpc.database.terminal.pingroup_terminal import PinGroupTerminal
 from pyedb.grpc.database.terminal.point_terminal import PointTerminal
+from pyedb.grpc.database.terminal.terminal import Terminal
 from pyedb.grpc.database.utility.sources import Source, SourceType
+from pyedb.grpc.database.utility.value import Value
 from pyedb.modeler.geometry_operators import GeometryOperators
 
 
@@ -206,25 +208,25 @@ class SourceExcitation:
         self._pedb = pedb
 
     @property
-    def _logger(self):
+    def _logger(self) -> Any:
         return self._pedb.logger
 
     @property
-    def excitations(self):
+    def excitations(self) -> Dict[str, Any]:
         """Get all excitations."""
         return self._pedb.excitations
 
     @property
-    def sources(self):
+    def sources(self) -> Dict[str, Any]:
         """Get all sources."""
         return self._pedb.sources
 
     @property
-    def probes(self):
+    def probes(self) -> Dict[str, Any]:
         """Get all probes."""
         return self._pedb.probes
 
-    def create_source_on_component(self, sources=None):
+    def create_source_on_component(self, sources: Optional[Union[Source, List[Source]]] = None) -> bool:
         """Create voltage, current source, or resistor on component.
 
         Parameters
@@ -278,12 +280,12 @@ class SourceExcitation:
                 term_name = source.name
                 positive_pin_group_term.SetName(term_name)
                 negative_pin_group_term.SetName("{}_ref".format(term_name))
-                positive_pin_group_term.source_amplitude = GrpcValue(source.amplitude)
-                negative_pin_group_term.source_amplitude = GrpcValue(source.amplitude)
-                positive_pin_group_term.source_phase = GrpcValue(source.phase)
-                negative_pin_group_term.source_phase = GrpcValue(source.phase)
-                positive_pin_group_term.impedance = GrpcValue(source.impedance)
-                negative_pin_group_term.impedance = GrpcValue(source.impedance)
+                positive_pin_group_term.source_amplitude = Value(source.amplitude)
+                negative_pin_group_term.source_amplitude = Value(source.amplitude)
+                positive_pin_group_term.source_phase = Value(source.phase)
+                negative_pin_group_term.source_phase = Value(source.phase)
+                positive_pin_group_term.impedance = Value(source.impedance)
+                negative_pin_group_term.impedance = Value(source.impedance)
                 positive_pin_group_term.reference_terminal = negative_pin_group_term
             elif source.source_type == SourceType.Isource:  # pragma: no cover
                 positive_pin_group_term = self._pedb.components._create_pin_group_terminal(
@@ -296,12 +298,12 @@ class SourceExcitation:
                 negative_pin_group_term.boundary_type = GrpcBoundaryType.CURRENT_SOURCE
                 positive_pin_group_term.name = source.name
                 negative_pin_group_term.name = "{}_ref".format(source.name)
-                positive_pin_group_term.source_amplitude = GrpcValue(source.amplitude)
-                negative_pin_group_term.source_amplitude = GrpcValue(source.amplitude)
-                positive_pin_group_term.source_phase = GrpcValue(source.phase)
-                negative_pin_group_term.source_phase = GrpcValue(source.phase)
-                positive_pin_group_term.impedance = GrpcValue(source.impedance)
-                negative_pin_group_term.impedance = GrpcValue(source.impedance)
+                positive_pin_group_term.source_amplitude = Value(source.amplitude)
+                negative_pin_group_term.source_amplitude = Value(source.amplitude)
+                positive_pin_group_term.source_phase = Value(source.phase)
+                negative_pin_group_term.source_phase = Value(source.phase)
+                positive_pin_group_term.impedance = Value(source.impedance)
+                negative_pin_group_term.impedance = Value(source.impedance)
                 positive_pin_group_term.reference_terminal = negative_pin_group_term
             elif source.source_type == SourceType.Rlc:  # pragma: no cover
                 self._pedb.components.create(
@@ -314,7 +316,13 @@ class SourceExcitation:
                 )
         return True
 
-    def create_port(self, terminal, ref_terminal=None, is_circuit_port=False, name=None):
+    def create_port(
+        self,
+        terminal: Terminal,
+        ref_terminal: Optional[Terminal] = None,
+        is_circuit_port: bool = False,
+        name: Optional[str] = None,
+    ) -> Any:
         """Create a port.
 
         Parameters
@@ -363,14 +371,14 @@ class SourceExcitation:
 
     def create_port_on_pins(
         self,
-        refdes,
-        pins,
-        reference_pins,
-        impedance=50.0,
-        port_name=None,
-        pec_boundary=False,
-        pingroup_on_single_pin=False,
-    ):
+        refdes: Union[str, Component],
+        pins: Union[int, str, PadstackInstance, List[Union[int, str, PadstackInstance]]],
+        reference_pins: Union[int, str, PadstackInstance, List[Union[int, str, PadstackInstance]]] = None,
+        impedance: Union[str, float] = "50ohm",
+        port_name: Optional[str] = None,
+        pec_boundary: bool = False,
+        pingroup_on_single_pin: bool = False,
+    ) -> PadstackInstanceTerminal:
         """Create circuit port between pins and reference ones.
 
         Parameters
@@ -423,12 +431,10 @@ class SourceExcitation:
             refdes = Component(self._pedb, refdes)
         pins = self._get_pins_for_ports(pins, refdes)
         if not pins:
-            self._logger.error("No pins found during port creation. Port is not defined.")
-            return False
+            raise RuntimeWarning("No pins found during port creation. Port is not defined.")
         reference_pins = self._get_pins_for_ports(reference_pins, refdes)
         if not reference_pins:
-            self._logger.error("No reference pins found during port creation. Port is not defined.")
-            return False
+            raise RuntimeWarning("No reference pins found during port creation. Port is not defined.")
         if refdes and any(refdes.rlc_values):
             return self._pedb.components.deactivate_rlc_component(component=refdes, create_circuit_port=True)
         if not port_name:
@@ -461,7 +467,7 @@ class SourceExcitation:
             ref_term = self._create_terminal(reference_pins[0], term_name=port_name + "_ref")
         ref_term.is_circuit_port = True
 
-        term.impedance = GrpcValue(impedance)
+        term.impedance = Value(impedance)
         term.reference_terminal = ref_term
         if pec_boundary:
             term.is_circuit_port = False
@@ -499,17 +505,17 @@ class SourceExcitation:
 
     def create_port_on_component(
         self,
-        component,
-        net_list,
-        port_type=SourceType.CoaxPort,
-        do_pingroup=True,
-        reference_net="gnd",
-        port_name=None,
-        solder_balls_height=None,
-        solder_balls_size=None,
-        solder_balls_mid_size=None,
-        extend_reference_pins_outside_component=False,
-    ):
+        component: Union[str, List[str]],
+        net_list: Union[str, List[str]],
+        port_type: SourceType,
+        do_pingroup: Optional[bool] = True,
+        reference_net: Optional[str] = None,
+        port_name: Optional[List[str]] = None,
+        solder_balls_height: Optional[float] = None,
+        solder_balls_size: Optional[float] = None,
+        solder_balls_mid_size: Optional[float] = None,
+        extend_reference_pins_outside_component: Optional[bool] = False,
+    ) -> List[str]:
         """Create ports on a component.
 
         Parameters
@@ -525,7 +531,7 @@ class SourceExcitation:
         do_pingroup : bool
             True activate pingroup during port creation (only used with combination of CircPort),
             False will take the closest reference pin and generate one port per signal pin.
-        refnet : string or list of string.
+        reference_net : string or list of string.
             list of the reference net.
         port_name : str
             Port name for overwriting the default port-naming convention,
@@ -556,7 +562,7 @@ class SourceExcitation:
         >>> from pyedb import Edb
         >>> edbapp = Edb("myaedbfolder")
         >>> net_list = ["M_DQ<1>", "M_DQ<2>", "M_DQ<3>", "M_DQ<4>", "M_DQ<5>"]
-        >>> edbapp.components.create_port_on_component(cmp="U2A5", net_list=net_list,
+        >>> edbapp.excitations.create_port_on_component(cmp="U2A5", net_list=net_list,
         >>> port_type=SourceType.CoaxPort, do_pingroup=False, refnet="GND")
 
         """
@@ -613,7 +619,7 @@ class SourceExcitation:
             pad_params = self._pedb.padstacks.get_pad_parameters(pin=cmp_pins[0], layername=pin_layers[0], pad_type=0)
             if not pad_params[0] == 7:
                 if not solder_balls_size:  # pragma no cover
-                    sball_diam = min([GrpcValue(val).value for val in pad_params[1]])
+                    sball_diam = min([Value(val) for val in pad_params[1]])
                     sball_mid_diam = sball_diam
                 else:  # pragma no cover
                     sball_diam = solder_balls_size
@@ -721,7 +727,7 @@ class SourceExcitation:
         return True
 
     @staticmethod
-    def _normalize_net_list(net_list) -> Set[str]:
+    def _normalize_net_list(net_list: Union[str, List[str]]) -> Set[str]:
         if not isinstance(net_list, list):
             net_list = [net_list]
         nets = set()
@@ -734,7 +740,9 @@ class SourceExcitation:
                 nets.add(net)
         return nets
 
-    def _create_terminal(self, pin, term_name=None):
+    def _create_terminal(
+        self, pin: PadstackInstance, term_name: Optional[str] = None
+    ) -> Optional[PadstackInstanceTerminal]:
         """Create terminal on component pin.
 
         Parameters
@@ -759,7 +767,9 @@ class SourceExcitation:
             layout=self._pedb.layout, name=term_name, padstack_instance=pin, layer=from_layer, net=pin.net, is_ref=False
         )
 
-    def add_port_on_rlc_component(self, component=None, circuit_ports=True, pec_boundary=False):
+    def add_port_on_rlc_component(
+        self, component: Optional[Union[str, Component]] = None, circuit_ports: bool = True, pec_boundary: bool = False
+    ) -> bool:
         """Deactivate RLC component and replace it with a circuit port.
         The circuit port supports only two-pin components.
 
@@ -840,7 +850,7 @@ class SourceExcitation:
             return True
         return False
 
-    def add_rlc_boundary(self, component=None, circuit_type=True):
+    def add_rlc_boundary(self, component: Optional[Union[str, Component]] = None, circuit_type: bool = True) -> bool:
         """Add RLC gap boundary on component and replace it with a circuit port.
         The circuit port supports only 2-pin components.
 
@@ -903,19 +913,25 @@ class SourceExcitation:
             rlc = GrpcRlc()
             if rlc_values[0]:
                 rlc.r_enabled = True
-                rlc.r = GrpcValue(rlc_values[0])
+                rlc.r = Value(rlc_values[0])
             if rlc_values[1]:
                 rlc.l_enabled = True
-                rlc.l = GrpcValue(rlc_values[1])
+                rlc.l = Value(rlc_values[1])
             if rlc_values[2]:
                 rlc.c_enabled = True
-                rlc.c = GrpcValue(rlc_values[2])
+                rlc.c = Value(rlc_values[2])
             rlc.is_parallel = component.is_parallel_rlc
             pos_pin_term.rlc_boundary = rlc
             self._logger.info("Component {} has been replaced by port".format(component.refdes))
             return True
 
-    def _create_pin_group_terminal(self, pingroup, isref=False, term_name=None, term_type="circuit"):
+    def _create_pin_group_terminal(
+        self,
+        pingroup: Union[str, "PinGroup"],
+        isref: bool = False,
+        term_name: Optional[str] = None,
+        term_type: str = "circuit",
+    ) -> Optional["PinGroupTerminal"]:
         """Creates an EDB pin group terminal from a given EDB pin group.
 
         Parameters
@@ -963,7 +979,13 @@ class SourceExcitation:
             pingroup_term.is_circuit_port = True
         return pingroup_term
 
-    def create_coax_port(self, padstackinstance, use_dot_separator=True, name=None, create_on_top=True):
+    def create_coax_port(
+        self,
+        padstackinstance: Union[PadstackInstance, int],
+        use_dot_separator: bool = True,
+        name: Optional[str] = None,
+        create_on_top: bool = True,
+    ) -> Optional[str]:
         """Create HFSS 3Dlayout coaxial lumped port on a pastack
         Requires to have solder ball defined before calling this method.
 
@@ -1030,10 +1052,16 @@ class SourceExcitation:
         )
         return port_name
 
-    def _port_exist(self, port_name):
+    def _port_exist(self, port_name: str) -> bool:
         return any(port for port in list(self._pedb.excitations.keys()) if port == port_name)
 
-    def _create_edge_terminal(self, prim_id, point_on_edge, terminal_name=None, is_ref=False):
+    def _create_edge_terminal(
+        self,
+        prim_id: Union[int, Primitive],
+        point_on_edge: List[float],
+        terminal_name: Optional[str] = None,
+        is_ref: bool = False,
+    ) -> Optional[GrpcEdgeTerminal]:
         """Create an edge terminal.
 
         Parameters
@@ -1068,7 +1096,13 @@ class SourceExcitation:
             layout=prim.layout, name=terminal_name, edges=pos_edge, net=prim.net, is_ref=is_ref
         )
 
-    def create_circuit_port_on_pin(self, pos_pin, neg_pin, impedance=50, port_name=None):
+    def create_circuit_port_on_pin(
+        self,
+        pos_pin: Union[str, PadstackInstance],
+        neg_pin: Union[str, PadstackInstance],
+        impedance: Union[int, float] = 50,
+        port_name: Optional[str] = None,
+    ) -> Optional[str]:
         """Create a circuit port on a pin.
 
         Parameters
@@ -1103,18 +1137,18 @@ class SourceExcitation:
 
     def _create_terminal_on_pins(
         self,
-        positive_pin,
-        negative_pin,
-        name=None,
-        use_pin_top_layer=True,
-        source_type="circuit_port",
-        impedance=50,
-        magnitude=0,
-        phase=0,
-        r=0,
-        l=0,
-        c=0,
-    ):
+        positive_pin: PadstackInstance,
+        negative_pin: PadstackInstance,
+        name: Optional[str] = None,
+        use_pin_top_layer: bool = True,
+        source_type: str = "circuit_port",
+        impedance: Union[int, float, str] = 50,
+        magnitude: Union[int, float, str] = 0,
+        phase: Union[int, float, str] = 0,
+        r: Union[int, float] = 0,
+        l: Union[int, float] = 0,
+        c: Union[int, float] = 0,
+    ) -> Optional[str]:
         """Create a terminal on pins.
 
         Parameters
@@ -1173,7 +1207,7 @@ class SourceExcitation:
         if source_type in ["circuit_port", "lumped_port"]:
             pos_terminal.boundary_type = GrpcBoundaryType.PORT
             neg_terminal.boundary_type = GrpcBoundaryType.PORT
-            pos_terminal.impedance = GrpcValue(impedance)
+            pos_terminal.impedance = Value(impedance)
             if source_type == "lumped_port":
                 pos_terminal.is_circuit_port = False
                 neg_terminal.is_circuit_port = False
@@ -1186,18 +1220,18 @@ class SourceExcitation:
         elif source_type == "current_source":
             pos_terminal.boundary_type = GrpcBoundaryType.CURRENT_SOURCE
             neg_terminal.boundary_type = GrpcBoundaryType.CURRENT_SOURCE
-            pos_terminal.source_amplitude = GrpcValue(magnitude)
-            pos_terminal.source_phase = GrpcValue(phase)
-            pos_terminal.impedance = GrpcValue(impedance)
+            pos_terminal.source_amplitude = Value(magnitude)
+            pos_terminal.source_phase = Value(phase)
+            pos_terminal.impedance = Value(impedance)
             pos_terminal.reference_terminal = neg_terminal
             pos_terminal.name = name
 
         elif source_type == "voltage_source":
             pos_terminal.boundary_type = GrpcBoundaryType.VOLTAGE_SOURCE
             neg_terminal.boundary_type = GrpcBoundaryType.VOLTAGE_SOURCE
-            pos_terminal.source_amplitude = GrpcValue(magnitude)
-            pos_terminal.impedance = GrpcValue(impedance)
-            pos_terminal.source_phase = GrpcValue(phase)
+            pos_terminal.source_amplitude = Value(magnitude)
+            pos_terminal.impedance = Value(impedance)
+            pos_terminal.source_phase = Value(phase)
             pos_terminal.reference_terminal = neg_terminal
             pos_terminal.name = name
 
@@ -1209,9 +1243,9 @@ class SourceExcitation:
             rlc.r_enabled = bool(r)
             rlc.l_enabled = bool(l)
             rlc.c_enabled = bool(c)
-            rlc.r = GrpcValue(r)
-            rlc.l = GrpcValue(l)
-            rlc.c = GrpcValue(c)
+            rlc.r = Value(r)
+            rlc.l = Value(l)
+            rlc.c = Value(c)
             pos_terminal.rlc_boundary_parameters = rlc
             pos_terminal.name = name
 
@@ -1220,7 +1254,14 @@ class SourceExcitation:
             return False
         return pos_terminal.name
 
-    def create_voltage_source_on_pin(self, pos_pin, neg_pin, voltage_value=0, phase_value=0, source_name=None):
+    def create_voltage_source_on_pin(
+        self,
+        pos_pin: Union[str, PadstackInstance],
+        neg_pin: Union[str, PadstackInstance],
+        voltage_value: Union[int, float] = 0,
+        phase_value: Union[int, float] = 0,
+        source_name: Optional[str] = None,
+    ) -> Optional[str]:
         """Create a voltage source.
 
         Parameters
@@ -1263,7 +1304,14 @@ class SourceExcitation:
             source_type="voltage_source",
         )
 
-    def create_current_source_on_pin(self, pos_pin, neg_pin, current_value=0, phase_value=0, source_name=None):
+    def create_current_source_on_pin(
+        self,
+        pos_pin: Union[str, PadstackInstance],
+        neg_pin: Union[str, PadstackInstance],
+        current_value: Union[int, float] = 0,
+        phase_value: Union[int, float] = 0,
+        source_name: Optional[str] = None,
+    ) -> Optional[str]:
         """Create a voltage source.
 
         Parameters
@@ -1306,7 +1354,13 @@ class SourceExcitation:
             source_type="current_source",
         )
 
-    def create_resistor_on_pin(self, pos_pin, neg_pin, rvalue=1, resistor_name=""):
+    def create_resistor_on_pin(
+        self,
+        pos_pin: Union[str, PadstackInstance],
+        neg_pin: Union[str, PadstackInstance],
+        rvalue: Union[int, float] = 1,
+        resistor_name: Optional[str] = "",
+    ) -> Optional[str]:
         """Create a Resistor boundary between two given pins..
 
         Parameters
@@ -1343,13 +1397,13 @@ class SourceExcitation:
 
     def create_circuit_port_on_net(
         self,
-        positive_component_name,
-        positive_net_name,
-        negative_component_name=None,
-        negative_net_name=None,
-        impedance=50,
-        port_name="",
-    ):
+        positive_component_name: str,
+        positive_net_name: str,
+        negative_component_name: str,
+        negative_net_name: Optional[str] = None,
+        impedance_value: Union[int, float] = 50,
+        port_name: Optional[str] = None,
+    ) -> Optional[str]:
         """Create a circuit port on a NET.
 
         It groups all pins belonging to the specified net and then applies the port on PinGroups.
@@ -1414,23 +1468,23 @@ class SourceExcitation:
             positive_pins=positive_pins,
             negatives_pins=negative_pins,
             name=port_name,
-            impedance=impedance,
+            impedance=impedance_value,
             source_type="circuit_port",
         )
 
     def create_pin_group_terminal(
         self,
-        positive_pins,
-        negatives_pins,
-        name=None,
-        impedance=50,
-        source_type="circuit_port",
-        magnitude=1.0,
-        phase=0,
-        r=0.0,
-        l=0.0,
-        c=0.0,
-    ):
+        positive_pins: Union[PadstackInstance, List[PadstackInstance]],
+        negatives_pins: Optional[Union[PadstackInstance, List[PadstackInstance]]] = None,
+        name: Optional[str] = None,
+        impedance: Union[int, float, str] = 50,
+        source_type: str = "circuit_port",
+        magnitude: Union[float, str] = 1.0,
+        phase: Union[float, str] = 0,
+        r: float = 0.0,
+        l: float = 0.0,
+        c: float = 0.0,
+    ) -> Optional[str]:
         """Create a pin group terminal.
 
         Parameters
@@ -1490,7 +1544,7 @@ class SourceExcitation:
             )
         if source_type in ["circuit_port", "lumped_port"]:
             pos_pingroup_terminal.boundary_type = GrpcBoundaryType.PORT
-            pos_pingroup_terminal.impedance = GrpcValue(impedance)
+            pos_pingroup_terminal.impedance = Value(impedance)
             if len(positive_pins) > 1 and len(negatives_pins) > 1:
                 if source_type == "lumped_port":
                     source_type = "circuit_port"
@@ -1506,16 +1560,16 @@ class SourceExcitation:
         elif source_type == "current_source":
             pos_pingroup_terminal.boundary_type = GrpcBoundaryType.CURRENT_SOURCE
             neg_pingroup_terminal.boundary_type = GrpcBoundaryType.CURRENT_SOURCE
-            pos_pingroup_terminal.source_amplitude = GrpcValue(magnitude)
-            pos_pingroup_terminal.source_phase = GrpcValue(phase)
+            pos_pingroup_terminal.source_amplitude = Value(magnitude)
+            pos_pingroup_terminal.source_phase = Value(phase)
             pos_pingroup_terminal.reference_terminal = neg_pingroup_terminal
             pos_pingroup_terminal.name = name
 
         elif source_type == "voltage_source":
             pos_pingroup_terminal.boundary_type = GrpcBoundaryType.VOLTAGE_SOURCE
             neg_pingroup_terminal.boundary_type = GrpcBoundaryType.VOLTAGE_SOURCE
-            pos_pingroup_terminal.source_amplitude = GrpcValue(magnitude)
-            pos_pingroup_terminal.source_phase = GrpcValue(phase)
+            pos_pingroup_terminal.source_amplitude = Value(magnitude)
+            pos_pingroup_terminal.source_phase = Value(phase)
             pos_pingroup_terminal.reference_terminal = neg_pingroup_terminal
             pos_pingroup_terminal.name = name
 
@@ -1527,9 +1581,9 @@ class SourceExcitation:
             Rlc.r_enabled = bool(r)
             Rlc.l_enabled = bool(l)
             Rlc.c_enabled = bool(c)
-            Rlc.r = GrpcValue(r)
-            Rlc.l = GrpcValue(l)
-            Rlc.c = GrpcValue(c)
+            Rlc.r = Value(r)
+            Rlc.l = Value(l)
+            Rlc.c = Value(c)
             pos_pingroup_terminal.rlc_boundary_parameters = Rlc
 
         elif source_type == "dc_terminal":
@@ -1538,7 +1592,7 @@ class SourceExcitation:
             pass
         return pos_pingroup_terminal.name
 
-    def _check_gnd(self, component_name):
+    def _check_gnd(self, component_name: str) -> Optional[str]:
         negative_net_name = None
         if self._pedb.nets.is_net_in_component(component_name, "GND"):
             negative_net_name = "GND"
@@ -1554,14 +1608,14 @@ class SourceExcitation:
 
     def create_voltage_source_on_net(
         self,
-        positive_component_name,
-        positive_net_name,
-        negative_component_name=None,
-        negative_net_name=None,
-        voltage_value=3.3,
-        phase_value=0,
-        source_name=None,
-    ):
+        positive_component_name: str,
+        positive_net_name: str,
+        negative_component_name: Optional[str] = None,
+        negative_net_name: Optional[str] = None,
+        voltage_value: Union[int, float] = 0,
+        phase_value: Union[int, float] = 0,
+        source_name: Optional[str] = None,
+    ) -> Optional[str]:
         """Create a voltage source.
 
         Parameters
@@ -1617,14 +1671,14 @@ class SourceExcitation:
 
     def create_current_source_on_net(
         self,
-        positive_component_name,
-        positive_net_name,
-        negative_component_name=None,
-        negative_net_name=None,
-        current_value=3.3,
-        phase_value=0,
-        source_name=None,
-    ):
+        positive_component_name: str,
+        positive_net_name: str,
+        negative_component_name: Optional[str] = None,
+        negative_net_name: Optional[str] = None,
+        current_value: Union[int, float] = 0,
+        phase_value: Union[int, float] = 0,
+        source_name: Optional[str] = None,
+    ) -> Optional[str]:
         """Create a voltage source.
 
         Parameters
@@ -1679,7 +1733,12 @@ class SourceExcitation:
             source_type="current_source",
         )
 
-    def create_coax_port_on_component(self, ref_des_list, net_list, delete_existing_terminal=False):
+    def create_coax_port_on_component(
+        self,
+        ref_des_list: Union[str, List[str]],
+        net_list: Union[str, List[str]],
+        delete_existing_terminal: bool = False,
+    ) -> List[str]:
         """Create a coaxial port on a component or component list on a net or net list.
            The name of the new coaxial port is automatically assigned.
 
@@ -1741,7 +1800,7 @@ class SourceExcitation:
                     self._logger.error(error)
         return coax
 
-    def check_before_terminal_assignement(self, connectable, delete_existing_terminal=False):
+    def check_before_terminal_assignement(self, connectable: Any, delete_existing_terminal: bool = False) -> bool:
         if not connectable:
             return False
         existing_terminals = [term for term in self._pedb.active_layout.terminals if term.id == connectable.id]
@@ -1763,15 +1822,15 @@ class SourceExcitation:
 
     def create_differential_wave_port(
         self,
-        positive_primitive_id,
-        positive_points_on_edge,
-        negative_primitive_id,
-        negative_points_on_edge,
-        port_name=None,
-        horizontal_extent_factor=5,
-        vertical_extent_factor=3,
-        pec_launch_width="0.01mm",
-    ):
+        positive_primitive_id: Union[int, Primitive],
+        positive_points_on_edge: List[float],
+        negative_primitive_id: Union[int, Primitive],
+        negative_points_on_edge: List[float],
+        port_name: Optional[str] = None,
+        horizontal_extent_factor: Union[int, float] = 5,
+        vertical_extent_factor: Union[int, float] = 3,
+        pec_launch_width: str = "0.01mm",
+    ) -> Tuple[str, BundleTerminal]:
         """Create a differential wave port.
 
         Parameters
@@ -1842,14 +1901,14 @@ class SourceExcitation:
 
     def create_wave_port(
         self,
-        prim_id,
-        point_on_edge,
-        port_name=None,
-        impedance=50,
-        horizontal_extent_factor=5,
-        vertical_extent_factor=3,
-        pec_launch_width="0.01mm",
-    ):
+        prim_id: Union[int, Primitive],
+        point_on_edge: List[float],
+        port_name: Optional[str] = None,
+        impedance: Union[int, float] = 50,
+        horizontal_extent_factor: Union[int, float] = 5,
+        vertical_extent_factor: Union[int, float] = 3,
+        pec_launch_width: str = "0.01mm",
+    ) -> Tuple[str, WavePort]:
         """Create a wave port.
 
         Parameters
@@ -1888,7 +1947,7 @@ class SourceExcitation:
         if isinstance(prim_id, Primitive):
             prim_id = prim_id.edb_uid
         pos_edge_term = self._create_edge_terminal(prim_id, point_on_edge, port_name)
-        pos_edge_term.impedance = GrpcValue(impedance)
+        pos_edge_term.impedance = Value(impedance)
         wave_port = WavePort(self._pedb, pos_edge_term)
         wave_port.horizontal_extent_factor = horizontal_extent_factor
         wave_port.vertical_extent_factor = vertical_extent_factor
@@ -1902,16 +1961,16 @@ class SourceExcitation:
 
     def create_edge_port_vertical(
         self,
-        prim_id,
-        point_on_edge,
-        port_name=None,
-        impedance=50,
-        reference_layer=None,
-        hfss_type="Gap",
-        horizontal_extent_factor=5,
-        vertical_extent_factor=3,
-        pec_launch_width="0.01mm",
-    ):
+        prim_id: int,
+        point_on_edge: List[float],
+        port_name: Optional[str] = None,
+        impedance: Union[int, float] = 50,
+        reference_layer: Optional[str] = None,
+        hfss_type: str = "Gap",
+        horizontal_extent_factor: Union[int, float] = 5,
+        vertical_extent_factor: Union[int, float] = 3,
+        pec_launch_width: str = "0.01mm",
+    ) -> str:
         """Create a vertical edge port.
 
         Parameters
@@ -1953,7 +2012,7 @@ class SourceExcitation:
         if not port_name:
             port_name = generate_unique_name("Terminal_")
         pos_edge_term = self._create_edge_terminal(prim_id, point_on_edge, port_name)
-        pos_edge_term.impedance = GrpcValue(impedance)
+        pos_edge_term.impedance = Value(impedance)
         if reference_layer:
             reference_layer = self._pedb.stackup.signal_layers[reference_layer]
             pos_edge_term.reference_layer = reference_layer
@@ -1980,14 +2039,14 @@ class SourceExcitation:
 
     def create_edge_port_horizontal(
         self,
-        prim_id,
-        point_on_edge,
-        ref_prim_id=None,
-        point_on_ref_edge=None,
-        port_name=None,
-        impedance=50,
-        layer_alignment="Upper",
-    ):
+        prim_id: Union[int, Primitive],
+        point_on_edge: List[float],
+        ref_prim_id: Optional[Union[int, Primitive]] = None,
+        point_on_ref_edge: Optional[List[float]] = None,
+        port_name: Optional[str] = None,
+        impedance: Union[int, float] = 50,
+        layer_alignment: str = "Upper",
+    ) -> Optional[EdgeTerminal]:
         """Create a horizontal edge port.
 
         Parameters
@@ -2025,7 +2084,7 @@ class SourceExcitation:
         pos_edge_term = self._create_edge_terminal(prim_id, point_on_edge, port_name)
         neg_edge_term = self._create_edge_terminal(ref_prim_id, point_on_ref_edge, port_name + "_ref", is_ref=True)
 
-        pos_edge_term.impedance = GrpcValue(impedance)
+        pos_edge_term.impedance = Value(impedance)
         pos_edge_term.reference_terminal = neg_edge_term
         if not layer_alignment == "Upper":
             layer_alignment = "Lower"
@@ -2040,7 +2099,12 @@ class SourceExcitation:
             return False
 
     def create_lumped_port_on_net(
-        self, nets=None, reference_layer=None, return_points_only=False, digit_resolution=6, at_bounding_box=True
+        self,
+        nets: Optional[Union[str, List[str]]] = None,
+        reference_layer: Optional[Union[str, StackupLayer]] = None,
+        return_points_only: bool = False,
+        digit_resolution: int = 6,
+        at_bounding_box: bool = True,
     ) -> bool:
         """Create an edge port on nets. This command looks for traces and polygons on the
         nets and tries to assign vertical lumped port.
@@ -2095,11 +2159,11 @@ class SourceExcitation:
             layout_extent_segments = [pt for pt in list(layout_bbox.arc_data) if pt.is_segment]
             first_pt = layout_extent_segments[0]
             layout_extent_points = [
-                [first_pt.start.x.value, first_pt.end.x.value],
-                [first_pt.Start.y.value, first_pt.end.y.value],
+                [Value(first_pt.start.x), Value(first_pt.end.x)],
+                [Value(first_pt.Start.y), Value(first_pt.end.y)],
             ]
             for segment in layout_extent_segments[1:]:
-                end_point = (segment.end.x.value, segment.end.y.value)
+                end_point = (Value(segment.end.x), Value(segment.end.y))
                 layout_extent_points[0].append(end_point[0])
                 layout_extent_points[1].append(end_point[1])
             for net in nets:
@@ -2110,8 +2174,8 @@ class SourceExcitation:
                     port_name = f"{net.name}_{path.id}"
                     for pt in trace_path_pts:
                         _pt = [
-                            round(pt.x.value, digit_resolution),
-                            round(pt.y.value, digit_resolution),
+                            round(Value(pt.x), digit_resolution),
+                            round(Value(pt.y), digit_resolution),
                         ]
                         if at_bounding_box:
                             if GeometryOperators.point_in_polygon(_pt, layout_extent_points) == 0:
@@ -2134,7 +2198,7 @@ class SourceExcitation:
                     for segment in poly_segment:
                         if (
                             GeometryOperators.point_in_polygon(
-                                [segment.mid_point.x.value, segment.mid_point.y.value], layout_extent_points
+                                [Value(segment.mid_point.x), Value(segment.mid_point.y)], layout_extent_points
                             )
                             == 0
                         ):
@@ -2152,8 +2216,11 @@ class SourceExcitation:
         return port_created
 
     def create_vertical_circuit_port_on_clipped_traces(
-        self, nets=None, reference_net=None, user_defined_extent=None
-    ) -> list[list[str]]:
+        self,
+        nets: Optional[Union[str, List[str], Net, List[Net]]] = None,
+        reference_net: Optional[Union[str, Net]] = None,
+        user_defined_extent: Optional[Union[List[float], GrpcPolygonData]] = None,
+    ) -> Union[List[List[str]], bool]:
         """Create an edge port on clipped signal traces.
 
         Parameters
@@ -2196,15 +2263,15 @@ class SourceExcitation:
                     _x = []
                     _y = []
                     for pt in _points:
-                        if pt.x.value < 1e100 and pt.y.value < 1e100:
-                            _x.append(pt.x.value)
-                            _y.append(pt.y.value)
+                        if Value(pt.x) < 1e100 and Value(pt.y) < 1e100:
+                            _x.append(Value(pt.x))
+                            _y.append(Value(pt.y))
                     user_defined_extent = [_x, _y]
             terminal_info = []
             for net in nets:
                 net_polygons = [prim for prim in self._pedb.modeler.primitives if prim.type in ["polygon", "rectangle"]]
                 for poly in net_polygons:
-                    mid_points = [[arc.midpoint.x.value, arc.midpoint.y.value] for arc in poly.arcs]
+                    mid_points = [[Value(arc.midpoint.x), Value(arc.midpoint.y)] for arc in poly.arcs]
                     for mid_point in mid_points:
                         if GeometryOperators.point_in_polygon(mid_point, user_defined_extent) == 0:
                             port_name = generate_unique_name(f"{poly.net_name}_{poly.id}")
@@ -2248,13 +2315,13 @@ class SourceExcitation:
 
     def create_bundle_wave_port(
         self,
-        primitives_id,
-        points_on_edge,
-        port_name=None,
-        horizontal_extent_factor=5,
-        vertical_extent_factor=3,
-        pec_launch_width="0.01mm",
-    ):
+        primitives_id: List[Union[int, Primitive]],
+        points_on_edge: List[List[float]],
+        port_name: Optional[str] = None,
+        horizontal_extent_factor: Union[int, float] = 5,
+        vertical_extent_factor: Union[int, float] = 3,
+        pec_launch_width: str = "0.01mm",
+    ) -> Tuple[str, BundleWavePort]:
         """Create a bundle wave port.
 
         Parameters
@@ -2308,7 +2375,7 @@ class SourceExcitation:
         _edb_bundle_terminal = BundleTerminal.create(terminals)
         return port_name, BundleWavePort(self._pedb, _edb_bundle_terminal)
 
-    def create_hfss_ports_on_padstack(self, pinpos, portname=None):
+    def create_hfss_ports_on_padstack(self, pinpos: PadstackInstance, portname: Optional[str] = None) -> bool:
         """Create an HFSS port on a padstack.
 
         Parameters
@@ -2343,7 +2410,7 @@ class SourceExcitation:
         else:
             return False
 
-    def get_ports_number(self):
+    def get_ports_number(self) -> int:
         """Return the total number of excitation ports in a layout.
 
         Parameters
@@ -2364,7 +2431,7 @@ class SourceExcitation:
         terms = [term for term in self._pedb.layout.terminals]
         return len([i for i in terms if not i.is_reference_terminal])
 
-    def get_point_terminal(self, name, net_name, location, layer) -> PointTerminal:
+    def get_point_terminal(self, name: str, net_name: str, location: List[float], layer: str) -> PointTerminal:
         """Place terminal between two points.
 
         Parameters
@@ -2394,7 +2461,14 @@ class SourceExcitation:
             layout=self._pedb.active_layout, name=name, net=net_name, layer=layer, point=location
         )
 
-    def create_rlc_boundary_on_pins(self, positive_pin=None, negative_pin=None, rvalue=0.0, lvalue=0.0, cvalue=0.0):
+    def create_rlc_boundary_on_pins(
+        self,
+        positive_pin: Optional[PadstackInstance] = None,
+        negative_pin: Optional[PadstackInstance] = None,
+        rvalue: float = 0.0,
+        lvalue: float = 0.0,
+        cvalue: float = 0.0,
+    ) -> Union[Terminal, bool]:
         """Create hfss rlc boundary on pins.
 
         Parameters
@@ -2435,9 +2509,9 @@ class SourceExcitation:
             rlc.r_enabled = True
             rlc.l_enabled = True
             rlc.c_enabled = True
-            rlc.r = GrpcValue(rvalue)
-            rlc.l = GrpcValue(lvalue)
-            rlc.c = GrpcValue(cvalue)
+            rlc.r = Value(rvalue)
+            rlc.l = Value(lvalue)
+            rlc.c = Value(cvalue)
             positive_pin_term.rlc_boundary_parameters = rlc
             term_name = f"{positive_pin.component.name}_{positive_pin.net.name}_{positive_pin.name}"
             positive_pin_term.name = term_name
@@ -2448,15 +2522,15 @@ class SourceExcitation:
 
     def create_edge_port_on_polygon(
         self,
-        polygon=None,
-        reference_polygon=None,
-        terminal_point=None,
-        reference_point=None,
-        reference_layer=None,
-        port_name=None,
-        port_impedance=50.0,
-        force_circuit_port=False,
-    ):
+        polygon: Optional[Primitive] = None,
+        reference_polygon: Optional[Primitive] = None,
+        terminal_point: Optional[List[float]] = None,
+        reference_point: Optional[List[float]] = None,
+        reference_layer: Optional[Union[str, StackupLayer]] = None,
+        port_name: Optional[str] = None,
+        port_impedance: Union[int, float] = 50.0,
+        force_circuit_port: bool = False,
+    ) -> Optional[str]:
         """Create lumped port between two edges from two different polygons. Can also create a vertical port when
         the reference layer name is only provided. When a port is created between two edge from two polygons which don't
         belong to the same layer, a circuit port will be automatically created instead of lumped. To enforce the circuit
@@ -2525,7 +2599,7 @@ class SourceExcitation:
             edge_term.is_circuit_port = False
 
         if port_impedance:
-            edge_term.impedance = GrpcValue(port_impedance)
+            edge_term.impedance = Value(port_impedance)
         edge_term.name = port_name
         if reference_polygon and reference_point:
             ref_edge = GrpcPrimitiveEdge.create(reference_polygon, reference_point)
@@ -2545,13 +2619,18 @@ class SourceExcitation:
                 ref_edge_term.is_circuit_port = False
 
             if port_impedance:
-                ref_edge_term.impedance = GrpcValue(port_impedance)
+                ref_edge_term.impedance = Value(port_impedance)
             edge_term.reference_terminal = ref_edge_term
         return True
 
     def create_port_between_pin_and_layer(
-        self, component_name=None, pins_name=None, layer_name=None, reference_net=None, impedance=50.0
-    ):
+        self,
+        component_name: Optional[str] = None,
+        pins_name: Optional[Union[str, List[str]]] = None,
+        layer_name: Optional[str] = None,
+        reference_net: Optional[str] = None,
+        impedance: Union[int, float] = 50.0,
+    ) -> bool:
         """Create circuit port between pin and a reference layer.
 
         Parameters
@@ -2607,7 +2686,7 @@ class SourceExcitation:
                             layout=pin.layout, net=pin.net, padstack_instance=pin, name=term_name, layer=start_layer
                         )
                         positive_terminal.boundary_type = GrpcBoundaryType.PORT
-                        positive_terminal.impedance = GrpcValue(impedance)
+                        positive_terminal.impedance = Value(impedance)
                         positive_terminal.Is_circuit_port = True
                         position = GrpcPointData(self._pedb.components.get_pin_position(pin))
                         negative_terminal = PointTerminal.create(
@@ -2618,7 +2697,7 @@ class SourceExcitation:
                             point=position,
                         )
                         negative_terminal.boundary_type = GrpcBoundaryType.PORT
-                        negative_terminal.impedance = GrpcValue(impedance)
+                        negative_terminal.impedance = Value(impedance)
                         negative_terminal.is_circuit_port = True
                         positive_terminal.reference_terminal = negative_terminal
                         self._logger.info("Port {} successfully created".format(term_name))
@@ -2630,7 +2709,11 @@ class SourceExcitation:
                     return terms
             return False
 
-    def create_current_source(self, terminal, ref_terminal):
+    def create_current_source(
+        self,
+        terminal: Union[PadstackInstanceTerminal, EdgeTerminal],
+        ref_terminal: Union[PadstackInstanceTerminal, EdgeTerminal],
+    ) -> bool:
         """Create a current source.
 
         Parameters
@@ -2668,8 +2751,13 @@ class SourceExcitation:
         return term
 
     def create_current_source_on_pin_group(
-        self, pos_pin_group_name, neg_pin_group_name, magnitude=1, phase=0, name=None
-    ):
+        self,
+        pos_pin_group_name: str,
+        neg_pin_group_name: str,
+        magnitude: Union[int, float] = 1,
+        phase: Union[int, float] = 0,
+        name: Optional[str] = None,
+    ) -> bool:
         """Create current source between two pin groups.
 
         Parameters
@@ -2707,7 +2795,11 @@ class SourceExcitation:
         pos_terminal.reference_terminal = neg_terminal
         return True
 
-    def create_voltage_source(self, terminal, ref_terminal):
+    def create_voltage_source(
+        self,
+        terminal: Union[PadstackInstanceTerminal, EdgeTerminal],
+        ref_terminal: Union[PadstackInstanceTerminal, EdgeTerminal],
+    ) -> bool:
         """Create a voltage source.
 
         Parameters
@@ -2745,8 +2837,14 @@ class SourceExcitation:
         return term
 
     def create_voltage_source_on_pin_group(
-        self, pos_pin_group_name, neg_pin_group_name, magnitude=1, phase=0, name=None, impedance=0.001
-    ):
+        self,
+        pos_pin_group_name: str,
+        neg_pin_group_name: str,
+        magnitude: Union[int, float] = 1,
+        phase: Union[int, float] = 0,
+        name: Optional[str] = None,
+        impedance: Union[int, float] = 0.001,
+    ) -> bool:
         """Create voltage source between two pin groups.
 
         Parameters
@@ -2789,7 +2887,7 @@ class SourceExcitation:
         pos_terminal.reference_terminal = neg_terminal
         return True
 
-    def create_voltage_probe(self, terminal, ref_terminal):
+    def create_voltage_probe(self, terminal: Terminal, ref_terminal: Terminal) -> Terminal:
         """Create a voltage probe.
 
         Parameters
@@ -2820,7 +2918,9 @@ class SourceExcitation:
         term.ref_terminal = ref_terminal
         return term
 
-    def create_voltage_probe_on_pin_group(self, probe_name, pos_pin_group_name, neg_pin_group_name, impedance=1000000):
+    def create_voltage_probe_on_pin_group(
+        self, probe_name: str, pos_pin_group_name: str, neg_pin_group_name: str, impedance: Union[int, float] = 1000000
+    ) -> bool:
         """Create voltage probe between two pin groups.
 
         Parameters
@@ -2859,11 +2959,8 @@ class SourceExcitation:
         return not pos_terminal.is_null
 
     def create_dc_terminal(
-        self,
-        component_name,
-        net_name,
-        source_name=None,
-    ):
+        self, component_name: str, net_name: str, source_name: Optional[str] = None
+    ) -> Optional[str]:
         """Create a dc terminal.
 
         Parameters
@@ -2872,7 +2969,6 @@ class SourceExcitation:
             Name of the positive component.
         net_name : str
             Name of the positive net.
-
         source_name : str, optional
             Name of the source. The default is ``""``.
 
@@ -2897,7 +2993,13 @@ class SourceExcitation:
             positive_pins=node_pin, name=source_name, source_type="dc_terminal", negatives_pins=None
         )
 
-    def create_circuit_port_on_pin_group(self, pos_pin_group_name, neg_pin_group_name, impedance=50, name=None):
+    def create_circuit_port_on_pin_group(
+        self,
+        pos_pin_group_name: str,
+        neg_pin_group_name: str,
+        impedance: Union[int, float] = 50,
+        name: Optional[str] = None,
+    ) -> bool:
         """Create a port between two pin groups.
 
         Parameters
@@ -2939,14 +3041,14 @@ class SourceExcitation:
 
     def place_voltage_probe(
         self,
-        name,
-        positive_net_name,
-        positive_location,
-        positive_layer,
-        negative_net_name,
-        negative_location,
-        negative_layer,
-    ):
+        name: str,
+        positive_net_name: str,
+        positive_location: List[float],
+        positive_layer: str,
+        negative_net_name: str,
+        negative_location: List[float],
+        negative_layer: str,
+    ) -> Terminal:
         """Place a voltage probe between two points.
 
         Parameters