prep-ic 0.1.0__py3-none-any.whl

prep_ic/__init__.py

@@ -0,0 +1,43 @@
+# SPDX-FileCopyrightText: 2026 Maximilian Golser and Simon Dorrer
+# SPDX-License-Identifier: Apache-2.0
+"""PREP-IC (Pinout, Ring and Early floorplan Planner for ICs): plan IC pad ring pinouts.
+
+Scripting API (no Qt needed)::
+
+    import prep_ic as prep
+
+    project = prep.load("chip.json")
+    project.sides["L"].append("VDDA [p]")
+    project.settings.std.pitch = 90
+    layout = project.layout()
+    print(layout.die_width, layout.die_height, layout.warnings)
+    prep.export_csv(project, "pins.csv")
+    prep.export_svg(project, "ring.svg")
+    prep.save(project, "chip.json")
+
+    project.settings.pdk = "ihp-sg13g2"          # see prep.pdk_names()
+    project.settings.package = "OP_QFN32_A4_FIT"  # see prep.package_names()
+    prep.export_librelane(project, "flow/padring")   # config part, pad_cfg.tcl, chip_top.sv, …
+"""
+
+# defined before the imports: submodules import them
+__version__ = "0.1.0"
+APP_NAME = "PREP-IC"
+
+from .formats.lef import read_lef
+from .formats.librelane import export_librelane, librelane_files
+from .formats.pinlist import export_csv
+from .formats.project_file import load, save
+from .formats.svg import export_svg, to_svg
+from .model import (SIDE_NAMES, SIDES, TYPE_NAMES, TYPES, Floorplan, Layout, Macro, PadSettings, Pin,
+                    Project, Settings, build_layout)
+from .model.chip import (add_missing_pads, align_macros, analyse, auto_rotate, move_line, optimize_pad_order, place_line,
+                         suggest_supply_pads, toggle_lock)
+from .model.chip import add_missing_pads as generate_pads
+from .model.pdk import get_package, get_pdk, package_names, pdk_names
+
+__all__ = ["APP_NAME", "add_missing_pads", "align_macros", "analyse", "auto_rotate", "move_line",
+           "optimize_pad_order", "place_line", "suggest_supply_pads", "toggle_lock", "SIDES", "SIDE_NAMES", "TYPES", "TYPE_NAMES", "Floorplan", "Layout", "Macro", "PadSettings",
+           "Pin", "Project", "Settings", "build_layout", "export_csv", "export_librelane", "export_svg",
+           "generate_pads", "get_package", "get_pdk", "librelane_files", "load", "package_names", "pdk_names",
+           "read_lef", "save", "to_svg"]

prep_ic/__main__.py

@@ -0,0 +1,7 @@
+# SPDX-FileCopyrightText: 2026 Maximilian Golser and Simon Dorrer
+# SPDX-License-Identifier: Apache-2.0
+import sys
+
+from .cli import main
+
+sys.exit(main())

prep_ic/cli.py

@@ -0,0 +1,60 @@
+# SPDX-FileCopyrightText: 2026 Maximilian Golser and Simon Dorrer
+# SPDX-License-Identifier: Apache-2.0
+"""Command line entry point. Without a subcommand the GUI starts.
+
+    prep-ic [PROJECT]
+    prep-ic export PROJECT [--csv FILE] [--svg FILE] [--librelane DIR]
+"""
+
+import argparse
+import sys
+
+from . import APP_NAME, __version__, export_csv, export_librelane, export_svg, load
+
+
+def _export(argv):
+    ap = argparse.ArgumentParser(prog="prep-ic export", description="Export a project without the GUI.")
+    ap.add_argument("project", help="project file (.json)")
+    ap.add_argument("--csv", metavar="FILE", help="write the pin list as CSV")
+    ap.add_argument("--svg", metavar="FILE", help="write the drawing as SVG")
+    ap.add_argument("--librelane", metavar="DIR",
+                    help="write the LibreLane pad ring files (needs a PDK in the project)")
+    args = ap.parse_args(argv)
+    if not (args.csv or args.svg or args.librelane):
+        ap.error("nothing to export, give --csv, --svg and/or --librelane")
+    try:
+        project = load(args.project)
+        if args.csv:
+            export_csv(project, args.csv)
+        if args.svg:
+            export_svg(project, args.svg)
+        if args.librelane:
+            for path in export_librelane(project, args.librelane, source=args.project):
+                print(f"wrote {path}")
+    except (OSError, ValueError) as e:
+        print(f"error: {e}", file=sys.stderr)
+        return 1
+    for w in project.layout().warnings:
+        print(f"warning: {w}", file=sys.stderr)
+    return 0
+
+
+def main(argv=None):
+    argv = sys.argv[1:] if argv is None else list(argv)
+    if argv and argv[0] == "export":
+        return _export(argv[1:])
+    ap = argparse.ArgumentParser(prog="prep-ic", description=f"{APP_NAME}: plan IC pad ring pinouts.",
+                                 epilog="Subcommand: 'prep-ic export -h' for exports without the GUI.")
+    ap.add_argument("project", nargs="?", help="project file (.json) to open")
+    ap.add_argument("--version", action="version", version=f"{APP_NAME} {__version__}")
+    args = ap.parse_args(argv)
+    try:
+        from .gui import run
+    except ImportError as e:
+        print(f"error: {e}", file=sys.stderr)
+        return 1
+    return run(args.project)
+
+
+if __name__ == "__main__":
+    sys.exit(main())

prep_ic/data/packages.json

@@ -0,0 +1,557 @@
+{
+ "_source": "EUROPRACTICE package library EP_PACKAGES_08022018.gds (cell names); pin numbering counter-clockwise, seen from the top",
+ "packages": [
+  {
+   "name": "OP_QFN16_A4_FIT",
+   "label": "QFN16 (OP_QFN16_A4_FIT)",
+   "pins": 16,
+   "segments": [
+    [
+     "L",
+     4
+    ],
+    [
+     "B",
+     4
+    ],
+    [
+     "R",
+     4
+    ],
+    [
+     "T",
+     4
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_QFN24_A4_FIT",
+   "label": "QFN24 (OP_QFN24_A4_FIT)",
+   "pins": 24,
+   "segments": [
+    [
+     "L",
+     6
+    ],
+    [
+     "B",
+     6
+    ],
+    [
+     "R",
+     6
+    ],
+    [
+     "T",
+     6
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_QFN32_A4_FIT",
+   "label": "QFN32 (OP_QFN32_A4_FIT)",
+   "pins": 32,
+   "segments": [
+    [
+     "L",
+     8
+    ],
+    [
+     "B",
+     8
+    ],
+    [
+     "R",
+     8
+    ],
+    [
+     "T",
+     8
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_QFN40_6x6mm_A4_FIT",
+   "label": "QFN40 (OP_QFN40_6x6mm_A4_FIT)",
+   "pins": 40,
+   "segments": [
+    [
+     "L",
+     10
+    ],
+    [
+     "B",
+     10
+    ],
+    [
+     "R",
+     10
+    ],
+    [
+     "T",
+     10
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_QFN48_A4_FIT",
+   "label": "QFN48 (OP_QFN48_A4_FIT)",
+   "pins": 48,
+   "segments": [
+    [
+     "L",
+     12
+    ],
+    [
+     "B",
+     12
+    ],
+    [
+     "R",
+     12
+    ],
+    [
+     "T",
+     12
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_QFN56_A4_FIT",
+   "label": "QFN56 (OP_QFN56_A4_FIT)",
+   "pins": 56,
+   "segments": [
+    [
+     "L",
+     14
+    ],
+    [
+     "B",
+     14
+    ],
+    [
+     "R",
+     14
+    ],
+    [
+     "T",
+     14
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_QFN64_9x9mm_A4_FIT",
+   "label": "QFN64 (OP_QFN64_9x9mm_A4_FIT)",
+   "pins": 64,
+   "segments": [
+    [
+     "L",
+     16
+    ],
+    [
+     "B",
+     16
+    ],
+    [
+     "R",
+     16
+    ],
+    [
+     "T",
+     16
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_QFN80_12x12mm_A4",
+   "label": "QFN80 (OP_QFN80_12x12mm_A4)",
+   "pins": 80,
+   "segments": [
+    [
+     "L",
+     20
+    ],
+    [
+     "B",
+     20
+    ],
+    [
+     "R",
+     20
+    ],
+    [
+     "T",
+     20
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_QFN88_10x10mm_A4",
+   "label": "QFN88 (OP_QFN88_10x10mm_A4)",
+   "pins": 88,
+   "segments": [
+    [
+     "L",
+     22
+    ],
+    [
+     "B",
+     22
+    ],
+    [
+     "R",
+     22
+    ],
+    [
+     "T",
+     22
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_QFN100_12x12mm_A4",
+   "label": "QFN100 (OP_QFN100_12x12mm_A4)",
+   "pins": 100,
+   "segments": [
+    [
+     "L",
+     25
+    ],
+    [
+     "B",
+     25
+    ],
+    [
+     "R",
+     25
+    ],
+    [
+     "T",
+     25
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "JLCC44_A4",
+   "label": "JLCC44 (JLCC44_A4)",
+   "pins": 44,
+   "segments": [
+    [
+     "T",
+     6
+    ],
+    [
+     "L",
+     11
+    ],
+    [
+     "B",
+     11
+    ],
+    [
+     "R",
+     11
+    ],
+    [
+     "T",
+     5
+    ]
+   ],
+   "pin1": "centre of the top side"
+  },
+  {
+   "name": "JLCC68L_A4",
+   "label": "JLCC68 (JLCC68L_A4)",
+   "pins": 68,
+   "segments": [
+    [
+     "T",
+     9
+    ],
+    [
+     "L",
+     17
+    ],
+    [
+     "B",
+     17
+    ],
+    [
+     "R",
+     17
+    ],
+    [
+     "T",
+     8
+    ]
+   ],
+   "pin1": "centre of the top side"
+  },
+  {
+   "name": "JLCC84_A4",
+   "label": "JLCC84 (JLCC84_A4)",
+   "pins": 84,
+   "segments": [
+    [
+     "T",
+     11
+    ],
+    [
+     "L",
+     21
+    ],
+    [
+     "B",
+     21
+    ],
+    [
+     "R",
+     21
+    ],
+    [
+     "T",
+     10
+    ]
+   ],
+   "pin1": "centre of the top side"
+  },
+  {
+   "name": "CLCC44_A4",
+   "label": "CLCC44 (CLCC44_A4)",
+   "pins": 44,
+   "segments": [
+    [
+     "T",
+     6
+    ],
+    [
+     "L",
+     11
+    ],
+    [
+     "B",
+     11
+    ],
+    [
+     "R",
+     11
+    ],
+    [
+     "T",
+     5
+    ]
+   ],
+   "pin1": "centre of the top side"
+  },
+  {
+   "name": "CLCC68L_A4",
+   "label": "CLCC68 (CLCC68L_A4)",
+   "pins": 68,
+   "segments": [
+    [
+     "T",
+     9
+    ],
+    [
+     "L",
+     17
+    ],
+    [
+     "B",
+     17
+    ],
+    [
+     "R",
+     17
+    ],
+    [
+     "T",
+     8
+    ]
+   ],
+   "pin1": "centre of the top side"
+  },
+  {
+   "name": "CLCC84_A4",
+   "label": "CLCC84 (CLCC84_A4)",
+   "pins": 84,
+   "segments": [
+    [
+     "T",
+     11
+    ],
+    [
+     "L",
+     21
+    ],
+    [
+     "B",
+     21
+    ],
+    [
+     "R",
+     21
+    ],
+    [
+     "T",
+     10
+    ]
+   ],
+   "pin1": "centre of the top side"
+  },
+  {
+   "name": "OP_SOIC16_A4",
+   "label": "SOIC16 (OP_SOIC16_A4)",
+   "pins": 16,
+   "segments": [
+    [
+     "L",
+     8
+    ],
+    [
+     "R",
+     8
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_SOIC20_A4",
+   "label": "SOIC20 (OP_SOIC20_A4)",
+   "pins": 20,
+   "segments": [
+    [
+     "L",
+     10
+    ],
+    [
+     "R",
+     10
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_SOIC24_A4",
+   "label": "SOIC24 (OP_SOIC24_A4)",
+   "pins": 24,
+   "segments": [
+    [
+     "L",
+     12
+    ],
+    [
+     "R",
+     12
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "OP_SOIC28_A4",
+   "label": "SOIC28 (OP_SOIC28_A4)",
+   "pins": 28,
+   "segments": [
+    [
+     "L",
+     14
+    ],
+    [
+     "R",
+     14
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "DIL16_A4",
+   "label": "DIL16 (DIL16_A4)",
+   "pins": 16,
+   "segments": [
+    [
+     "L",
+     8
+    ],
+    [
+     "R",
+     8
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "DIL24_A4",
+   "label": "DIL24 (DIL24_A4)",
+   "pins": 24,
+   "segments": [
+    [
+     "L",
+     12
+    ],
+    [
+     "R",
+     12
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "DIL28_A4_cav7800",
+   "label": "DIL28 (DIL28_A4_cav7800)",
+   "pins": 28,
+   "segments": [
+    [
+     "L",
+     14
+    ],
+    [
+     "R",
+     14
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "DIL40L_A4",
+   "label": "DIL40L (DIL40L_A4)",
+   "pins": 40,
+   "segments": [
+    [
+     "L",
+     20
+    ],
+    [
+     "R",
+     20
+    ]
+   ],
+   "pin1": "top of the left side"
+  },
+  {
+   "name": "DIL48L_A4",
+   "label": "DIL48L (DIL48L_A4)",
+   "pins": 48,
+   "segments": [
+    [
+     "L",
+     24
+    ],
+    [
+     "R",
+     24
+    ]
+   ],
+   "pin1": "top of the left side"
+  }
+ ]
+}