peakrdl-busdecoder 0.6.5__py3-none-any.whl → 0.6.6__py3-none-any.whl

peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py

@@ -47,37 +47,48 @@ class APB3Cpuif(BaseCpuif):
 
         return "\n".join(f"assign {kv[0]} = {kv[1]};" for kv in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
-                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
-                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+                fanin["cpuif_wr_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_wr_err"] = f"{node.inst_name}_fanin_err{array_idx}"
             else:
-                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
-
+                fanin["cpuif_wr_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_wr_err"] = self.signal("PSLVERR", node, "i")
         return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
                 fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
             else:
+                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
                 fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())

peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py

@@ -53,22 +53,32 @@ class APB3CpuifFlat(BaseCpuif):
 
         return "\n".join(f"assign {kv[0]} = {kv[1]};" for kv in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+            fanin["cpuif_wr_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_wr_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
             fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())

peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv

@@ -19,8 +19,8 @@ assign cpuif_rd_addr = {{cpuif.signal("PADDR")}};
 assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
 
 assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
-assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack;
-assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack | cpuif_wr_ack;
+assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_wr_err;
 
 //--------------------------------------------------------------------------
 // Fanout CPU Bus interface signals

peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py

@@ -50,37 +50,49 @@ class APB4Cpuif(BaseCpuif):
 
         return "\n".join(f"assign {kv[0]} = {kv[1]};" for kv in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
-                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
-                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+                fanin["cpuif_wr_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_wr_err"] = f"{node.inst_name}_fanin_err{array_idx}"
             else:
-                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+                fanin["cpuif_wr_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_wr_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
                 fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
             else:
+                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
                 fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())

peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py

@@ -55,22 +55,31 @@ class APB4CpuifFlat(BaseCpuif):
 
         return "\n".join(f"assign {kv[0]} = {kv[1]};" for kv in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
-
+            fanin["cpuif_wr_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_wr_err"] = self.signal("PSLVERR", node, "i")
         return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
             fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(f"{kv[0]} = {kv[1]};" for kv in fanin.items())

peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv

@@ -20,8 +20,8 @@ assign cpuif_wr_data = {{cpuif.signal("PWDATA")}};
 assign cpuif_wr_byte_en = {{cpuif.signal("PSTRB")}};
 
 assign {{cpuif.signal("PRDATA")}} = cpuif_rd_data;
-assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack;
-assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+assign {{cpuif.signal("PREADY")}} = cpuif_rd_ack | cpuif_wr_ack; 
+assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_wr_err;
 
 //--------------------------------------------------------------------------
 // Fanout CPU Bus interface signals

peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py

@@ -63,38 +63,50 @@ class AXI4LiteCpuif(BaseCpuif):
 
         return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
-                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
-                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+                fanin["cpuif_wr_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_wr_err"] = f"{node.inst_name}_fanin_err{array_idx}"
             else:
                 # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
-                fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
-                fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
+                fanin["cpuif_wr_ack"] = self.signal("BVALID", node, "i")
+                fanin["cpuif_wr_err"] = f"{self.signal('BRESP', node, 'i')}[1]"
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
             # Use intermediate signals for interface arrays to avoid
             # non-constant indexing of interface arrays in procedural blocks
             if self.is_interface and node.is_array and node.array_dimensions:
                 # Generate array index string [i0][i1]... for the intermediate signal
                 array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
                 fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
             else:
+                fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
+                fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
                 fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())

peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py

@@ -72,23 +72,33 @@ class AXI4LiteCpuifFlat(BaseCpuif):
 
         return "\n".join(f"assign {lhs} = {rhs};" for lhs, rhs in fanout.items())
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
-            fanin["cpuif_rd_ack"] = "'0"
-            fanin["cpuif_rd_err"] = "'0"
+            fanin["cpuif_wr_ack"] = "'0"
+            fanin["cpuif_wr_err"] = "'0"
+            if error:
+                fanin["cpuif_wr_ack"] = "'1"
+                fanin["cpuif_wr_err"] = "cpuif_wr_sel.cpuif_err"
         else:
             # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
-            fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
-            fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
+            fanin["cpuif_wr_ack"] = self.signal("BVALID", node, "i")
+            fanin["cpuif_wr_err"] = f"{self.signal('BRESP', node, 'i')}[1]"
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         fanin: dict[str, str] = {}
         if node is None:
+            fanin["cpuif_rd_ack"] = "'0"
+            fanin["cpuif_rd_err"] = "'0"
             fanin["cpuif_rd_data"] = "'0"
+            if error:
+                fanin["cpuif_rd_ack"] = "'1"
+                fanin["cpuif_rd_err"] = "cpuif_rd_sel.cpuif_err"
         else:
+            fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
+            fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
             fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())

peakrdl_busdecoder/cpuif/base_cpuif.py

@@ -110,10 +110,10 @@ class BaseCpuif:
     def fanout(self, node: AddressableNode, array_stack: deque[int]) -> str:
         raise NotImplementedError
 
-    def fanin(self, node: AddressableNode | None = None) -> str:
+    def fanin_wr(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         raise NotImplementedError
 
-    def readback(self, node: AddressableNode | None = None) -> str:
+    def fanin_rd(self, node: AddressableNode | None = None, *, error: bool = False) -> str:
         raise NotImplementedError
 
     def fanin_intermediate_assignments(

peakrdl_busdecoder/cpuif/fanin_gen.py

@@ -20,8 +20,8 @@ class FaninGenerator(BusDecoderListener):
 
         self._stack: deque[Body] = deque()
         cb = CombinationalBody()
-        cb += cpuif.fanin()
-        cb += cpuif.readback()
+        cb += cpuif.fanin_wr()
+        cb += cpuif.fanin_rd()
         self._stack.append(cb)
 
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
@@ -48,15 +48,13 @@ class FaninGenerator(BusDecoderListener):
                 self._stack.append(fb)
 
         ifb = IfBody()
-        with ifb.cm(
-            f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)} || cpuif_wr_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}"
-        ) as b:
-            b += self._cpuif.fanin(node)
+        with ifb.cm(f"cpuif_wr_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}") as b:
+            b += self._cpuif.fanin_wr(node)
         self._stack[-1] += ifb
 
         ifb = IfBody()
         with ifb.cm(f"cpuif_rd_sel.{get_indexed_path(self._cpuif.exp.ds.top_node, node)}") as b:
-            b += self._cpuif.readback(node)
+            b += self._cpuif.fanin_rd(node)
         self._stack[-1] += ifb
 
         return action
@@ -72,4 +70,14 @@ class FaninGenerator(BusDecoderListener):
         super().exit_AddressableComponent(node)
 
     def __str__(self) -> str:
+        wr_ifb = IfBody()
+        with wr_ifb.cm("cpuif_wr_sel.cpuif_err") as b:
+            self._cpuif.fanin_wr(error=True)
+        self._stack[-1] += wr_ifb
+
+        rd_ifb = IfBody()
+        with rd_ifb.cm("cpuif_rd_sel.cpuif_err") as b:
+            self._cpuif.fanin_rd(error=True)
+        self._stack[-1] += rd_ifb
+
         return "\n".join(map(str, self._stack))

{peakrdl_busdecoder-0.6.5.dist-info → peakrdl_busdecoder-0.6.6.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-busdecoder
-Version: 0.6.5
+Version: 0.6.6
 Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
 Author: Arnav Sacheti
 License: LGPLv3

{peakrdl_busdecoder-0.6.5.dist-info → peakrdl_busdecoder-0.6.6.dist-info}/RECORD

@@ -20,30 +20,30 @@ peakrdl_busdecoder/body/for_loop_body.py,sha256=lJYfDiB7MF9_mfbGEApoVHRViBCqpGRs
 peakrdl_busdecoder/body/if_body.py,sha256=S4oVS7yz04R1i-23W-aWpVcVZa5dW-H0FL_KnMy-Wsc,3261
 peakrdl_busdecoder/body/struct_body.py,sha256=74ItYoYD-GqEidxc-ncV5y8fzGoM47NI4GnnweclmS8,624
 peakrdl_busdecoder/cpuif/__init__.py,sha256=T8YrELGuOBIPgj1e86tNJ5tSCf7fXpPadqa71v5MEx8,59
-peakrdl_busdecoder/cpuif/base_cpuif.py,sha256=-5bI43pbcPVYhvS0AEYgMkCBxkhnqmx9jLMazzT0z5k,4985
-peakrdl_busdecoder/cpuif/fanin_gen.py,sha256=ioCxjj3V3X8rHssqwuI4p_U-LKpBalATW_Qshtt8j9U,2425
+peakrdl_busdecoder/cpuif/base_cpuif.py,sha256=RknbZXMFsBcjR6FyPzF3mD4_lPQZxRDpt-5Vwbj5ef8,5036
+peakrdl_busdecoder/cpuif/fanin_gen.py,sha256=QnbJ_rTCI1HqP7cIGDGbS0q8rBhDzM_7FWcYEMotjP8,2661
 peakrdl_busdecoder/cpuif/fanin_intermediate_gen.py,sha256=hfvMyyx5ajEzvop3dzV37dT6Jn9yjORFnUkMAT1034A,5271
 peakrdl_busdecoder/cpuif/fanout_gen.py,sha256=-kopGBHC07D9VreygfN0VubHGVVO51og4lAFq6B1oV8,1876
 peakrdl_busdecoder/cpuif/interface.py,sha256=0xp_4K6DZMGOePbFgLEOIaVemjMS5pnQp7izKmzgu4s,6462
 peakrdl_busdecoder/cpuif/apb3/__init__.py,sha256=Uq82IJHzlITUvjTuETvPpSzvLEYoairzzPKfPz7kuC4,119
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 peakrdl_busdecoder/cpuif/apb3/apb3_interface.py,sha256=PQwMtjETR9-c9S1BzjdWieCis2qoOfUyRQAWcD3ScyE,2170
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 peakrdl_busdecoder/cpuif/apb4/__init__.py,sha256=k4JCbIrKGT8hiRvWJDcqc5xx7j9i_xYgpXU70sNaLsc,119
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 peakrdl_busdecoder/cpuif/apb4/apb4_interface.py,sha256=dnVWHi1NZScIR7sLYVfxbJDrU-Fm221O1XvHMdpSyi4,2472
-peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv,sha256=woX7UBWvg_mtnrBKSel60p269d1sFgGelzgA5kISxew,2020
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 peakrdl_busdecoder/cpuif/axi4lite/__init__.py,sha256=5XuWfPK2jDzr6egKUDJFr8l3k3lW-feLIh-lN7Mo8Ks,145
-peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py,sha256=bSHP_xYczv30-F62wZYe3rqma458qi6sqSzLAKApiGE,5056
-peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py,sha256=47yz1o6yoGFyoIswdka946n_kkwsApUhqYO_xNKekR4,3868
+peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py,sha256=61Cvj2ndSOns61E0DfTo356k46owuNPSrusqs0FBM70,5770
+peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py,sha256=gzXmQX15e0OZcYaXDvXNqQhGLqSHM3qkGCs7qk_lNf8,4410
 peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_interface.py,sha256=EXW-nPJwMF_oCPdJ4XmreiLwhnpqSca9iViosh2rEXM,3721
 peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv,sha256=ketPrq715LSEs8Ar9ecXgnSe2AUAdQ70oNVmDbXc2Tc,3351
 peakrdl_busdecoder/udps/__init__.py,sha256=gPc74OMVWTIr5vgtFArzbhEyi1OYjllR3ZFwHJ8APaY,106
-peakrdl_busdecoder-0.6.5.dist-info/licenses/LICENSE,sha256=eAMIGRcnsTDZVr4qelHkJ49Rd_IiDY4_MVHU7N0UWSw,7646
-peakrdl_busdecoder-0.6.5.dist-info/METADATA,sha256=OVIXfBAAbfNLR-3lgk6QSMWaV-KecglM3m7KPPMUq7c,2797
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-peakrdl_busdecoder-0.6.5.dist-info/entry_points.txt,sha256=7Xzgt-C2F4cQu1kRLpZa0MbXSFFMC1SWEDnZkY0GH7s,73
-peakrdl_busdecoder-0.6.5.dist-info/top_level.txt,sha256=ZIYuTsl8cYby4g8tNR_JGzbYYTrG9mqYLSBqnY1Gpmk,19
-peakrdl_busdecoder-0.6.5.dist-info/RECORD,,
+peakrdl_busdecoder-0.6.6.dist-info/licenses/LICENSE,sha256=eAMIGRcnsTDZVr4qelHkJ49Rd_IiDY4_MVHU7N0UWSw,7646
+peakrdl_busdecoder-0.6.6.dist-info/METADATA,sha256=NBh_tp01j-ohVg_PgfGhDAqtHCGcA5yZl0yHgTPRZXM,2797
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+peakrdl_busdecoder-0.6.6.dist-info/RECORD,,

{peakrdl_busdecoder-0.6.5.dist-info → peakrdl_busdecoder-0.6.6.dist-info}/WHEEL

@@ -1,5 +1,5 @@
 Wheel-Version: 1.0
-Generator: setuptools (80.9.0)
+Generator: setuptools (80.10.2)
 Root-Is-Purelib: true
 Tag: py3-none-any