peakrdl-busdecoder 0.4.0__py3-none-any.whl → 0.6.0__py3-none-any.whl

peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py

@@ -35,15 +35,15 @@ class APB3CpuifFlat(BaseCpuif):
 
     def fanout(self, node: AddressableNode) -> str:
         fanout: dict[str, str] = {}
-        fanout[self.signal("PSEL", node)] = (
-            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+        fanout[self.signal("PSEL", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PENABLE", node)] = self.signal("PENABLE")
-        fanout[self.signal("PWRITE", node)] = (
-            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+        fanout[self.signal("PENABLE", node, "gi")] = self.signal("PENABLE")
+        fanout[self.signal("PWRITE", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PADDR", node)] = self.signal("PADDR")
-        fanout[self.signal("PWDATA", node)] = "cpuif_wr_data"
+        fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
+        fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
 
         return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
 
@@ -53,8 +53,8 @@ class APB3CpuifFlat(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node)
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node)
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
 
@@ -63,6 +63,6 @@ class APB3CpuifFlat(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("PRDATA", node)
+            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py

@@ -35,17 +35,17 @@ class APB4CpuifFlat(BaseCpuif):
 
     def fanout(self, node: AddressableNode) -> str:
         fanout: dict[str, str] = {}
-        fanout[self.signal("PSEL", node)] = (
-            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+        fanout[self.signal("PSEL", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}|cpuif_rd_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PENABLE", node)] = self.signal("PENABLE")
-        fanout[self.signal("PWRITE", node)] = (
-            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'i')}"
+        fanout[self.signal("PENABLE", node, "gi")] = self.signal("PENABLE")
+        fanout[self.signal("PWRITE", node, "gi")] = (
+            f"cpuif_wr_sel.{get_indexed_path(self.exp.ds.top_node, node, 'gi')}"
         )
-        fanout[self.signal("PADDR", node)] = self.signal("PADDR")
-        fanout[self.signal("PPROT", node)] = self.signal("PPROT")
-        fanout[self.signal("PWDATA", node)] = "cpuif_wr_data"
-        fanout[self.signal("PSTRB", node)] = "cpuif_wr_byte_en"
+        fanout[self.signal("PADDR", node, "gi")] = self.signal("PADDR")
+        fanout[self.signal("PPROT", node, "gi")] = self.signal("PPROT")
+        fanout[self.signal("PWDATA", node, "gi")] = "cpuif_wr_data"
+        fanout[self.signal("PSTRB", node, "gi")] = "cpuif_wr_byte_en"
 
         return "\n".join(map(lambda kv: f"assign {kv[0]} = {kv[1]};", fanout.items()))
 
@@ -55,8 +55,8 @@ class APB4CpuifFlat(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node)
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node)
+            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
 
@@ -65,6 +65,6 @@ class APB4CpuifFlat(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("PRDATA", node)
+            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))

peakrdl_busdecoder/cpuif/interface.py

@@ -1,10 +1,13 @@
 """Interface abstraction for handling flat and non-flat signal declarations."""
 
+import re
 from abc import ABC, abstractmethod
 from typing import TYPE_CHECKING
 
 from systemrdl.node import AddressableNode
 
+from ..utils import get_indexed_path
+
 if TYPE_CHECKING:
     from .base_cpuif import BaseCpuif
 
@@ -93,7 +96,6 @@ class SVInterface(Interface):
         indexer: str | int | None = None,
     ) -> str:
         """Generate SystemVerilog interface signal reference."""
-        from ..utils import get_indexed_path
 
         # SVInterface only supports string indexers (loop variable names like "i", "gi")
         if indexer is not None and not isinstance(indexer, str):
@@ -166,6 +168,13 @@ class FlatInterface(Interface):
 
         # Is an array
         if indexer is not None:
+            if isinstance(indexer, str):
+                indexed_path = get_indexed_path(node.parent, node, indexer, skip_kw_filter=True)
+                pattern = r"\[.*?\]"
+                indexes = re.findall(pattern, indexed_path)
+
+                return f"{base}_{signal}{''.join(indexes)}"
+
             return f"{base}_{signal}[{indexer}]"
         return f"{base}_{signal}[N_{node.inst_name.upper()}S]"
 

peakrdl_busdecoder/decode_logic_gen.py

@@ -70,7 +70,9 @@ class DecodeLogicGenerator(BusDecoderListener):
         # Avoid generating a redundant >= 0 comparison, which triggers Verilator warnings.
         if not (l_bound.value == 0 and len(l_bound_comp) == 1):
             predicates.append(lower_expr)
-        predicates.append(upper_expr)
+        # Avoid generating a redundant full-width < max comparison, which triggers Verilator warnings.
+        if not (u_bound.value == (1 << addr_width) and len(u_bound_comp) == 1):
+            predicates.append(upper_expr)
 
         return predicates
 

peakrdl_busdecoder/sv_int.py

@@ -1,3 +1,6 @@
+from typing import Literal
+
+
 class SVInt:
     def __init__(self, value: int, width: int | None = None) -> None:
         self.value = value
@@ -19,3 +22,27 @@ class SVInt:
             return SVInt(self.value + other.value, max(self.width, other.width))
         else:
             return SVInt(self.value + other.value, None)
+
+    def __sub__(self, other: "SVInt") -> "SVInt":
+        if self.width is not None and other.width is not None:
+            return SVInt(self.value - other.value, max(self.width, other.width))
+        else:
+            return SVInt(self.value - other.value, None)
+
+    def __len__(self) -> int:
+        if self.width is not None:
+            return self.width
+        else:
+            return self.value.bit_length()
+
+    def to_bytes(self, byteorder: Literal["little", "big"] = "little") -> bytes:
+        byte_length = (self.value.bit_length() + 7) // 8
+        return self.value.to_bytes(byte_length, byteorder)
+
+    def __eq__(self, other: object) -> bool:
+        if not isinstance(other, SVInt):
+            return NotImplemented
+        return self.value == other.value and self.width == other.width
+
+    def __hash__(self) -> int:
+        return hash((self.value, self.width))

{peakrdl_busdecoder-0.4.0.dist-info → peakrdl_busdecoder-0.6.0.dist-info}/METADATA

@@ -1,8 +1,8 @@
 Metadata-Version: 2.4
 Name: peakrdl-busdecoder
-Version: 0.4.0
+Version: 0.6.0
 Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
-Author: Alex Mykyta
+Author: Arnav Sacheti
 License: LGPLv3
 Project-URL: Source, https://github.com/arnavsacheti/PeakRDL-BusDecoder
 Project-URL: Tracker, https://github.com/arnavsacheti/PeakRDL-BusDecoder/issues
@@ -20,8 +20,8 @@ Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA
 Requires-Python: >=3.10
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: jinja2>=3.1.6
-Requires-Dist: systemrdl-compiler~=1.30.1
+Requires-Dist: jinja2~=3.1
+Requires-Dist: systemrdl-compiler~=1.30
 Provides-Extra: cli
 Requires-Dist: peakrdl-cli>=1.2.3; extra == "cli"
 Dynamic: license-file

{peakrdl_busdecoder-0.4.0.dist-info → peakrdl_busdecoder-0.6.0.dist-info}/RECORD

@@ -1,6 +1,6 @@
 peakrdl_busdecoder/__init__.py,sha256=zKSEa8EqCrZUtGoHCuZ0uNQVQMV2isVn47CgsDj5K48,75
 peakrdl_busdecoder/__peakrdl__.py,sha256=76kLBbSWVlKkCI5ESiID1aWVcQHr4sK32ujP5kna8xU,4601
-peakrdl_busdecoder/decode_logic_gen.py,sha256=MdZbOiW2YNudhD-Msl_5wgGhd3mMaBNhTpUl-bilgHs,5873
+peakrdl_busdecoder/decode_logic_gen.py,sha256=q4qSmufJI28eX75A532BOoNfIufljq3gHNLdqKbRqio,6060
 peakrdl_busdecoder/design_scanner.py,sha256=syD6IXAJWYdpq2PQPvUGflPjhR_pO35R46Ld5K5XZHQ,1562
 peakrdl_busdecoder/design_state.py,sha256=_zqgn2dQH2ozK63NwqRvPV7Bty7G-BAESu3yux2cJmI,4926
 peakrdl_busdecoder/exporter.py,sha256=ZkGBeK-c733a3Xyc2ZeiGbWgBnDDW_s9nc64QiEf6no,5356
@@ -10,7 +10,7 @@ peakrdl_busdecoder/module_tmpl.sv,sha256=Sjo05-g_oP48x0jCdEyOvpBjwYV3wiACESgaC7v
 peakrdl_busdecoder/package_tmpl.sv,sha256=E0_jYmXx1nEMb78WApbCvMWYlrAuNfSWB7Jw23UkBYU,852
 peakrdl_busdecoder/py.typed,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 peakrdl_busdecoder/struct_gen.py,sha256=UGNdGg-S6u2JRoDExP6Mt5h3bu01fP-gQ15FcwD9gNw,2334
-peakrdl_busdecoder/sv_int.py,sha256=W0utmnR4XCuj3FVb9OGmRZ7SwlgEyO-XghMfd1I3iGA,872
+peakrdl_busdecoder/sv_int.py,sha256=D57h4sgqnQWQtPw80OeDZk_i2_t2aOTsihmASB4NkGo,1788
 peakrdl_busdecoder/utils.py,sha256=Kdcee6bhubI5XVX20JQ3wo0qYJTknqrv4l8kxhSd7wI,2219
 peakrdl_busdecoder/validate_design.py,sha256=91yuWEzj0aAZ0eqzF1TF4N17yqG-D5oK5yYxDINlPms,8857
 peakrdl_busdecoder/body/__init__.py,sha256=ZFTs8xIxeLyasyabLtGp7kClmmLlJpqdKJ854pmvTJg,311
@@ -24,15 +24,15 @@ peakrdl_busdecoder/cpuif/base_cpuif.py,sha256=tSqBeV_eG5zvBaLltLY8qmJBhwuCym3rs_
 peakrdl_busdecoder/cpuif/fanin_gen.py,sha256=ioCxjj3V3X8rHssqwuI4p_U-LKpBalATW_Qshtt8j9U,2425
 peakrdl_busdecoder/cpuif/fanin_intermediate_gen.py,sha256=hfvMyyx5ajEzvop3dzV37dT6Jn9yjORFnUkMAT1034A,5271
 peakrdl_busdecoder/cpuif/fanout_gen.py,sha256=0-6eMzYbf25csHaRUJCsiyFz7lxS2Mdu0bXNm6e6cFI,1850
-peakrdl_busdecoder/cpuif/interface.py,sha256=tFObXG18ashLrXSWn5O1ZwA-VNg9CL6w9XWi3qKd1sY,6148
+peakrdl_busdecoder/cpuif/interface.py,sha256=4NYJHv2rr50YLm_eB9I89Y4XUckMD42ZtHskU0_Nm8o,6448
 peakrdl_busdecoder/cpuif/apb3/__init__.py,sha256=Uq82IJHzlITUvjTuETvPpSzvLEYoairzzPKfPz7kuC4,119
 peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py,sha256=iQDpHpv9HQQiBm9zHlUuSCaUysraFvHA25kt2XlpKmM,4248
-peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py,sha256=5_li9azFbFc0q9CLpqQNPvbcALsNlOBwV9ROHZuZ81c,2374
+peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py,sha256=az0u0YOIuB5Tk2Dq76hu1B_batkiE3phnJS8G4pGyho,2422
 peakrdl_busdecoder/cpuif/apb3/apb3_interface.py,sha256=hU0GUCZGYnvskmZU6NznMGgRJFliD360WgwhsQh9rqY,2147
 peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv,sha256=6et25KbiNkZBD1hxjSx0XZFUP9NnvVpixMSGtwJuwdA,1967
 peakrdl_busdecoder/cpuif/apb4/__init__.py,sha256=k4JCbIrKGT8hiRvWJDcqc5xx7j9i_xYgpXU70sNaLsc,119
 peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py,sha256=SnQ1wERBkk1yc4ZiE4z__Sp2441ljFJ7b7mxGPKoiFQ,4457
-peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py,sha256=JcQ7TfW2bWA9g_uCpsmEUNQfRikx5ZImhf2VSFGIdmw,2504
+peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py,sha256=rTLOYGdHLGD6aPs18Wb7R7gASnX1QnVpYQCotbrhP5U,2564
 peakrdl_busdecoder/cpuif/apb4/apb4_interface.py,sha256=Ln5jIBhCHbIYS5sxR5AjFVvcMYD_rw71VF6KqyyNUkg,2449
 peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv,sha256=jjzIbiNvsDeMQWOIo08TpeKbSP3NILQkP3gWdlcX9Ak,2310
 peakrdl_busdecoder/cpuif/axi4lite/__init__.py,sha256=5XuWfPK2jDzr6egKUDJFr8l3k3lW-feLIh-lN7Mo8Ks,145
@@ -41,9 +41,9 @@ peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py,sha256=M9f6-2XloH1UCwH
 peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_interface.py,sha256=eBs3RLGGvvQen4C6MR9RUZIHuTQEidYHG4NGxlYY1Bc,3702
 peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv,sha256=ketPrq715LSEs8Ar9ecXgnSe2AUAdQ70oNVmDbXc2Tc,3351
 peakrdl_busdecoder/udps/__init__.py,sha256=gPc74OMVWTIr5vgtFArzbhEyi1OYjllR3ZFwHJ8APaY,106
-peakrdl_busdecoder-0.4.0.dist-info/licenses/LICENSE,sha256=eAMIGRcnsTDZVr4qelHkJ49Rd_IiDY4_MVHU7N0UWSw,7646
-peakrdl_busdecoder-0.4.0.dist-info/METADATA,sha256=uGopMHm1NkeK7SFCfOHcvahKg3HcWiKY59S7ixTqBVE,2560
-peakrdl_busdecoder-0.4.0.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
-peakrdl_busdecoder-0.4.0.dist-info/entry_points.txt,sha256=7Xzgt-C2F4cQu1kRLpZa0MbXSFFMC1SWEDnZkY0GH7s,73
-peakrdl_busdecoder-0.4.0.dist-info/top_level.txt,sha256=ZIYuTsl8cYby4g8tNR_JGzbYYTrG9mqYLSBqnY1Gpmk,19
-peakrdl_busdecoder-0.4.0.dist-info/RECORD,,
+peakrdl_busdecoder-0.6.0.dist-info/licenses/LICENSE,sha256=eAMIGRcnsTDZVr4qelHkJ49Rd_IiDY4_MVHU7N0UWSw,7646
+peakrdl_busdecoder-0.6.0.dist-info/METADATA,sha256=GNPShOm8hPu8gRdvDCK6v5rQgKJIPuPUVeIyTfZf83U,2558
+peakrdl_busdecoder-0.6.0.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
+peakrdl_busdecoder-0.6.0.dist-info/entry_points.txt,sha256=7Xzgt-C2F4cQu1kRLpZa0MbXSFFMC1SWEDnZkY0GH7s,73
+peakrdl_busdecoder-0.6.0.dist-info/top_level.txt,sha256=ZIYuTsl8cYby4g8tNR_JGzbYYTrG9mqYLSBqnY1Gpmk,19
+peakrdl_busdecoder-0.6.0.dist-info/RECORD,,