peakrdl-busdecoder 0.2.0__py3-none-any.whl → 0.4.0__py3-none-any.whl

peakrdl_busdecoder/__peakrdl__.py

@@ -116,7 +116,9 @@ class Exporter(ExporterSubcommandPlugin):
             type=int,
             default=1,
             help="""Maximum depth for address decoder to descend into nested
-            addressable components. Default is 1.
+            addressable components. Value of 0 decodes all levels (infinite depth).
+            Value of 1 decodes only top-level children. Value of 2 decodes top-level
+            and one level deeper, etc. Default is 1.
             """,
         )
 

peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py

@@ -52,8 +52,16 @@ class APB3Cpuif(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+            else:
+                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
 
@@ -62,6 +70,23 @@ class APB3Cpuif(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
+            else:
+                fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def fanin_intermediate_assignments(
+        self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str
+    ) -> list[str]:
+        """Generate intermediate signal assignments for APB3 interface arrays."""
+        return [
+            f"assign {inst_name}_fanin_ready{array_idx} = {master_prefix}{indexed_path}.PREADY;",
+            f"assign {inst_name}_fanin_err{array_idx} = {master_prefix}{indexed_path}.PSLVERR;",
+            f"assign {inst_name}_fanin_data{array_idx} = {master_prefix}{indexed_path}.PRDATA;",
+        ]

peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv

@@ -26,6 +26,13 @@ assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpu
 // Fanout CPU Bus interface signals
 //--------------------------------------------------------------------------
 {{fanout|walk(cpuif=cpuif)}}
+{%- if cpuif.is_interface %}
+
+//--------------------------------------------------------------------------
+// Intermediate signals for interface array fanin
+//--------------------------------------------------------------------------
+{{fanin_intermediate|walk(cpuif=cpuif)}}
+{%- endif %}
 
 //--------------------------------------------------------------------------
 // Fanin CPU Bus interface signals

peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py

@@ -55,8 +55,16 @@ class APB4Cpuif(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
-            fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+            else:
+                fanin["cpuif_rd_ack"] = self.signal("PREADY", node, "i")
+                fanin["cpuif_rd_err"] = self.signal("PSLVERR", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
 
@@ -65,6 +73,23 @@ class APB4Cpuif(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
+            else:
+                fanin["cpuif_rd_data"] = self.signal("PRDATA", node, "i")
 
         return "\n".join(map(lambda kv: f"{kv[0]} = {kv[1]};", fanin.items()))
+
+    def fanin_intermediate_assignments(
+        self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str
+    ) -> list[str]:
+        """Generate intermediate signal assignments for APB4 interface arrays."""
+        return [
+            f"assign {inst_name}_fanin_ready{array_idx} = {master_prefix}{indexed_path}.PREADY;",
+            f"assign {inst_name}_fanin_err{array_idx} = {master_prefix}{indexed_path}.PSLVERR;",
+            f"assign {inst_name}_fanin_data{array_idx} = {master_prefix}{indexed_path}.PRDATA;",
+        ]

peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv

@@ -29,6 +29,13 @@ assign {{cpuif.signal("PSLVERR")}} = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpu
 // Fanout CPU Bus interface signals
 //--------------------------------------------------------------------------
 {{fanout|walk(cpuif=cpuif)}}
+{%- if cpuif.is_interface %}
+
+//--------------------------------------------------------------------------
+// Intermediate signals for interface array fanin
+//--------------------------------------------------------------------------
+{{fanin_intermediate|walk(cpuif=cpuif)}}
+{%- endif %}
 
 //--------------------------------------------------------------------------
 // Fanin CPU Bus interface signals

peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py

@@ -4,14 +4,14 @@ from systemrdl.node import AddressableNode
 
 from ...utils import get_indexed_path
 from ..base_cpuif import BaseCpuif
-from .axi4lite_interface import AXI4LiteSVInterface
+from .axi4_lite_interface import AXI4LiteSVInterface
 
 if TYPE_CHECKING:
     from ...exporter import BusDecoderExporter
 
 
 class AXI4LiteCpuif(BaseCpuif):
-    template_path = "axi4lite_tmpl.sv"
+    template_path = "axi4_lite_tmpl.sv"
 
     def __init__(self, exp: "BusDecoderExporter") -> None:
         super().__init__(exp)
@@ -68,9 +68,17 @@ class AXI4LiteCpuif(BaseCpuif):
             fanin["cpuif_rd_ack"] = "'0"
             fanin["cpuif_rd_err"] = "'0"
         else:
-            # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
-            fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
-            fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_ack"] = f"{node.inst_name}_fanin_ready{array_idx}"
+                fanin["cpuif_rd_err"] = f"{node.inst_name}_fanin_err{array_idx}"
+            else:
+                # Read side: ack comes from RVALID; err if RRESP[1] is set (SLVERR/DECERR)
+                fanin["cpuif_rd_ack"] = self.signal("RVALID", node, "i")
+                fanin["cpuif_rd_err"] = f"{self.signal('RRESP', node, 'i')}[1]"
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
 
@@ -79,6 +87,23 @@ class AXI4LiteCpuif(BaseCpuif):
         if node is None:
             fanin["cpuif_rd_data"] = "'0"
         else:
-            fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
+            # Use intermediate signals for interface arrays to avoid
+            # non-constant indexing of interface arrays in procedural blocks
+            if self.is_interface and node.is_array and node.array_dimensions:
+                # Generate array index string [i0][i1]... for the intermediate signal
+                array_idx = "".join(f"[i{i}]" for i in range(len(node.array_dimensions)))
+                fanin["cpuif_rd_data"] = f"{node.inst_name}_fanin_data{array_idx}"
+            else:
+                fanin["cpuif_rd_data"] = self.signal("RDATA", node, "i")
 
         return "\n".join(f"{lhs} = {rhs};" for lhs, rhs in fanin.items())
+
+    def fanin_intermediate_assignments(
+        self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str
+    ) -> list[str]:
+        """Generate intermediate signal assignments for AXI4-Lite interface arrays."""
+        return [
+            f"assign {inst_name}_fanin_ready{array_idx} = {master_prefix}{indexed_path}.RVALID;",
+            f"assign {inst_name}_fanin_err{array_idx} = {master_prefix}{indexed_path}.RRESP[1];",
+            f"assign {inst_name}_fanin_data{array_idx} = {master_prefix}{indexed_path}.RDATA;",
+        ]

peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py

@@ -4,7 +4,7 @@ from systemrdl.node import AddressableNode
 
 from ...utils import get_indexed_path
 from ..base_cpuif import BaseCpuif
-from .axi4lite_interface import AXI4LiteFlatInterface
+from .axi4_lite_interface import AXI4LiteFlatInterface
 
 if TYPE_CHECKING:
     from ...exporter import BusDecoderExporter
@@ -13,7 +13,7 @@ if TYPE_CHECKING:
 class AXI4LiteCpuifFlat(BaseCpuif):
     """Verilator-friendly variant that flattens the AXI4-Lite interface ports."""
 
-    template_path = "axi4lite_tmpl.sv"
+    template_path = "axi4_lite_tmpl.sv"
 
     def __init__(self, exp: "BusDecoderExporter") -> None:
         super().__init__(exp)

peakrdl_busdecoder/cpuif/axi4lite/{axi4lite_tmpl.sv → axi4_lite_tmpl.sv}

@@ -53,6 +53,13 @@ assign {{cpuif.signal("BRESP")}}  = (cpuif_wr_err | cpuif_wr_sel.cpuif_err | cpu
 // Fanout CPU Bus interface signals
 //--------------------------------------------------------------------------
 {{fanout|walk(cpuif=cpuif)}}
+{%- if cpuif.is_interface %}
+
+//--------------------------------------------------------------------------
+// Intermediate signals for interface array fanin
+//--------------------------------------------------------------------------
+{{fanin_intermediate|walk(cpuif=cpuif)}}
+{%- endif %}
 
 //--------------------------------------------------------------------------
 // Fanin CPU Bus interface signals

peakrdl_busdecoder/cpuif/base_cpuif.py

@@ -7,6 +7,7 @@ from systemrdl.node import AddressableNode
 
 from ..utils import clog2, get_indexed_path, is_pow2, roundup_pow2
 from .fanin_gen import FaninGenerator
+from .fanin_intermediate_gen import FaninIntermediateGenerator
 from .fanout_gen import FanoutGenerator
 
 if TYPE_CHECKING:
@@ -24,11 +25,7 @@ class BaseCpuif:
 
     @property
     def addressable_children(self) -> list[AddressableNode]:
-        return [
-            child
-            for child in self.exp.ds.top_node.children(unroll=self.unroll)
-            if isinstance(child, AddressableNode)
-        ]
+        return self.exp.ds.get_addressable_children_at_depth(unroll=self.unroll)
 
     @property
     def addr_width(self) -> int:
@@ -97,6 +94,7 @@ class BaseCpuif:
             "ds": self.exp.ds,
             "fanout": FanoutGenerator,
             "fanin": FaninGenerator,
+            "fanin_intermediate": FaninIntermediateGenerator,
         }
 
         template = jj_env.get_template(self.template_path)
@@ -116,3 +114,24 @@ class BaseCpuif:
 
     def readback(self, node: AddressableNode | None = None) -> str:
         raise NotImplementedError
+
+    def fanin_intermediate_assignments(
+        self, node: AddressableNode, inst_name: str, array_idx: str, master_prefix: str, indexed_path: str
+    ) -> list[str]:
+        """Generate intermediate signal assignments for interface array fanin.
+
+        This method should be implemented by cpuif classes that use interfaces.
+        It returns a list of assignment strings that copy signals from interface
+        arrays to intermediate unpacked arrays using constant (genvar) indexing.
+
+        Args:
+            node: The addressable node
+            inst_name: Instance name for the intermediate signals
+            array_idx: Array index string (e.g., "[gi0][gi1]")
+            master_prefix: Master interface prefix
+            indexed_path: Indexed path to the interface element
+
+        Returns:
+            List of assignment strings
+        """
+        return []  # Default: no intermediate assignments needed

peakrdl_busdecoder/cpuif/fanin_gen.py

@@ -27,6 +27,17 @@ class FaninGenerator(BusDecoderListener):
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
         action = super().enter_AddressableComponent(node)
 
+        should_generate = action == WalkerAction.SkipDescendants
+        if not should_generate and self._ds.max_decode_depth == 0:
+            for child in node.children():
+                if isinstance(child, AddressableNode):
+                    break
+            else:
+                should_generate = True
+
+        if not should_generate:
+            return action
+
         if node.array_dimensions:
             for i, dim in enumerate(node.array_dimensions):
                 fb = ForLoopBody(

peakrdl_busdecoder/cpuif/fanin_intermediate_gen.py

@@ -0,0 +1,142 @@
+"""Generator for intermediate signals needed for interface array fanin.
+
+When using SystemVerilog interface arrays, we cannot use variable indices
+in procedural blocks (like always_comb). This generator creates intermediate
+signals that copy from interface arrays using generate loops, which can then
+be safely accessed with variable indices in the fanin logic.
+"""
+
+from collections import deque
+from typing import TYPE_CHECKING
+
+from systemrdl.node import AddressableNode
+from systemrdl.walker import WalkerAction
+
+from ..body import Body, ForLoopBody
+from ..design_state import DesignState
+from ..listener import BusDecoderListener
+from ..utils import get_indexed_path
+
+if TYPE_CHECKING:
+    from .base_cpuif import BaseCpuif
+
+
+class FaninIntermediateGenerator(BusDecoderListener):
+    """Generates intermediate signals for interface array fanin."""
+
+    def __init__(self, ds: DesignState, cpuif: "BaseCpuif") -> None:
+        super().__init__(ds)
+        self._cpuif = cpuif
+        self._declarations: list[str] = []
+        self._stack: deque[Body] = deque()
+        self._stack.append(Body())
+
+    def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
+        action = super().enter_AddressableComponent(node)
+
+        # Only generate intermediates for interface arrays
+        # Check if cpuif has is_interface attribute (some implementations don't)
+        is_interface = getattr(self._cpuif, "is_interface", False)
+        if not is_interface or not node.array_dimensions:
+            return action
+
+        # Generate intermediate signal declarations
+        self._generate_intermediate_declarations(node)
+
+        # Generate assignment logic using generate loops
+        if node.array_dimensions:
+            for i, dim in enumerate(node.array_dimensions):
+                fb = ForLoopBody(
+                    "genvar",
+                    f"gi{i}",
+                    dim,
+                )
+                self._stack.append(fb)
+
+        # Generate assignments from interface array to intermediates
+        self._stack[-1] += self._generate_intermediate_assignments(node)
+
+        return action
+
+    def exit_AddressableComponent(self, node: AddressableNode) -> None:
+        is_interface = getattr(self._cpuif, "is_interface", False)
+        if is_interface and node.array_dimensions:
+            for _ in node.array_dimensions:
+                b = self._stack.pop()
+                if not b:
+                    continue
+                self._stack[-1] += b
+
+        super().exit_AddressableComponent(node)
+
+    def _generate_intermediate_declarations(self, node: AddressableNode) -> None:
+        """Generate intermediate signal declarations for a node."""
+        inst_name = node.inst_name
+
+        # Array dimensions should be checked before calling this function
+        if not node.array_dimensions:
+            return
+
+        # Calculate total array size
+        array_size = 1
+        for dim in node.array_dimensions:
+            array_size *= dim
+
+        # Create array dimension string
+        array_str = "".join(f"[{dim}]" for dim in node.array_dimensions)
+
+        # Generate declarations for each fanin signal
+        # For APB3/4: PREADY, PSLVERR, PRDATA
+        # These are the signals read in fanin
+        self._declarations.append(f"logic {inst_name}_fanin_ready{array_str};")
+        self._declarations.append(f"logic {inst_name}_fanin_err{array_str};")
+        self._declarations.append(
+            f"logic [{self._cpuif.data_width - 1}:0] {inst_name}_fanin_data{array_str};"
+        )
+
+    def _generate_intermediate_assignments(self, node: AddressableNode) -> str:
+        """Generate assignments from interface array to intermediate signals."""
+        inst_name = node.inst_name
+        indexed_path = get_indexed_path(node.parent, node, "gi", skip_kw_filter=True)
+
+        # Get master prefix - use getattr to avoid type errors
+        interface = getattr(self._cpuif, "_interface", None)
+        if interface is None:
+            return ""
+        master_prefix = interface.get_master_prefix()
+
+        # Array dimensions should be checked before calling this function
+        if not node.array_dimensions:
+            return ""
+
+        # Create indexed signal names for left-hand side
+        array_idx = "".join(f"[gi{i}]" for i in range(len(node.array_dimensions)))
+
+        # Delegate to cpuif to get the appropriate assignments for this interface type
+        assignments = self._cpuif.fanin_intermediate_assignments(
+            node, inst_name, array_idx, master_prefix, indexed_path
+        )
+
+        return "\n".join(assignments)
+
+    def get_declarations(self) -> str:
+        """Get all intermediate signal declarations."""
+        if not self._declarations:
+            return ""
+        return "\n".join(self._declarations)
+
+    def __str__(self) -> str:
+        """Get all intermediate signal declarations and assignments."""
+        if not self._declarations:
+            return ""
+
+        # Output declarations first
+        output = "\n".join(self._declarations)
+        output += "\n\n"
+
+        # Then output assignments
+        body_str = "\n".join(map(str, self._stack))
+        if body_str and body_str.strip():
+            output += body_str
+
+        return output

peakrdl_busdecoder/cpuif/fanout_gen.py

@@ -23,6 +23,17 @@ class FanoutGenerator(BusDecoderListener):
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
         action = super().enter_AddressableComponent(node)
 
+        should_generate = action == WalkerAction.SkipDescendants
+        if not should_generate and self._ds.max_decode_depth == 0:
+            for child in node.children():
+                if isinstance(child, AddressableNode):
+                    break
+            else:
+                should_generate = True
+
+        if not should_generate:
+            return action
+
         if node.array_dimensions:
             for i, dim in enumerate(node.array_dimensions):
                 fb = ForLoopBody(

peakrdl_busdecoder/decode_logic_gen.py

@@ -85,6 +85,20 @@ class DecodeLogicGenerator(BusDecoderListener):
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
         action = super().enter_AddressableComponent(node)
 
+        should_decode = action == WalkerAction.SkipDescendants
+
+        if not should_decode and self._ds.max_decode_depth == 0:
+            # When decoding all levels, treat leaf registers as decode boundary
+            for child in node.children():
+                if isinstance(child, AddressableNode):
+                    break
+            else:
+                should_decode = True
+
+        # Only generate select logic if we're at the decode boundary
+        if not should_decode:
+            return action
+
         conditions: list[str] = []
         conditions.extend(self.cpuif_addr_predicate(node))
         conditions.extend(self.cpuif_prot_predicate(node))
@@ -146,6 +160,8 @@ class DecodeLogicGenerator(BusDecoderListener):
     def __str__(self) -> str:
         body = self._decode_stack[-1]
         if isinstance(body, IfBody):
+            if len(body) == 0:
+                return f"{self._flavor.cpuif_select}.cpuif_err = 1'b1;"
             with body.cm(...) as b:
                 b += f"{self._flavor.cpuif_select}.cpuif_err = 1'b1;"
 

peakrdl_busdecoder/design_state.py

@@ -1,6 +1,6 @@
 from typing import TypedDict
 
-from systemrdl.node import AddrmapNode
+from systemrdl.node import AddressableNode, AddrmapNode
 from systemrdl.rdltypes.user_enum import UserEnum
 
 from .design_scanner import DesignScanner
@@ -72,3 +72,56 @@ class DesignState:
         if user_addr_width < self.addr_width:
             msg.fatal(f"User-specified address width shall be greater than or equal to {self.addr_width}.")
         self.addr_width = user_addr_width
+
+    def get_addressable_children_at_depth(self, unroll: bool = False) -> list[AddressableNode]:
+        """
+        Get addressable children at the decode boundary based on max_decode_depth.
+
+        max_decode_depth semantics:
+        - 0: decode all levels (return leaf registers)
+        - 1: decode only top level (return children at depth 1)
+        - 2: decode top + 1 level (return children at depth 2)
+        - N: decode down to depth N (return children at depth N)
+
+        Args:
+            unroll: Whether to unroll arrayed nodes
+
+        Returns:
+            List of addressable nodes at the decode boundary
+        """
+        from systemrdl.node import RegNode
+
+        def collect_nodes(node: AddressableNode, current_depth: int) -> list[AddressableNode]:
+            """Recursively collect nodes at the decode boundary."""
+            result: list[AddressableNode] = []
+
+            # For depth 0, collect all leaf registers
+            if self.max_decode_depth == 0:
+                # If this is a register, it's a leaf
+                if isinstance(node, RegNode):
+                    result.append(node)
+                else:
+                    # Recurse into children
+                    for child in node.children(unroll=unroll):
+                        if isinstance(child, AddressableNode):
+                            result.extend(collect_nodes(child, current_depth + 1))
+            else:
+                # For depth N, collect children at depth N
+                if current_depth == self.max_decode_depth:
+                    # We're at the decode boundary - return this node
+                    result.append(node)
+                elif current_depth < self.max_decode_depth:
+                    # We haven't reached the boundary yet - recurse
+                    for child in node.children(unroll=unroll):
+                        if isinstance(child, AddressableNode):
+                            result.extend(collect_nodes(child, current_depth + 1))
+
+            return result
+
+        # Start collecting from top node's children
+        nodes: list[AddressableNode] = []
+        for child in self.top_node.children(unroll=unroll):
+            if isinstance(child, AddressableNode):
+                nodes.extend(collect_nodes(child, 1))
+
+        return nodes

peakrdl_busdecoder/exporter.py

@@ -89,7 +89,9 @@ class BusDecoderExporter:
             interface. By default, arrayed nodes are kept as arrays.
         max_decode_depth: int
             Maximum depth for address decoder to descend into nested addressable
-            components. By default, the decoder descends 1 level deep.
+            components. A value of 0 decodes all levels (infinite depth). A value
+            of 1 decodes only top-level children. A value of 2 decodes top-level
+            and one level deeper, etc. By default, the decoder descends 1 level deep.
         """
         # If it is the root node, skip to top addrmap
         if isinstance(node, RootNode):

peakrdl_busdecoder/listener.py

@@ -15,7 +15,12 @@ class BusDecoderListener(RDLListener):
     def should_skip_node(self, node: AddressableNode) -> bool:
         """Check if this node should be skipped (not decoded)."""
         # Check if current depth exceeds max depth
-        if self._depth > self._ds.max_decode_depth:
+        # max_decode_depth semantics:
+        # - 0 means decode all levels (infinite)
+        # - 1 means decode only top level (depth 0)
+        # - 2 means decode top + 1 level (depth 0 and 1)
+        # - N means decode down to depth N-1
+        if self._ds.max_decode_depth > 0 and self._depth >= self._ds.max_decode_depth:
             return True
 
         # Check if this node only contains external addressable children

peakrdl_busdecoder/module_tmpl.sv

@@ -51,7 +51,7 @@ module {{ds.module_name}}
     //--------------------------------------------------------------------------
     always_comb begin
         // Default all write select signals to 0
-        cpuif_wr_sel = '0;
+        cpuif_wr_sel = '{default: '0};
 
         if (cpuif_req && cpuif_wr_en) begin
             // A write request is pending
@@ -66,7 +66,7 @@ module {{ds.module_name}}
     //--------------------------------------------------------------------------
     always_comb begin
         // Default all read select signals to 0
-        cpuif_rd_sel = '0;
+        cpuif_rd_sel = '{default: '0};
 
         if (cpuif_req && cpuif_rd_en) begin
             // A read request is pending

peakrdl_busdecoder/struct_gen.py

@@ -3,7 +3,7 @@ from collections import deque
 from systemrdl.node import AddressableNode
 from systemrdl.walker import WalkerAction
 
-from .body import Body, StructBody
+from .body import StructBody
 from .design_state import DesignState
 from .identifier_filter import kw_filter as kwf
 from .listener import BusDecoderListener
@@ -16,42 +16,53 @@ class StructGenerator(BusDecoderListener):
     ) -> None:
         super().__init__(ds)
 
-        self._stack: deque[Body] = deque()
-        self._stack.append(StructBody("cpuif_sel_t", True, True))
+        self._stack: list[StructBody] = [StructBody("cpuif_sel_t", True, False)]
+        self._struct_defs: list[StructBody] = []
+        self._created_struct_stack: deque[bool] = deque()  # Track if we created a struct for each node
 
     def enter_AddressableComponent(self, node: AddressableNode) -> WalkerAction | None:
         action = super().enter_AddressableComponent(node)
 
-        self._skip = False
-        if action == WalkerAction.SkipDescendants:
-            self._skip = True
+        skip = action == WalkerAction.SkipDescendants
 
-        if node.children():
+        # Only create nested struct if we're not skipping and node has addressable children
+        has_addressable_children = any(isinstance(child, AddressableNode) for child in node.children())
+        if has_addressable_children and not skip:
             # Push new body onto stack
-            body = StructBody(f"cpuif_sel_{node.inst_name}_t", True, True)
+            body = StructBody(f"cpuif_sel_{node.inst_name}_t", True, False)
             self._stack.append(body)
+            self._created_struct_stack.append(True)
+        else:
+            self._created_struct_stack.append(False)
 
         return action
 
     def exit_AddressableComponent(self, node: AddressableNode) -> None:
         type = "logic"
 
-        if node.children():
+        # Pop the created_struct flag
+        created_struct = self._created_struct_stack.pop()
+
+        # Only pop struct body if we created one
+        if created_struct:
             body = self._stack.pop()
-            if body and isinstance(body, StructBody) and not self._skip:
-                self._stack.appendleft(body)
+            if body:
+                self._struct_defs.append(body)
                 type = body.name
 
         name = kwf(node.inst_name)
 
         if node.array_dimensions:
             for dim in node.array_dimensions:
-                name = f"[{dim - 1}:0]{name}"
+                name = f"{name}[{dim}]"
 
         self._stack[-1] += f"{type} {name};"
 
         super().exit_AddressableComponent(node)
 
     def __str__(self) -> str:
-        self._stack[-1] += "logic cpuif_err;"
-        return "\n".join(map(str, self._stack))
+        if "logic cpuif_err;" not in self._stack[-1].lines:
+            self._stack[-1] += "logic cpuif_err;"
+        bodies = [str(body) for body in self._struct_defs]
+        bodies.append(str(self._stack[-1]))
+        return "\n".join(bodies)

{peakrdl_busdecoder-0.2.0.dist-info → peakrdl_busdecoder-0.4.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: peakrdl-busdecoder
-Version: 0.2.0
+Version: 0.4.0
 Summary: Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces
 Author: Alex Mykyta
 License: LGPLv3

{peakrdl_busdecoder-0.2.0.dist-info → peakrdl_busdecoder-0.4.0.dist-info}/RECORD

@@ -1,15 +1,15 @@
 peakrdl_busdecoder/__init__.py,sha256=zKSEa8EqCrZUtGoHCuZ0uNQVQMV2isVn47CgsDj5K48,75
-peakrdl_busdecoder/__peakrdl__.py,sha256=phRHXzr6_7zIpgQtwg4-aY4N_Da4PSuDXNRZUgG_eN0,4429
-peakrdl_busdecoder/decode_logic_gen.py,sha256=9ub2Vmx_vwONaUT9gCgLe6AixS0MTe7_q5foRBLdhG4,5256
+peakrdl_busdecoder/__peakrdl__.py,sha256=76kLBbSWVlKkCI5ESiID1aWVcQHr4sK32ujP5kna8xU,4601
+peakrdl_busdecoder/decode_logic_gen.py,sha256=MdZbOiW2YNudhD-Msl_5wgGhd3mMaBNhTpUl-bilgHs,5873
 peakrdl_busdecoder/design_scanner.py,sha256=syD6IXAJWYdpq2PQPvUGflPjhR_pO35R46Ld5K5XZHQ,1562
-peakrdl_busdecoder/design_state.py,sha256=xwos_gw9qoV2OpuAXP95Hn_dFyV5cFdROfVGS6OB7Z0,2617
-peakrdl_busdecoder/exporter.py,sha256=2Id5riWIR-AwvIU8fzjFC0NbIEyYzXk1YS6gXvEXMuA,5178
+peakrdl_busdecoder/design_state.py,sha256=_zqgn2dQH2ozK63NwqRvPV7Bty7G-BAESu3yux2cJmI,4926
+peakrdl_busdecoder/exporter.py,sha256=ZkGBeK-c733a3Xyc2ZeiGbWgBnDDW_s9nc64QiEf6no,5356
 peakrdl_busdecoder/identifier_filter.py,sha256=poSIS1BMscORxOuDX_nXqvdNzClhKASdAVv9aDM_aqA,3972
-peakrdl_busdecoder/listener.py,sha256=y62gXl_SOg_TGLYytw9xO5tRNe_kgv7dKbET_RlBpnQ,2233
-peakrdl_busdecoder/module_tmpl.sv,sha256=OoscLFeh6FwChaZOFEmJXbz0OjRklifNE5jpAs2ZqN0,2853
+peakrdl_busdecoder/listener.py,sha256=WZ2fma6oSpGGZwuP7Zcv1futWBalaeZeVZD7DX1KQz4,2509
+peakrdl_busdecoder/module_tmpl.sv,sha256=Sjo05-g_oP48x0jCdEyOvpBjwYV3wiACESgaC7viN00,2877
 peakrdl_busdecoder/package_tmpl.sv,sha256=E0_jYmXx1nEMb78WApbCvMWYlrAuNfSWB7Jw23UkBYU,852
 peakrdl_busdecoder/py.typed,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
-peakrdl_busdecoder/struct_gen.py,sha256=6SIx7Eds2xrcpAqDBLSbNhy21sTdqMrIHT0I8QZe-FU,1690
+peakrdl_busdecoder/struct_gen.py,sha256=UGNdGg-S6u2JRoDExP6Mt5h3bu01fP-gQ15FcwD9gNw,2334
 peakrdl_busdecoder/sv_int.py,sha256=W0utmnR4XCuj3FVb9OGmRZ7SwlgEyO-XghMfd1I3iGA,872
 peakrdl_busdecoder/utils.py,sha256=Kdcee6bhubI5XVX20JQ3wo0qYJTknqrv4l8kxhSd7wI,2219
 peakrdl_busdecoder/validate_design.py,sha256=91yuWEzj0aAZ0eqzF1TF4N17yqG-D5oK5yYxDINlPms,8857
@@ -20,29 +20,30 @@ peakrdl_busdecoder/body/for_loop_body.py,sha256=lJYfDiB7MF9_mfbGEApoVHRViBCqpGRs
 peakrdl_busdecoder/body/if_body.py,sha256=S4oVS7yz04R1i-23W-aWpVcVZa5dW-H0FL_KnMy-Wsc,3261
 peakrdl_busdecoder/body/struct_body.py,sha256=74ItYoYD-GqEidxc-ncV5y8fzGoM47NI4GnnweclmS8,624
 peakrdl_busdecoder/cpuif/__init__.py,sha256=T8YrELGuOBIPgj1e86tNJ5tSCf7fXpPadqa71v5MEx8,59
-peakrdl_busdecoder/cpuif/base_cpuif.py,sha256=QJ8F8VMZN57rNnLY8QHDmnPLaXR-CyCx2cNligPT5wU,4100
-peakrdl_busdecoder/cpuif/fanin_gen.py,sha256=K2fZbxGx4um05LG18eDRPqXBp7-wBXwPmddOTKbe_NI,2053
-peakrdl_busdecoder/cpuif/fanout_gen.py,sha256=mENigVzZ7edw3DMVkoXzyFQObV_r81hO4UP677IDlYk,1478
+peakrdl_busdecoder/cpuif/base_cpuif.py,sha256=tSqBeV_eG5zvBaLltLY8qmJBhwuCym3rs_q4mIJT6HI,5058
+peakrdl_busdecoder/cpuif/fanin_gen.py,sha256=ioCxjj3V3X8rHssqwuI4p_U-LKpBalATW_Qshtt8j9U,2425
+peakrdl_busdecoder/cpuif/fanin_intermediate_gen.py,sha256=hfvMyyx5ajEzvop3dzV37dT6Jn9yjORFnUkMAT1034A,5271
+peakrdl_busdecoder/cpuif/fanout_gen.py,sha256=0-6eMzYbf25csHaRUJCsiyFz7lxS2Mdu0bXNm6e6cFI,1850
 peakrdl_busdecoder/cpuif/interface.py,sha256=tFObXG18ashLrXSWn5O1ZwA-VNg9CL6w9XWi3qKd1sY,6148
 peakrdl_busdecoder/cpuif/apb3/__init__.py,sha256=Uq82IJHzlITUvjTuETvPpSzvLEYoairzzPKfPz7kuC4,119
-peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py,sha256=oskculfTBlXJWvJzcC0LeS5OH_s0GfOc0q7iuEvGzkw,2584
+peakrdl_busdecoder/cpuif/apb3/apb3_cpuif.py,sha256=iQDpHpv9HQQiBm9zHlUuSCaUysraFvHA25kt2XlpKmM,4248
 peakrdl_busdecoder/cpuif/apb3/apb3_cpuif_flat.py,sha256=5_li9azFbFc0q9CLpqQNPvbcALsNlOBwV9ROHZuZ81c,2374
 peakrdl_busdecoder/cpuif/apb3/apb3_interface.py,sha256=hU0GUCZGYnvskmZU6NznMGgRJFliD360WgwhsQh9rqY,2147
-peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv,sha256=DCiBUQEEZ5zAo71Wra9IiyHazLk98SugLF2MdjxNYWU,1679
+peakrdl_busdecoder/cpuif/apb3/apb3_tmpl.sv,sha256=6et25KbiNkZBD1hxjSx0XZFUP9NnvVpixMSGtwJuwdA,1967
 peakrdl_busdecoder/cpuif/apb4/__init__.py,sha256=k4JCbIrKGT8hiRvWJDcqc5xx7j9i_xYgpXU70sNaLsc,119
-peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py,sha256=2XklIUPYuBatWonL8Clni_hm8bq8pzHXWuyASBwd2EY,2793
+peakrdl_busdecoder/cpuif/apb4/apb4_cpuif.py,sha256=SnQ1wERBkk1yc4ZiE4z__Sp2441ljFJ7b7mxGPKoiFQ,4457
 peakrdl_busdecoder/cpuif/apb4/apb4_cpuif_flat.py,sha256=JcQ7TfW2bWA9g_uCpsmEUNQfRikx5ZImhf2VSFGIdmw,2504
 peakrdl_busdecoder/cpuif/apb4/apb4_interface.py,sha256=Ln5jIBhCHbIYS5sxR5AjFVvcMYD_rw71VF6KqyyNUkg,2449
-peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv,sha256=0Ql3ri9VVSJP9ODFpsparhUeKvWwjQgZDn0zQqmad7Q,2022
+peakrdl_busdecoder/cpuif/apb4/apb4_tmpl.sv,sha256=jjzIbiNvsDeMQWOIo08TpeKbSP3NILQkP3gWdlcX9Ak,2310
 peakrdl_busdecoder/cpuif/axi4lite/__init__.py,sha256=5XuWfPK2jDzr6egKUDJFr8l3k3lW-feLIh-lN7Mo8Ks,145
-peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py,sha256=QxgAKKN8tJ6gphWy2_ztfTEO92YDMXBgBQGEDfFbNJk,3326
-peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py,sha256=M9gR3aNuN3VE32iwBMVQuvBRxQ1g4zGW_YlT6Q9QDNw,3418
-peakrdl_busdecoder/cpuif/axi4lite/axi4lite_interface.py,sha256=eBs3RLGGvvQen4C6MR9RUZIHuTQEidYHG4NGxlYY1Bc,3702
-peakrdl_busdecoder/cpuif/axi4lite/axi4lite_tmpl.sv,sha256=Uz30kPye9wiAn1UIR9oNpahyn5KPrrAjbCI8_8-gxK8,3063
+peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py,sha256=_DpGXEFs77AFQAAspsGZxIxQuhehjPPFgL_9hLfuQeQ,5001
+peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif_flat.py,sha256=M9f6-2XloH1UCwHctolO4Um8BfAYiivWVM5PmAfksjY,3420
+peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_interface.py,sha256=eBs3RLGGvvQen4C6MR9RUZIHuTQEidYHG4NGxlYY1Bc,3702
+peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_tmpl.sv,sha256=ketPrq715LSEs8Ar9ecXgnSe2AUAdQ70oNVmDbXc2Tc,3351
 peakrdl_busdecoder/udps/__init__.py,sha256=gPc74OMVWTIr5vgtFArzbhEyi1OYjllR3ZFwHJ8APaY,106
-peakrdl_busdecoder-0.2.0.dist-info/licenses/LICENSE,sha256=eAMIGRcnsTDZVr4qelHkJ49Rd_IiDY4_MVHU7N0UWSw,7646
-peakrdl_busdecoder-0.2.0.dist-info/METADATA,sha256=xGwY74YR6s52NNmhUpNxQJ8MeK5p8UGG2PMUYDixAXg,2560
-peakrdl_busdecoder-0.2.0.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
-peakrdl_busdecoder-0.2.0.dist-info/entry_points.txt,sha256=7Xzgt-C2F4cQu1kRLpZa0MbXSFFMC1SWEDnZkY0GH7s,73
-peakrdl_busdecoder-0.2.0.dist-info/top_level.txt,sha256=ZIYuTsl8cYby4g8tNR_JGzbYYTrG9mqYLSBqnY1Gpmk,19
-peakrdl_busdecoder-0.2.0.dist-info/RECORD,,
+peakrdl_busdecoder-0.4.0.dist-info/licenses/LICENSE,sha256=eAMIGRcnsTDZVr4qelHkJ49Rd_IiDY4_MVHU7N0UWSw,7646
+peakrdl_busdecoder-0.4.0.dist-info/METADATA,sha256=uGopMHm1NkeK7SFCfOHcvahKg3HcWiKY59S7ixTqBVE,2560
+peakrdl_busdecoder-0.4.0.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
+peakrdl_busdecoder-0.4.0.dist-info/entry_points.txt,sha256=7Xzgt-C2F4cQu1kRLpZa0MbXSFFMC1SWEDnZkY0GH7s,73
+peakrdl_busdecoder-0.4.0.dist-info/top_level.txt,sha256=ZIYuTsl8cYby4g8tNR_JGzbYYTrG9mqYLSBqnY1Gpmk,19
+peakrdl_busdecoder-0.4.0.dist-info/RECORD,,