pcb-dfm 0.4.0__py3-none-any.whl

pcb_dfm/__init__.py

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+"""
+pcb_dfm package init.
+
+For now we keep the public API minimal so that internal modules
+like pcb_dfm.engine.* can be imported without pulling in extra
+dependencies or failing on missing symbols.
+"""
+
+import logging
+
+from .results import CheckResult, DfmResult
+
+# Library convention: attach a NullHandler so importing pcb_dfm never emits log
+# output on its own. Applications (and the CLI) opt in by configuring handlers.
+logging.getLogger("pcb_dfm").addHandler(logging.NullHandler())
+
+__all__ = [
+    "CheckResult",
+    "DfmResult",
+]

pcb_dfm/__main__.py

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+import sys
+
+from .cli.main import main
+
+if __name__ == "__main__":
+    sys.exit(main())

pcb_dfm/check_data/categories.json

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+{
+  "schema_version": "1.0.0",
+  "categories": [
+    {
+      "id": "copper_geometry",
+      "name": "Copper geometry",
+      "description": "Trace widths, clearances, annular rings, copper balancing, slivers and general photolithography or etch related constraints."
+    },
+    {
+      "id": "drill_via_integrity",
+      "name": "Drill and via integrity",
+      "description": "Drill sizes, via annular rings, aspect ratio, spacing, tenting, and other drill process constraints."
+    },
+    {
+      "id": "solder_mask_silkscreen",
+      "name": "Solder mask and silkscreen",
+      "description": "Mask openings, mask clearance, mask webbing, silkscreen printability, and mask defined pad constraints."
+    },
+    {
+      "id": "fabrication_stackup",
+      "name": "Fabrication stackup",
+      "description": "Dielectric thickness, material specs, layer registration, impedance controlled structures, and copper to edge constraints."
+    },
+    {
+      "id": "mechanical_outline",
+      "name": "Mechanical and outline",
+      "description": "Board outline, milling, slots, corner radii, tabs, mousebites, and mechanical drill features."
+    },
+    {
+      "id": "assembly",
+      "name": "Assembly",
+      "description": "Component spacing, polarity, reflow considerations, paste area, tombstoning, and wave solder constraints."
+    },
+    {
+      "id": "thermal_power",
+      "name": "Thermal and power integrity",
+      "description": "Thermal reliefs, copper areas for heat dissipation, plane fragmentation, and via in pad thermal management."
+    },
+    {
+      "id": "high_speed_si",
+      "name": "High speed and signal integrity",
+      "description": "Differential pair spacing and skew, return path continuity, stub length, and crosstalk prediction."
+    },
+    {
+      "id": "fab_process_compatibility",
+      "name": "Fabrication process compatibility",
+      "description": "Non standard hole types, missing tooling, silkscreen issues, and aperture definition errors."
+    },
+    {
+      "id": "yield_prediction",
+      "name": "Yield prediction",
+      "description": "Quantitative estimates of etch margin, drill wander tolerance, and plating thickness uniformity."
+    }
+  ]
+}

pcb_dfm/check_data/checks/acid_trap_angle.json

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+{
+  "id": "acid_trap_angle",
+  "category_id": "copper_geometry",
+  "name": "Minimum copper corner angle",
+  "description": "Detect acute copper angles that could create acid traps during etching.",
+  "what_it_measures": "Smallest internal copper corner angle found in traces and pours.",
+  "metric": {
+    "kind": "angle",
+    "units": "deg",
+    "preferred_direction": "maximize",
+    "target": { "min": 90.0 },
+    "limits": { "min": 60.0 },
+    "scale_min": 45.0,
+    "scale_max": 135.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["trace", "plane"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "binary",
+    "pass_threshold": 100,
+    "weight": 0.5
+  }
+}

pcb_dfm/check_data/checks/aperture_definition_errors.json

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+{
+  "id": "aperture_definition_errors",
+  "category_id": "fab_process_compatibility",
+  "name": "Aperture definition errors",
+  "description": "Detect missing, ambiguous, or conflicting aperture definitions in Gerber or artwork data.",
+  "what_it_measures": "Count of aperture related errors detected in the image data.",
+  "metric": {
+    "kind": "count",
+    "units": "errors",
+    "preferred_direction": "minimize",
+    "target": { "max": 0.0 },
+    "limits": { "max": 1.0 },
+    "scale_min": 0.0,
+    "scale_max": 10.0
+  },
+  "severity_default": "error",
+  "applies_to": ["other"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "binary",
+    "pass_threshold": 100,
+    "weight": 1.0
+  }
+}

pcb_dfm/check_data/checks/backdrill_stub_length.json

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+{
+  "id": "backdrill_stub_length",
+  "category_id": "drill_via_integrity",
+  "name": "Backdrill stub length",
+  "description": "Limit remaining via stubs after backdrilling on high speed nets.",
+  "what_it_measures": "Maximum residual stub length on backdrilled vias.",
+  "metric": {
+    "kind": "distance",
+    "units": "mm",
+    "preferred_direction": "minimize",
+    "target": { "max": 0.3 },
+    "limits": { "max": 0.5 },
+    "scale_min": 0.0,
+    "scale_max": 1.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["via", "net"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "binary",
+    "pass_threshold": 100,
+    "weight": 0.6
+  }
+}

pcb_dfm/check_data/checks/component_to_component_spacing.json

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+{
+  "id": "component_to_component_spacing",
+  "category_id": "assembly",
+  "name": "Component to component spacing",
+  "description": "Ensure enough clearance between components for placement, soldering, and rework.",
+  "what_it_measures": "Minimum body to body distance between any two components.",
+  "metric": {
+    "kind": "distance",
+    "units": "mm",
+    "preferred_direction": "maximize",
+    "target": { "min": 0.5 },
+    "limits": { "min": 0.25 },
+    "scale_min": 0.1,
+    "scale_max": 2.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["component"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 1.0
+  }
+}

pcb_dfm/check_data/checks/copper_density_balance.json

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+{
+  "id": "copper_density_balance",
+  "category_id": "copper_geometry",
+  "name": "Copper density balance",
+  "description": "Check for large copper density variations that can cause warp, bow, or etch non uniformity.",
+  "what_it_measures": "Copper fill percentage in sliding windows across each layer.",
+  "metric": {
+    "kind": "percent",
+    "units": "%",
+    "preferred_direction": "target_range",
+    "target": { "min": 30.0, "max": 70.0 },
+    "limits": { "min": 10.0, "max": 90.0 },
+    "scale_min": 0.0,
+    "scale_max": 100.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["plane", "trace"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 1.0
+  }
+}

pcb_dfm/check_data/checks/copper_sliver_width.json

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+{
+  "id": "copper_sliver_width",
+  "category_id": "copper_geometry",
+  "name": "Copper sliver width",
+  "description": "Detect very thin isolated copper slivers that may peel or over etch.",
+  "what_it_measures": "Narrowest width of isolated copper islands or spokes.",
+  "metric": {
+    "kind": "distance",
+    "units": "um",
+    "preferred_direction": "maximize",
+    "target": { "min": 150.0 },
+    "limits": { "min": 100.0 },
+    "scale_min": 50.0,
+    "scale_max": 250.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["trace", "plane"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "binary",
+    "pass_threshold": 100,
+    "weight": 0.7
+  }
+}

pcb_dfm/check_data/checks/copper_thermal_area.json

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+{
+  "id": "copper_thermal_area",
+  "category_id": "thermal_power",
+  "name": "Copper thermal area",
+  "description": "Ensure heat generating components have enough copper area for dissipation.",
+  "what_it_measures": "Total copper area connected to each thermally significant pad or component.",
+  "metric": {
+    "kind": "area",
+    "units": "mm2",
+    "preferred_direction": "maximize",
+    "target": { "min": 50.0 },
+    "limits": { "min": 20.0 },
+    "scale_min": 0.0,
+    "scale_max": 200.0
+  },
+  "severity_default": "info",
+  "applies_to": ["component", "pad_smt", "plane"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 0.5
+  }
+}

pcb_dfm/check_data/checks/copper_to_edge_distance.json

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+{
+  "id": "copper_to_edge_distance",
+  "category_id": "fabrication_stackup",
+  "name": "Copper to edge distance",
+  "description": "Verify that copper features are sufficiently pulled back from the board outline.",
+  "what_it_measures": "Smallest distance from any copper feature to the final routed board edge.",
+  "metric": {
+    "kind": "distance",
+    "units": "um",
+    "preferred_direction": "maximize",
+    "target": { "min": 250.0 },
+    "limits": { "min": 200.0 },
+    "scale_min": 100.0,
+    "scale_max": 500.0
+  },
+  "severity_default": "error",
+  "applies_to": ["trace", "plane", "pad_smt", "pad_tht"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "binary",
+    "pass_threshold": 100,
+    "weight": 1.0
+  }
+}

pcb_dfm/check_data/checks/crosstalk_estimate.json

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+{
+  "id": "crosstalk_estimate",
+  "category_id": "high_speed_si",
+  "name": "Crosstalk risk estimate",
+  "description": "Estimate near end and far end crosstalk risk based on parallelism and spacing between sensitive nets.",
+  "what_it_measures": "Estimated coupling coefficient or risk percentage for critical net pairs.",
+  "metric": {
+    "kind": "percent",
+    "units": "%",
+    "preferred_direction": "minimize",
+    "target": { "max": 10.0 },
+    "limits": { "max": 25.0 },
+    "scale_min": 0.0,
+    "scale_max": 100.0
+  },
+  "severity_default": "info",
+  "applies_to": ["trace", "net"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 0.7
+  }
+}

pcb_dfm/check_data/checks/dielectric_thickness_uniformity.json

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+{
+  "id": "dielectric_thickness_uniformity",
+  "category_id": "fabrication_stackup",
+  "name": "Dielectric thickness uniformity",
+  "description": "Check deviation between designed and nominal dielectric thicknesses.",
+  "what_it_measures": "Deviation of dielectric thickness from target for each core or prepreg layer.",
+  "metric": {
+    "kind": "distance",
+    "units": "um",
+    "preferred_direction": "minimize",
+    "target": { "max": 10.0 },
+    "limits": { "max": 25.0 },
+    "scale_min": 0.0,
+    "scale_max": 50.0
+  },
+  "severity_default": "info",
+  "applies_to": ["stackup"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 0.5
+  }
+}

pcb_dfm/check_data/checks/diff_pair_skew.json

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+{
+  "id": "diff_pair_skew",
+  "category_id": "high_speed_si",
+  "name": "Differential pair skew",
+  "description": "Limit length mismatch between members of each differential pair.",
+  "what_it_measures": "Maximum length difference between traces in each diff pair.",
+  "metric": {
+    "kind": "distance",
+    "units": "mm",
+    "preferred_direction": "minimize",
+    "target": { "max": 0.5 },
+    "limits": { "max": 1.0 },
+    "scale_min": 0.0,
+    "scale_max": 2.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["trace", "net"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 1.0
+  }
+}

pcb_dfm/check_data/checks/diff_pair_spacing.json

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+{
+  "id": "diff_pair_spacing",
+  "category_id": "high_speed_si",
+  "name": "Differential pair spacing",
+  "description": "Check that differential pairs maintain their specified intra pair spacing.",
+  "what_it_measures": "Deviation of actual gap between paired traces from the nominal design spacing.",
+  "metric": {
+    "kind": "distance",
+    "units": "um",
+    "preferred_direction": "minimize",
+    "target": { "max": 25.0 },
+    "limits": { "max": 50.0 },
+    "scale_min": 0.0,
+    "scale_max": 100.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["trace", "net"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 0.8
+  }
+}

pcb_dfm/check_data/checks/drill_aspect_ratio.json

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+{
+  "id": "drill_aspect_ratio",
+  "category_id": "drill_via_integrity",
+  "name": "Drill aspect ratio",
+  "description": "Limit the aspect ratio of plated through holes for reliable plating.",
+  "what_it_measures": "Maximum board_thickness / drill_diameter across all plated holes.",
+  "metric": {
+    "kind": "ratio",
+    "units": ":1",
+    "preferred_direction": "minimize",
+    "target": { "max": 8.0 },
+    "limits": { "max": 10.0 },
+    "scale_min": 4.0,
+    "scale_max": 12.0
+  },
+  "severity_default": "error",
+  "applies_to": ["via", "pad_tht"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "binary",
+    "pass_threshold": 100,
+    "weight": 1.0
+  }
+}

pcb_dfm/check_data/checks/drill_to_drill_spacing.json

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+{
+  "id": "drill_to_drill_spacing",
+  "category_id": "drill_via_integrity",
+  "name": "Drill to drill spacing",
+  "description": "Check minimum spacing between drilled holes to avoid breakout and tool wander issues.",
+  "what_it_measures": "Smallest edge to edge distance between any two holes.",
+  "metric": {
+    "kind": "distance",
+    "units": "um",
+    "preferred_direction": "maximize",
+    "target": { "min": 200.0 },
+    "limits": { "min": 150.0 },
+    "scale_min": 100.0,
+    "scale_max": 400.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["drill", "via", "pad_tht"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "binary",
+    "pass_threshold": 100,
+    "weight": 0.8
+  }
+}

pcb_dfm/check_data/checks/drill_wander_budget.json

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+{
+  "id": "drill_wander_budget",
+  "category_id": "yield_prediction",
+  "name": "Drill wander budget",
+  "description": "Estimate remaining tolerance before drill wander causes breakout or annular ring violations.",
+  "what_it_measures": "Minimum additional radial displacement allowed before drill breakout would occur.",
+  "metric": {
+    "kind": "distance",
+    "units": "um",
+    "preferred_direction": "maximize",
+    "target": { "min": 50.0 },
+    "limits": { "min": 25.0 },
+    "scale_min": 0.0,
+    "scale_max": 100.0
+  },
+  "severity_default": "info",
+  "applies_to": ["via", "pad_tht", "drill"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 0.9
+  }
+}

pcb_dfm/check_data/checks/etch_compensation_margin.json

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+{
+  "id": "etch_compensation_margin",
+  "category_id": "yield_prediction",
+  "name": "Etch compensation margin",
+  "description": "Estimate margin between copper feature sizes and the minimum etch process capability.",
+  "what_it_measures": "Average and worst case margin between actual feature widths or spaces and the process limit values.",
+  "metric": {
+    "kind": "percent",
+    "units": "%",
+    "preferred_direction": "maximize",
+    "target": { "min": 20.0 },
+    "limits": { "min": 0.0 },
+    "scale_min": -20.0,
+    "scale_max": 50.0
+  },
+  "severity_default": "info",
+  "applies_to": ["trace", "plane", "pad_smt", "pad_tht"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 1.0
+  }
+}

pcb_dfm/check_data/checks/fillet_radius_milling.json

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+{
+  "id": "fillet_radius_milling",
+  "category_id": "mechanical_outline",
+  "name": "Internal corner radius for milling",
+  "description": "Check that internal corners respect the minimum corner radius dictated by milling tools.",
+  "what_it_measures": "Smallest internal corner radius along routed board outlines and cutouts.",
+  "metric": {
+    "kind": "distance",
+    "units": "mm",
+    "preferred_direction": "maximize",
+    "target": { "min": 0.4 },
+    "limits": { "min": 0.3 },
+    "scale_min": 0.2,
+    "scale_max": 1.0
+  },
+  "severity_default": "info",
+  "applies_to": ["board_outline", "mechanical"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "binary",
+    "pass_threshold": 100,
+    "weight": 0.4
+  }
+}

pcb_dfm/check_data/checks/highspeed_stub_length.json

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+{
+  "id": "highspeed_stub_length",
+  "category_id": "high_speed_si",
+  "name": "High speed stub length",
+  "description": "Check that stubs on high speed nets are short enough to avoid significant reflections.",
+  "what_it_measures": "Maximum length of unterminated stubs on nets classified as high speed.",
+  "metric": {
+    "kind": "distance",
+    "units": "mm",
+    "preferred_direction": "minimize",
+    "target": { "max": 5.0 },
+    "limits": { "max": 10.0 },
+    "scale_min": 0.0,
+    "scale_max": 20.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["trace", "net"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 0.9
+  }
+}

pcb_dfm/check_data/checks/impedance_control.json

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+{
+  "id": "impedance_control",
+  "category_id": "fabrication_stackup",
+  "name": "Impedance control",
+  "description": "Compare realized impedance of controlled impedance traces to their targets.",
+  "what_it_measures": "Percentage deviation of calculated trace impedance from specified target impedance.",
+  "metric": {
+    "kind": "percent",
+    "units": "%",
+    "preferred_direction": "minimize",
+    "target": { "max": 8.0 },
+    "limits": { "max": 10.0 },
+    "scale_min": 0.0,
+    "scale_max": 20.0
+  },
+  "severity_default": "warning",
+  "applies_to": ["trace", "stackup", "net"],
+  "scoring": {
+    "enabled": true,
+    "strategy": "linear",
+    "pass_threshold": 80,
+    "weight": 1.0
+  }
+}