oscura 0.5.0__py3-none-any.whl → 0.5.1__py3-none-any.whl

oscura/__init__.py

@@ -46,7 +46,7 @@ Example:
 For more information, see https://github.com/oscura-re/oscura
 """
 
-__version__ = "0.5.0"
+__version__ = "0.5.1"
 __author__ = "Oscura Contributors"
 
 # Core types

oscura/analyzers/digital/__init__.py

@@ -52,17 +52,9 @@ from oscura.analyzers.digital.edges import (
 from oscura.analyzers.digital.extraction import (
     LOGIC_FAMILIES,
     detect_edges,
-    detect_logic_family,
-    detect_open_collector,
     get_logic_threshold,
     to_digital,
 )
-from oscura.analyzers.digital.ic_database import (
-    IC_DATABASE,
-    ICTiming,
-    identify_ic,
-    validate_ic_timing,
-)
 from oscura.analyzers.digital.quality import (
     Glitch,
     NoiseMarginResult,
@@ -105,37 +97,13 @@ from oscura.analyzers.digital.timing import (
     skew,
     slew_rate,
 )
-from oscura.analyzers.digital.timing_paths import (
-    ICStage,
-    SetupHoldAnalysis,
-    TimingPathResult,
-    analyze_setup_hold,
-    analyze_timing_path,
-    calculate_timing_budget,
-    find_critical_paths,
-)
-from oscura.analyzers.digital.vintage import (
-    REPLACEMENT_DATABASE,
-    analyze_vintage_logic,
-)
-from oscura.analyzers.digital.vintage_result import (
-    BOMEntry,
-    ICIdentificationResult,
-    ModernReplacementIC,
-    VintageLogicAnalysisResult,
-)
 
 __all__ = [
-    # IC Database
-    "IC_DATABASE",
     # Extraction
     "LOGIC_FAMILIES",
-    "REPLACEMENT_DATABASE",
     "AdaptiveThresholdResult",
     # Adaptive Thresholds (RE-THR-001)
     "AdaptiveThresholder",
-    # Vintage Logic Analysis
-    "BOMEntry",
     # Clock Recovery (DSP-002)
     "BaudRateResult",
     # Bus Decoding (DSP-003)
@@ -157,10 +125,6 @@ __all__ = [
     "EdgeTimingViolation",
     # Quality
     "Glitch",
-    "ICIdentificationResult",
-    "ICStage",
-    "ICTiming",
-    "ModernReplacementIC",
     # Multi-Level Logic (RE-THR-002)
     "MultiLevelDetector",
     "MultiLevelResult",
@@ -168,25 +132,18 @@ __all__ = [
     # Signal Quality (DSP-005)
     "NoiseMargins",
     "ParallelBusConfig",
-    "SetupHoldAnalysis",
     "SignalIntegrityReport",
     "SignalQualityAnalyzer",
     "SimpleQualityMetrics",
     "ThresholdConfig",
     "TimingConstraint",
-    "TimingPathResult",
     "TimingViolation",
     "TransitionMetrics",
-    "VintageLogicAnalysisResult",
     "Violation",
     "align_by_trigger",
-    "analyze_setup_hold",
     "analyze_signal_integrity",
-    "analyze_timing_path",
-    "analyze_vintage_logic",
     "apply_adaptive_threshold",
     "calculate_threshold_snr",
-    "calculate_timing_budget",
     "check_timing_constraints",
     "classify_edge_quality",
     "correlate_channels",
@@ -196,14 +153,10 @@ __all__ = [
     "detect_edges",
     "detect_edges_advanced",
     "detect_glitches",
-    "detect_logic_family",
     "detect_multi_level",
-    "detect_open_collector",
     "detect_violations",
-    "find_critical_paths",
     "get_logic_threshold",
     "hold_time",
-    "identify_ic",
     "interpolate_edge_time",
     "measure_clock_jitter",
     "measure_edge_timing",
@@ -221,5 +174,4 @@ __all__ = [
     "skew",
     "slew_rate",
     "to_digital",
-    "validate_ic_timing",
 ]

oscura/analyzers/digital/extraction.py

@@ -25,7 +25,6 @@ if TYPE_CHECKING:
 # Standard logic family threshold constants
 # Reference: Various IC manufacturer datasheets
 LOGIC_FAMILIES: dict[str, dict[str, float]] = {
-    # Modern logic families (5V)
     "TTL": {
         "VIL_max": 0.8,  # Maximum input low voltage
         "VIH_min": 2.0,  # Minimum input high voltage
@@ -75,63 +74,6 @@ LOGIC_FAMILIES: dict[str, dict[str, float]] = {
         "VOH_min": 1.1,
         "VCC": 1.2,
     },
-    # Vintage logic families (1960s-1970s)
-    "ECL": {
-        "VIL_max": -1.475,  # ECL 10K series
-        "VIH_min": -1.105,
-        "VOL_max": -1.630,  # Typical -1.63V
-        "VOH_min": -0.980,  # Typical -0.98V
-        "VCC": 0.0,  # Ground-referenced
-        "VEE": -5.2,  # Negative supply
-        "differential": True,  # Differential signaling
-    },
-    "ECL_100K": {
-        "VIL_max": -1.810,  # ECL 100K series (faster)
-        "VIH_min": -1.620,
-        "VOL_max": -1.950,
-        "VOH_min": -1.650,
-        "VCC": 0.0,
-        "VEE": -5.2,
-        "differential": True,
-    },
-    "RTL": {
-        "VIL_max": 0.4,  # Resistor-Transistor Logic
-        "VIH_min": 0.9,
-        "VOL_max": 0.2,
-        "VOH_min": 3.6,  # Typical 3.6V high output
-        "VCC": 3.6,  # 3.6V supply common
-    },
-    "DTL": {
-        "VIL_max": 0.5,  # Diode-Transistor Logic
-        "VIH_min": 2.0,
-        "VOL_max": 0.4,
-        "VOH_min": 4.0,  # Typical 4V high output
-        "VCC": 5.0,
-    },
-    "MOS": {
-        "VIL_max": -3.0,  # P-channel MOS (negative logic)
-        "VIH_min": -10.0,
-        "VOL_max": -0.5,
-        "VOH_min": -11.5,
-        "VCC": 0.0,  # Ground
-        "VDD": -12.0,  # Negative supply
-    },
-    "PMOS": {
-        "VIL_max": -3.0,  # PMOS (4000 series at -12V)
-        "VIH_min": -9.0,
-        "VOL_max": -0.5,
-        "VOH_min": -11.5,
-        "VCC": 0.0,
-        "VDD": -12.0,
-    },
-    "NMOS": {
-        "VIL_max": 1.5,  # NMOS (positive logic, 12V)
-        "VIH_min": 8.0,
-        "VOL_max": 0.5,
-        "VOH_min": 11.5,
-        "VCC": 12.0,
-        "VSS": 0.0,
-    },
 }
 
 
@@ -463,146 +405,9 @@ def get_logic_threshold(
         raise ValueError(f"Unknown threshold_type: {threshold_type}")
 
 
-def detect_logic_family(
-    trace: WaveformTrace,
-    *,
-    confidence_threshold: float = 0.8,
-) -> tuple[str, float]:
-    """Auto-detect logic family from signal voltage levels.
-
-    Analyzes the signal to determine which logic family it most likely represents
-    based on voltage levels.
-
-    Args:
-        trace: Input analog waveform trace.
-        confidence_threshold: Minimum confidence (0-1) to return a match.
-
-    Returns:
-        Tuple of (family_name, confidence_score).
-        Returns ("unknown", 0.0) if no match above threshold.
-
-    Example:
-        >>> family, conf = detect_logic_family(trace)
-        >>> print(f"Detected: {family} ({conf*100:.1f}% confidence)")
-    """
-    if len(trace.data) < 10:
-        return ("unknown", 0.0)
-
-    data = np.asarray(trace.data)
-
-    # Find voltage levels using percentiles
-    p10, p90 = np.percentile(data, [10, 90])
-    vlow = p10
-    vhigh = p90
-
-    # Calculate midpoint and swing
-    vmid = (vlow + vhigh) / 2.0
-    vswing = vhigh - vlow
-
-    if vswing < 0.1:  # Insufficient signal
-        return ("unknown", 0.0)
-
-    # Score each logic family
-    scores: dict[str, float] = {}
-
-    for family_name, levels in LOGIC_FAMILIES.items():
-        # Check if voltage levels match this family
-        vil_max = levels["VIL_max"]
-        vih_min = levels["VIH_min"]
-        vcc = levels.get("VCC", 5.0)
-
-        # Expected midpoint for this family
-        expected_mid = (vil_max + vih_min) / 2.0
-
-        # Score based on:
-        # 1. Midpoint proximity
-        # 2. High level proximity to VOH
-        # 3. Low level proximity to VOL
-
-        mid_error = abs(vmid - expected_mid)
-        high_error = abs(vhigh - levels.get("VOH_min", vih_min))
-        low_error = abs(vlow - levels.get("VOL_max", vil_max))
-
-        # Normalize errors (handle VCC=0 for ECL/PMOS)
-        if vcc != 0:
-            mid_score = max(0, 1.0 - mid_error / abs(vcc))
-            high_score = max(0, 1.0 - high_error / abs(vcc))
-            low_score = max(0, 1.0 - low_error / abs(vcc))
-        else:
-            # For VCC=0 families (ECL), use voltage range instead
-            voltage_range = abs(vih_min - vil_max)
-            if voltage_range > 0:
-                mid_score = max(0, 1.0 - mid_error / voltage_range)
-                high_score = max(0, 1.0 - high_error / voltage_range)
-                low_score = max(0, 1.0 - low_error / voltage_range)
-            else:
-                mid_score = high_score = low_score = 0.0
-
-        # Combined score (weighted average)
-        total_score = mid_score * 0.5 + high_score * 0.25 + low_score * 0.25
-        scores[family_name] = total_score
-
-    # Find best match
-    if not scores:
-        return ("unknown", 0.0)
-
-    best_family = max(scores.items(), key=lambda x: x[1])
-
-    if best_family[1] < confidence_threshold:
-        return ("unknown", best_family[1])
-
-    return best_family
-
-
-def detect_open_collector(
-    trace: WaveformTrace,
-    *,
-    asymmetry_threshold: float = 3.0,
-) -> tuple[bool, float]:
-    """Detect open-collector or open-drain output.
-
-    Open-collector outputs have slow rise times (limited by pull-up resistor)
-    and fast fall times (active transistor).
-
-    Args:
-        trace: Input analog waveform trace.
-        asymmetry_threshold: Minimum rise/fall ratio to indicate open-collector.
-
-    Returns:
-        Tuple of (is_open_collector, asymmetry_ratio).
-
-    Example:
-        >>> is_oc, ratio = detect_open_collector(trace)
-        >>> if is_oc:
-        ...     print(f"Open-collector detected (rise/fall = {ratio:.1f})")
-    """
-    from oscura.analyzers.waveform.measurements import fall_time, rise_time
-
-    if len(trace.data) < 10:
-        return (False, 1.0)
-
-    # Measure rise and fall times
-    tr = rise_time(trace, ref_levels=(0.1, 0.9))
-    tf = fall_time(trace, ref_levels=(0.9, 0.1))
-
-    # Check for valid measurements
-    if np.isnan(tr) or np.isnan(tf) or tf == 0:
-        return (False, 1.0)
-
-    # Calculate asymmetry ratio
-    asymmetry = tr / tf
-
-    # Open-collector has slow rise, fast fall
-    is_oc = bool(asymmetry >= asymmetry_threshold)
-
-    return (is_oc, float(asymmetry))
-
-
 __all__ = [
     "LOGIC_FAMILIES",
     "detect_edges",
-    "detect_logic_family",
-    "detect_open_collector",
     "get_logic_threshold",
     "to_digital",
 ]

oscura/analyzers/protocols/__init__.py

@@ -2,7 +2,7 @@
 
 Provides protocol decoders for common serial and automotive protocols including
 UART, SPI, I2C, CAN, LIN, FlexRay, JTAG, SWD, I2S, USB, HDLC, Manchester, CAN-FD,
-1-Wire, and parallel bus protocols (GPIB, Centronics, ISA).
+and 1-Wire.
 """
 
 from oscura.analyzers.protocols.base import (
@@ -60,18 +60,6 @@ from oscura.analyzers.protocols.onewire import (
     OneWireTimings,
     decode_onewire,
 )
-
-# Parallel bus protocols
-from oscura.analyzers.protocols.parallel_bus import (
-    CentronicsFrame,
-    GPIBFrame,
-    GPIBMessageType,
-    ISACycleType,
-    ISATransaction,
-    decode_centronics,
-    decode_gpib,
-    decode_isa_bus,
-)
 from oscura.analyzers.protocols.spi import SPIDecoder, decode_spi
 from oscura.analyzers.protocols.swd import SWDDecoder, SWDResponse, decode_swd
 from oscura.analyzers.protocols.uart import UARTDecoder, decode_uart
@@ -103,16 +91,12 @@ __all__ = [
     "CANFDFrameType",
     "CANFrame",
     "CANFrameType",
-    # Parallel bus protocols
-    "CentronicsFrame",
     "ChannelDef",
     "DecoderState",
     # FlexRay (PRO-016)
     "FlexRayDecoder",
     "FlexRayFrame",
     "FlexRaySegment",
-    "GPIBFrame",
-    "GPIBMessageType",
     # HDLC (PRO-013)
     "HDLCDecoder",
     # I2C (PRO-004)
@@ -120,8 +104,6 @@ __all__ = [
     # I2S (PRO-011)
     "I2SDecoder",
     "I2SMode",
-    "ISACycleType",
-    "ISATransaction",
     # JTAG (PRO-009)
     "JTAGDecoder",
     # LIN (PRO-008)
@@ -153,13 +135,10 @@ __all__ = [
     "USBSpeed",
     "decode_can",
     "decode_can_fd",
-    "decode_centronics",
     "decode_flexray",
-    "decode_gpib",
     "decode_hdlc",
     "decode_i2c",
     "decode_i2s",
-    "decode_isa_bus",
     "decode_jtag",
     "decode_lin",
     "decode_manchester",

oscura/automotive/__init__.py

@@ -42,7 +42,7 @@ Example:
     P0420: Catalyst System Efficiency Below Threshold (Bank 1)
 """
 
-__version__ = "0.5.0"  # pragma: no cover
+__version__ = "0.5.1"  # pragma: no cover
 
 __all__ = [
     "CANMessage",