opencos-eda 0.3.12__py3-none-any.whl → 0.3.14__py3-none-any.whl

opencos/tools/questa_common.py

@@ -53,8 +53,10 @@ class ToolQuesta(Tool):
                 if line.strip().startswith('Release Notes For'):
                     m = re.search(r'(\d+)\.(\d+)', line)
                     if m:
-                        self.questa_major = int(m.group(1))
-                        self.questa_minor = int(m.group(2))
+                        if self._TOOL.startswith('questa'):
+                            # don't set these for ModelsimASE:
+                            self.questa_major = int(m.group(1))
+                            self.questa_minor = int(m.group(2))
                         self._VERSION = str(self.questa_major) + '.' + str(self.questa_minor)
                         util.debug(f'version {self._VERSION} ({release_notes_txt_filepath})')
                         break
@@ -101,11 +103,14 @@ class ToolQuesta(Tool):
 
         return self._VERSION
 
-    def set_tool_defines(self):
-        # Will only be called from an object which also inherits from CommandDesign,
-        # i.e. has self.defines
-        self.defines['OC_TOOL_QUESTA'] = None
-        self.defines[f'OC_TOOL_QUESTA_{self.questa_major:d}_{self.questa_minor:d}'] = None
+    def set_tool_defines(self) -> None:
+        '''Override from class Tool, which handles picking up config['tools'][self._TOOL]
+
+        defines. We also set the OC_TOOL_QUESTA_[major]_[minor] if those exist
+        '''
+        super().set_tool_defines() # Tool, set from config.
+        if self.questa_major and self.questa_minor:
+            self.defines[f'OC_TOOL_QUESTA_{self.questa_major:d}_{self.questa_minor:d}'] = None
 
 
 
@@ -145,6 +150,7 @@ class CommonSimQuesta(CommandSim, ToolQuesta):
 
     def prepare_compile(self):
         self.set_tool_defines()
+        self.update_library_map()
         self.write_vlog_dot_f()
         self.write_vsim_dot_do(dot_do_to_write='all')
 
@@ -250,21 +256,24 @@ class CommonSimQuesta(CommandSim, ToolQuesta):
         for value in self.incdirs:
             vlog_dot_f_lines += [ f"+incdir+{value}" ]
 
-        for k,v in self.defines.items():
-            if v is None:
-                vlog_dot_f_lines += [ f'+define+{k}' ]
-            else:
-
-                # if the value v is a double-quoted string, such as v='"hi"', the
-                # entire +define+NAME="hi" needs to wrapped in double quotes with the
-                # value v double-quotes escaped: "+define+NAME=\"hi\""
-                if isinstance(v, str) and v.startswith('"') and v.endswith('"'):
-                    str_v = v.replace('"', '\\"')
-                    vlog_dot_f_lines += [ f'"+define+{k}={str_v}"' ]
+        if self.args['ext-defines-sv-fname']:
+            self.create_ext_defines_sv()
+        else:
+            for k,v in self.defines.items():
+                if v is None:
+                    vlog_dot_f_lines += [ f'+define+{k}' ]
                 else:
-                    # Generally we should only support int and str python types passed as
-                    # +define+{k}={v}, but also for SystemVerilog plusargs
-                    vlog_dot_f_lines += [ f'+define+{k}={sanitize_defines_for_sh(v)}' ]
+
+                    # if the value v is a double-quoted string, such as v='"hi"', the
+                    # entire +define+NAME="hi" needs to wrapped in double quotes with the
+                    # value v double-quotes escaped: "+define+NAME=\"hi\""
+                    if isinstance(v, str) and v.startswith('"') and v.endswith('"'):
+                        str_v = v.replace('"', '\\"')
+                        vlog_dot_f_lines += [ f'"+define+{k}={str_v}"' ]
+                    else:
+                        # Generally we should only support int and str python types passed as
+                        # +define+{k}={v}, but also for SystemVerilog plusargs
+                        vlog_dot_f_lines += [ f'+define+{k}={sanitize_defines_for_sh(v)}' ]
 
 
         vlog_dot_f_lines += self.args['compile-args']
@@ -297,10 +306,17 @@ class CommonSimQuesta(CommandSim, ToolQuesta):
         # work around this by setting tcl varaibles for each parameter.
         if self.parameters:
             if not self.use_vopt:
-                voptargs_str += ' ' + ' '.join(self.process_parameters_get_list(arg_prefix='-G'))
+                voptargs_str += ' ' + ' '.join(
+                    self.process_parameters_get_list(
+                        arg_prefix='-G', hier_delimiter='/', top_hier_str=f'/{self.args["top"]}/'
+                    )
+                )
             else:
                 for k,v in self.parameters.items():
-                    s = sim.parameters_dict_get_command_list(params={k: v}, arg_prefix='')[0]
+                    s = sim.parameters_dict_get_command_list(
+                        params={k: v}, arg_prefix='', hier_delimiter='/',
+                        top_hier_str=f'/{self.args["top"]}/'
+                    )[0]
                     # At this point, s should be a str in form {k}={v}
                     if not s or '=' not in s:
                         continue
@@ -310,9 +326,12 @@ class CommonSimQuesta(CommandSim, ToolQuesta):
                         # we'll do:
                         #   set PARAMETERS(MyParam) "hi bye"
                         #  vopt -GMyParam=$PARAMETERS(MyParam)
-                        s = s.replace(f'{k}=', f'set PARAMETERS({k}) ')
+                        parts = s.split('=')
+                        _name = parts[0]
+                        _value = '='.join(parts[1:])
+                        s = f'set PARAMETERS({_name}) {_value}'
                         vopt_do_lines.append(s)
-                        voptargs_str += f' -G{k}=$PARAMETERS({k}) '
+                        voptargs_str += f' -G{_name}=$PARAMETERS({_name}) '
                     else:
                         voptargs_str += f' -G{s} '
 
@@ -370,6 +389,10 @@ class CommonSimQuesta(CommandSim, ToolQuesta):
                 + f" -sv_seed {self.args['seed']} {sim_plusargs_str} {vsim_suppress_list_str}" \
                 + f" {voptargs_str} {vsim_ext_args} work.{self.args['top']}"
 
+        # If there are additional top level libs, we wont' add them to the vopt step, add
+        # to vsim only (after work.TOP):
+        for l in self.args['add-top-library']:
+            vsim_one_liner += f' {l}'
 
         vsim_one_liner = vsim_one_liner.replace('\n', ' ')
 
@@ -519,3 +542,9 @@ class CommonFListQuesta(CommandFList, ToolQuesta):
     def __init__(self, config: dict):
         CommandFList.__init__(self, config=config)
         ToolQuesta.__init__(self, config=self.config)
+        self.args.update({
+            # an Flist, like vlog.f, cannot support parameters or sim-plusargs, so warn
+            # if they are present b/c they will not be emitted.
+            'emit-parameter': False,
+            'emit-plusargs': False,
+        })

opencos/tools/questa_fe.py

@@ -41,20 +41,6 @@ class CommandSimQuestaFe(CommonSimQuesta):
         })
 
 
-    def set_tool_defines(self):
-        '''Override from questa.ToolQuesta'''
-        # Update any defines from config.tools.questa_fse:
-        self.defines.update(
-            self.tool_config.get(
-                'defines',
-                # defaults, if not set:
-                {
-                 'OC_TOOL_QUESTA_FE': 1
-                }
-            )
-        )
-
-
 class CommandElabQuestaFe(CommandSimQuestaFe):
     '''CommandElabQuesta is a command handler for: eda elab --tool=questa_fe'''
 

opencos/tools/questa_fse.py

@@ -38,20 +38,6 @@ class CommandSimQuestaFse(CommonSimQuesta):
         })
 
 
-    def set_tool_defines(self):
-        '''Override from questa.ToolQuesta'''
-        # Update any defines from config.tools.questa_fse:
-        self.defines.update(
-            self.tool_config.get(
-                'defines',
-                # defaults, if not set:
-                {
-                 'OC_TOOL_QUESTA_FSE': 1
-                }
-            )
-        )
-
-
 class CommandElabQuestaFse(CommandSimQuestaFse):
     '''CommandElabQuestaFse is a command handler for: eda elab --tool=questa_fse'''
 

opencos/tools/riviera.py

@@ -9,6 +9,8 @@ Contains classes for ToolRiviera, CommandSimRiviera, CommandElabRiviera.
 import os
 import subprocess
 
+from pathlib import Path
+
 from opencos import util
 from opencos.commands import CommandFList
 from opencos.files import safe_shutil_which
@@ -65,6 +67,8 @@ class ToolRiviera(ToolQuesta):
 class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
     '''CommandSimRiviera is a command handler for: eda sim --tool=riviera'''
 
+    library_map_supported = True
+
     def __init__(self, config: dict):
         CommonSimQuesta.__init__(self, config=config)
 
@@ -82,6 +86,7 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
             'waves-fst': True,
             'waves-vcd': False,
             'coverage-tcl': '',
+            'ext-defines-sv-fname': '_ext_defines.sv',
         })
         self.args_help.update({
             'waves-fst': (
@@ -99,6 +104,12 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
                 'Attempts to support UVM. Adds to vlog: -l uvm +incdir+PATH for the PATH to'
                 ' uvm_macros.svh for the installed version of Riviera used.'
             ),
+            'license-queue': (
+                'Set to enable env vars (if unset) LICENSE_QUEUE=1, ALDEC_LICENSE_QUEUE=1,'
+                ' FLEXLM_TIMEOUT=3000000 (3us), which should set Riviera to wait for licenses'
+                ' instead of immediately exiting with error. You may wish to also set your own'
+                ' env vars for ALDEC_LICENSE_FILE instead of LM_LICENSE_FILE.'
+            ),
         })
 
         if self.uvm_versions:
@@ -109,15 +120,6 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
             'uvm-version': { 'choices': list(self.uvm_versions) }
         })
 
-    def set_tool_defines(self):
-        # Update any defines from config.tools.modelsim_ase:
-        self.defines.update(
-            self.tool_config.get(
-                'defines',
-                # defaults, if not set:
-                {'OC_TOOL_RIVIERA': 1}
-            )
-        )
 
     # Note: many of these we follow the same flow as CommandSimModelsimAse:
     # do_it, prepare_compile, compile, elaborate, simulate
@@ -192,23 +194,33 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
                 '-dbg'
             ])
 
+        # Note, in Riviera we have to put sim libs in vsim call (with -L) and in vlog (with -l)
+        vlog_dot_f_lines.extend([f'-l {x}' for x in self.args['sim-library']])
+
         for value in self.incdirs:
             vlog_dot_f_lines += [ f"+incdir+{value}" ]
 
-        for k,v in self.defines.items():
-            if v is None:
-                vlog_dot_f_lines += [ f'+define+{k}' ]
-            else:
-                # if the value v is a double-quoted string, such as v='"hi"', the
-                # entire +define+NAME="hi" needs to wrapped in double quotes with the
-                # value v double-quotes escaped: "+define+NAME=\"hi\""
-                if isinstance(v, str) and v.startswith('"') and v.endswith('"'):
-                    str_v = v.replace('"', '\\"')
-                    vlog_dot_f_lines += [ f'"+define+{k}={str_v}"' ]
+        # For external defines, we will create a file in the work-dir named
+        # _ext_defines.sv, it will be the first file in the file list, and it
+        # will be valid Verilog/SV, not a list of +define+Name[=Value]
+        if self.args['ext-defines-sv-fname']:
+            self.create_ext_defines_sv()
+        else:
+            for k,v in self.defines.items():
+                if v is None:
+                    vlog_dot_f_lines += [ f'+define+{k}' ]
                 else:
-                    # Generally we should only support int and str python types passed as
-                    # +define+{k}={v}, but also for SystemVerilog plusargs
-                    vlog_dot_f_lines += [ f'+define+{k}={sanitize_defines_for_sh(v)}' ]
+                    # if the value v is a double-quoted string, such as v='"hi"', the
+                    # entire +define+NAME="hi" needs to wrapped in double quotes with the
+                    # value v double-quotes escaped: "+define+NAME=\"hi\""
+                    if isinstance(v, str) and v.startswith('"') and v.endswith('"'):
+                        str_v = v.replace('"', '\\"')
+                        vlog_dot_f_lines += [ f'"+define+{k}={str_v}"' ]
+                    else:
+                        # Generally we should only support int and str python types passed as
+                        # +define+{k}={v}, but also for SystemVerilog plusargs
+                        vlog_dot_f_lines += [ f'+define+{k}={sanitize_defines_for_sh(v)}' ]
+
 
 
         vlog_dot_f_lines += self.args['compile-args']
@@ -261,11 +273,22 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
             if all(x not in voptargs_str for x in ('+access +r', '+access +w+r')):
                 voptargs_str += ' +access +r'
 
-        # parameters
+        # parameters, for Riviera we need to use the leading forward slash option
+        # aka -G/Name=Value, if our parameter name doesn't already have path information.
+        # If you do -GName=Value, all parameters in the hierachy with Name will be set,
+        # so to only do top level parameters, if hierarchy isn't mentioned in the Name,
+        # would need to do -G/{self.args['top']}/Name=Value.
         if self.parameters:
-            voptargs_str += ' ' + ' '.join(self.process_parameters_get_list(arg_prefix='-G'))
+            voptargs_str += ' ' + ' '.join(
+                self.process_parameters_get_list(
+                    arg_prefix='-G', hier_delimiter='/', top_hier_str=f'/{self.args["top"]}/'
+                )
+            )
 
-        vsim_libs = ' '.join([f'-l {x}' for x in self.args['sim-library']])
+        # Note, in Riviera we have to put sim libs in vsim call (with -L) and in vlog (with -l)
+        # we previously updated self.args['sim-library'] with self.update_library_map()
+        vmap_lines_str = self.get_vmap_lines_str()
+        vsim_libs = ' '.join([f'-L {x}' for x in self.args['sim-library']])
 
         vsim_one_liner = (
             "vsim"
@@ -273,11 +296,16 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
             f" {voptargs_str} {vsim_ext_args} {vsim_libs} work.{self.args['top']}"
         )
 
+
+        for l in self.args['add-top-library']:
+            vsim_one_liner += f' {l}'
+
         vsim_one_liner = vsim_one_liner.replace('\n', ' ') # needs to be a one-liner
 
         vsim_vlogonly_dot_do_lines = [
             "if {[file exists work]} { vdel -all work; }",
             "vlib work;",
+            vmap_lines_str,
             "if {[catch {vlog -f vlog.f} result]} {",
             "    echo \"Caught $result \";",
             "    if {[batch_mode]} {",
@@ -293,6 +321,7 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
             "if {[file exists work]} { vdel -all work; }",
             "vlib work;",
             "set qc 30;",
+            vmap_lines_str,
             "if {[catch {vlog -f vlog.f} result]} {",
             "    echo \"Caught $result \";",
             "    if {[batch_mode]} {",
@@ -314,6 +343,7 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
             "if {[file exists work]} { vdel -all work; }",
             "vlib work;",
             "set qc 30;",
+            vmap_lines_str,
             "if {[catch {vlog -f vlog.f} result]} {",
             "    echo \"Caught $result \";",
             "    if {[batch_mode]} {",
@@ -365,6 +395,23 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
                 f.writelines(line + "\n" for line in vsim_vlogonly_dot_do_lines)
 
 
+    def handle_arg_license_queue(self) -> None:
+        '''Handles self.args['license-queue'] (bool) to set env vars
+
+        Overriden from opencos.command.sim::CommandSim.
+        '''
+        if not self.args['license-queue']:
+            return
+
+        if 'LICENSE_QUEUE' not in os.environ:
+            os.environ['LICENSE_QUEUE'] = '1'
+        if 'ALDEC_LICENSE_QUEUE' not in os.environ:
+            os.environ['ALDEC_LICENSE_QUEUE'] = '1'
+
+        # Anecdotal evidence, set this which may help
+        if 'FLEXLM_TIMEOUT' not in os.environ:
+            os.environ['FLEXLM_TIMEOUT'] = '3000000' # 3e6 us = 3 sec
+
 
     def _get_vsim_suppress_list_str(self) -> str:
         vsim_suppress_list = []
@@ -377,6 +424,38 @@ class CommandSimRiviera(CommonSimQuesta, ToolRiviera):
 
         return ' '.join(vsim_suppress_list)
 
+    def update_library_map(self, base_search_paths: list | None = None) -> None:
+        '''Override from sim::CommandSim
+
+        We add some common places to look relative to the Riviera install paths
+        '''
+        bsp = []
+        if isinstance(base_search_paths, list):
+            bsp += base_search_paths
+        bsp += [
+            Path(self.sim_exe_base_path),
+            Path(self.sim_exe_base_path) / '..',
+            Path(self.sim_exe_base_path) / '..' / 'vlib',
+        ]
+        super().update_library_map(base_search_paths=bsp)
+
+    def get_vmap_lines_str(self) -> str:
+        '''Returns an empty str, or single str in the form:
+
+        vmap -global LibraryName  AbsolutePathToDotLibFile
+        vmap -global LibraryName2 AbsolutePathToAnotherDotLibFile
+        ...
+        uses self.args['library-map'], updates self.args['sim-library']
+        '''
+        if not self.library_map:
+            return ''
+
+        lines = []
+        for lib_name, lib_file_path in self.library_map.items():
+            lines.append(f'vmap -global {lib_name} {lib_file_path}')
+
+        return '\n'.join(lines)
+
 
 class CommandElabRiviera(CommandSimRiviera):
     '''CommandElabRiviera is a command handler for: eda elab --tool=riviera'''

opencos/tools/slang.py

@@ -63,7 +63,7 @@ class ToolSlang(Tool):
         return self._VERSION
 
     def set_tool_defines(self):
-        self.defines['OC_TOOL_SLANG'] = None # add define
+        super().set_tool_defines()
         if 'SYNTHESIS' not in self.defines:
             self.defines['SIMULATION'] = None # add define
         # Expected to manually add SYNTHESIS command line or target, otherwise.
@@ -139,14 +139,17 @@ class CommandElabSlang(CommandElab, ToolSlang):
             command_list += [ '--include-directory', value ]
 
         # defines:
-        for k,v in self.defines.items():
-            command_list.append( '--define-macro' )
-            if v is None:
-                command_list.append( k )
-            else:
-                # Generally we should only support int and str python types passed as
-                # --define-macro {k}={v}
-                command_list.append( f'{k}={sanitize_defines_for_sh(v)}' )
+        if self.args['ext-defines-sv-fname']:
+            self.create_ext_defines_sv()
+        else:
+            for k,v in self.defines.items():
+                command_list.append( '--define-macro' )
+                if v is None:
+                    command_list.append( k )
+                else:
+                    # Generally we should only support int and str python types passed as
+                    # --define-macro {k}={v}
+                    command_list.append( f'{k}={sanitize_defines_for_sh(v)}' )
 
         # parameters
         command_list.extend(

opencos/tools/slang_yosys.py

@@ -22,12 +22,6 @@ class ToolSlangYosys(ToolYosys):
         'https://github.com/MikePopoloski/slang',
     ]
 
-    def set_tool_defines(self):
-        super().set_tool_defines()
-        self.defines.update({
-            'OC_TOOL_SLANG': None,
-        })
-
 
 class CommandSynthSlangYosys(CommonSynthYosys, ToolSlangYosys):
     '''CommandSynthSlangYosys is a command handler for: eda synth --tool=slang_yosys'''

opencos/tools/surelog.py

@@ -48,7 +48,7 @@ class ToolSurelog(Tool):
         return self._VERSION
 
     def set_tool_defines(self):
-        self.defines['OC_TOOL_SURELOG'] = None # add define
+        super().set_tool_defines()
         if 'SYNTHESIS' not in self.defines:
             self.defines['SIMULATION'] = None # add define
         # Expected to manually add SYNTHESIS command line or target, otherwise.
@@ -116,13 +116,16 @@ class CommandElabSurelog(CommandElab, ToolSurelog):
         )
 
         # defines:
-        for k,v in self.defines.items():
-            if v is None:
-                command_list.append( f'+define+{k}' )
-            else:
-                # Generally we should only support int and str python types passed as
-                # +define+{k}={v}
-                command_list.append( f'+define+{k}={sanitize_defines_for_sh(v)}' )
+        if self.args['ext-defines-sv-fname']:
+            self.create_ext_defines_sv()
+        else:
+            for k,v in self.defines.items():
+                if v is None:
+                    command_list.append( f'+define+{k}' )
+                else:
+                    # Generally we should only support int and str python types passed as
+                    # +define+{k}={v}
+                    command_list.append( f'+define+{k}={sanitize_defines_for_sh(v)}' )
 
         # Because many elab target-name won't match the --top needed for
         # slang, we'll leave this to arg --surelog-top:

opencos/tools/tabbycad_yosys.py

@@ -21,17 +21,11 @@ class ToolTabbyCadYosys(ToolYosys):
     _TOOL = 'tabbycad_yosys'
     _URL = 'https://www.yosyshq.com/tabby-cad-datasheet'
 
-    def set_tool_defines(self):
-        super().set_tool_defines()
-        self.defines.update({
-            'OC_TOOL_TABBYCAD': None,
-        })
-
 
 class CommandSynthTabbyCadYosys(CommonSynthYosys, ToolTabbyCadYosys):
     '''Command handler for: eda synth --tool tabbycad_yosys.'''
 
-    def __init__(self, config:dict):
+    def __init__(self, config: dict):
         CommonSynthYosys.__init__(self, config)
         ToolTabbyCadYosys.__init__(self, config=self.config)
 

opencos/tools/verilator.py

@@ -67,9 +67,6 @@ class ToolVerilator(Tool):
         self._VERSION = version
         return self._VERSION
 
-    def set_tool_defines(self):
-        # We don't need to define VERILATOR, the verilated exe does that itself.
-        pass
 
 class VerilatorSim(CommandSim, ToolVerilator):
     '''VerilatorSim is a command handler for: eda sim --tool=verilator'''
@@ -150,6 +147,7 @@ class VerilatorSim(CommandSim, ToolVerilator):
     # We do not override CommandSim.do_it()
     def prepare_compile(self):
         self.set_tool_defines()
+        self.update_library_map()
 
         # If there are C++ files here, then we will run Verilator in --cc mode:
         if self.files_cpp:
@@ -222,7 +220,9 @@ class VerilatorSim(CommandSim, ToolVerilator):
                 check_logs=False
             )
 
-    def get_compile_command_lists(self, **kwargs) -> list:
+    def get_compile_command_lists( # pylint: disable=too-many-branches
+            self, **kwargs
+    ) -> list:
 
         # Support for lint_only (bool) in kwargs:
         lint_only = kwargs.get('lint_only', False)
@@ -250,6 +250,10 @@ class VerilatorSim(CommandSim, ToolVerilator):
             '-top', self.args['top'],
         ]
 
+        if self.args['add-top-library']:
+            util.warning('--add-top-library: currently not supported in eda --tool=verilator:',
+                         f'{self.args["add-top-library"]}')
+
         if not lint_only:
             verilate_command_list += [
                 '-o', 'sim.exe',
@@ -268,13 +272,16 @@ class VerilatorSim(CommandSim, ToolVerilator):
             verilate_command_list += [ f"+incdir+{value}" ]
 
         # defines
-        for k,v in self.defines.items():
-            if v is None:
-                verilate_command_list += [ f'+define+{k}' ]
-            else:
-                # Generally we should only support int and str python types passed as
-                # +define+{k}={v}, but also for SystemVerilog plusargs
-                verilate_command_list += [ f'+define+{k}={sanitize_defines_for_sh(v)}' ]
+        if self.args['ext-defines-sv-fname']:
+            self.create_ext_defines_sv()
+        else:
+            for k,v in self.defines.items():
+                if v is None:
+                    verilate_command_list += [ f'+define+{k}' ]
+                else:
+                    # Generally we should only support int and str python types passed as
+                    # +define+{k}={v}, but also for SystemVerilog plusargs
+                    verilate_command_list += [ f'+define+{k}={sanitize_defines_for_sh(v)}' ]
 
         # parameters
         verilate_command_list.extend(