opencos-eda 0.2.57__py3-none-any.whl → 0.3.1__py3-none-any.whl

opencos/tests/test_deps_helpers.py

@@ -59,26 +59,26 @@ def test_get_all_targets_eda_multi():
 
 def test_parse_deps_shell_str__no_parse():
     line = 'some_file.sv'
-    d = deps_commands.parse_deps_shell_str(line, '', '')
+    d = deps_commands.parse_deps_shell_str(line, '', '', attributes={})
     assert not d, f'{d=}'
 
     line = 'some_target:'
-    d = deps_commands.parse_deps_shell_str(line, '', '')
+    d = deps_commands.parse_deps_shell_str(line, '', '', attributes={})
     assert not d, f'{d=}'
 
     line = '   csr@some_file.sv'
-    d = deps_commands.parse_deps_shell_str(line, '', '')
+    d = deps_commands.parse_deps_shell_str(line, '', '', attributes={})
     assert not d, f'{d=}'
 
 def test_parse_deps_shell_str__cp():
     line = '    shell@ cp ./oclib_fifo_test.sv oclib_fifo_test_COPY.sv ;'
-    d = deps_commands.parse_deps_shell_str(line, '', '')
+    d = deps_commands.parse_deps_shell_str(line, '', '', attributes={})
     assert d, f'{d=}'
     assert d['exec_list'] == ['cp', './oclib_fifo_test.sv', 'oclib_fifo_test_COPY.sv', ';'], f'{d=}'
 
 def test_parse_deps_shell_str__echo():
     line = '    shell@echo "hello world"'
-    d = deps_commands.parse_deps_shell_str(line, '', '')
+    d = deps_commands.parse_deps_shell_str(line, '', '', attributes={})
     assert d, f'{d=}'
     assert d['exec_list'] == ['echo', '"hello', 'world"'], f'{d=}'
 
@@ -88,7 +88,9 @@ def test_parse_deps_shell_str__enable_filepath_replacement():
     module_dir = os.path.dirname(os.path.abspath(__file__))
     os.chdir(module_dir)
     line = 'shell@cp ../deps/deps_commands.py .pytest.copied.py'
-    d = deps_commands.parse_deps_shell_str(line, target_path='./', target_node='foo_target')
+    d = deps_commands.parse_deps_shell_str(
+        line, target_path='./', target_node='foo_target', attributes={}
+    )
     assert d, f'{d=}'
     spath = os.path.abspath(os.path.join('..', 'deps', 'deps_commands.py'))
     assert d['exec_list'] == ['cp', spath, '.pytest.copied.py'], f'{d=}'
@@ -100,8 +102,10 @@ def test_parse_deps_shell_str__disable_filepath_replacement():
     module_dir = os.path.dirname(os.path.abspath(__file__))
     os.chdir(module_dir)
     line = 'shell@cp ../deps/deps_commands.py .pytest.copied.py'
-    d = deps_commands.parse_deps_shell_str(line, target_path='./', target_node='foo_target',
-                                          enable_filepath_subst_target_dir=False)
+    d = deps_commands.parse_deps_shell_str(
+        line, target_path='./', target_node='foo_target',
+        attributes={'filepath-subst-target-dir': False}
+    )
     assert d, f'{d=}'
     assert d['exec_list'] == ['cp', '../deps/deps_commands.py', '.pytest.copied.py'], f'{d=}'
     assert d['target_node'] == 'foo_target'
@@ -112,8 +116,10 @@ def test_parse_deps_shell_str__enable_dirpath_replacement():
     module_dir = os.path.dirname(os.path.abspath(__file__))
     os.chdir(module_dir)
     line = 'shell@ls -ltr ./'
-    d = deps_commands.parse_deps_shell_str(line, target_path='./', target_node='foo_target',
-                                          enable_dirpath_subst_target_dir=True)
+    d = deps_commands.parse_deps_shell_str(
+        line, target_path='./', target_node='foo_target',
+        attributes={'dirpath-subst-target-dir': True}
+    )
     assert d, f'{d=}'
     assert d['exec_list'] == ['ls', '-ltr', os.path.abspath('./')], f'{d=}'
     assert d['target_node'] == 'foo_target'
@@ -125,7 +131,10 @@ def test_parse_deps_shell_str__disable_dirpath_replacement():
     module_dir = os.path.dirname(os.path.abspath(__file__))
     os.chdir(module_dir)
     line = 'shell@ls -ltr ./'
-    d = deps_commands.parse_deps_shell_str(line, target_path='./', target_node='foo_target')
+    d = deps_commands.parse_deps_shell_str(
+        line, target_path='./', target_node='foo_target',
+        attributes={}
+    )
     assert d, f'{d=}'
     assert d['exec_list'] == ['ls', '-ltr', './'], f'{d=}'
     assert d['target_node'] == 'foo_target'
@@ -134,26 +143,26 @@ def test_parse_deps_shell_str__disable_dirpath_replacement():
 
 def test_parse_deps_work_dir_add_srcs__no_parse():
     line = 'some_file.sv'
-    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '')
+    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '', {})
     assert not d, f'{d=}'
 
     line = 'some_target:'
-    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '')
+    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '', {})
     assert not d, f'{d=}'
 
     line = '   csr@some_file.sv'
-    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '')
+    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '', {})
     assert not d, f'{d=}'
 
 def test_parse_deps_work_dir_add_srcs__single_file():
     line = '    work_dir_add_srcs@ single_file.txt'
-    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '')
+    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '', {})
     assert d, f'{d=}'
     assert d['file_list'] == ['single_file.txt']
 
 def test_parse_deps_work_dir_add_srcs__several_file():
     line = '    work_dir_add_srcs@ single_file.txt another.sv  gen-verilog/mine.v ./gen-vhdl/wordy.vhdl'
-    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '')
+    d = deps_commands.parse_deps_work_dir_add_srcs(line, '', '', {})
     assert d, f'{d=}'
     assert d['file_list'] == [
         'single_file.txt', 'another.sv', 'gen-verilog/mine.v', './gen-vhdl/wordy.vhdl'
@@ -162,34 +171,37 @@ def test_parse_deps_work_dir_add_srcs__several_file():
 
 def test_parse_deps_peakrdl__no_parse():
     line = 'some_file.sv'
-    d = deps_commands.parse_deps_peakrdl(line, '', '')
+    d = deps_commands.parse_deps_peakrdl(line, '', '', {})
     assert not d, f'{d=}'
 
     line = 'some_target:'
-    d = deps_commands.parse_deps_peakrdl(line, '', '')
+    d = deps_commands.parse_deps_peakrdl(line, '', '', {})
     assert not d, f'{d=}'
 
     line = '   csr@some_file.sv'
-    d = deps_commands.parse_deps_peakrdl(line, '', '')
+    d = deps_commands.parse_deps_peakrdl(line, '', '', {})
     assert not d, f'{d=}'
 
 def test_parse_deps_peakrdl__with_top():
     line = '    peakrdl@ --cpuif axi4-lite-flat --top   my_fancy_csrs ./my_csrs.rdl'
-    d = deps_commands.parse_deps_peakrdl(line, '', '')
+    d = deps_commands.parse_deps_peakrdl(line, '', '', {})
     assert d, f'{d=}'
     assert len(d['shell_commands_list']) > 0
-    assert d['work_dir_add_srcs']['file_list'] == ['peakrdl/my_fancy_csrs_pkg.sv', 'peakrdl/my_fancy_csrs.sv']
+    assert d['work_dir_add_srcs']['file_list'] == ['peakrdl/my_fancy_csrs_pkg.sv',
+                                                   'peakrdl/my_fancy_csrs.sv']
 
 def test_parse_deps_peakrdl__with_top2():
     line = '    peakrdl@ --cpuif axi4-lite-flat --top=my_fancy_csrs ./my_csrs.rdl'
-    d = deps_commands.parse_deps_peakrdl(line, '', '')
+    d = deps_commands.parse_deps_peakrdl(line, '', '', {})
     assert d, f'{d=}'
     assert len(d['shell_commands_list']) > 0
-    assert d['work_dir_add_srcs']['file_list'] == ['peakrdl/my_fancy_csrs_pkg.sv', 'peakrdl/my_fancy_csrs.sv']
+    assert d['work_dir_add_srcs']['file_list'] == ['peakrdl/my_fancy_csrs_pkg.sv',
+                                                   'peakrdl/my_fancy_csrs.sv']
 
 def test_parse_deps_peakrdl__infer_top():
     line = '    peakrdl@ --cpuif axi4-lite-flat ./my_csrs.rdl'
-    d = deps_commands.parse_deps_peakrdl(line, '', '')
+    d = deps_commands.parse_deps_peakrdl(line, '', '', {})
     assert d, f'{d=}'
     assert len(d['shell_commands_list']) > 0
-    assert d['work_dir_add_srcs']['file_list'] == ['peakrdl/my_csrs_pkg.sv', 'peakrdl/my_csrs.sv']
+    assert d['work_dir_add_srcs']['file_list'] == ['peakrdl/my_csrs_pkg.sv',
+                                                   'peakrdl/my_csrs.sv']

opencos/tests/test_eda.py

@@ -20,7 +20,6 @@ and should be more gracefully handled.
 import os
 import shutil
 import subprocess
-from contextlib import redirect_stdout, redirect_stderr
 
 import pytest
 
@@ -107,6 +106,7 @@ class TestsRequiresVerilator( # pylint: disable=too-many-public-methods
         assert rc == 0
 
 
+
     def test_args_sim_tool_with_path(self):
         '''Test for calling a tool as --tool=<tool>=</path/to/tool-exe>'''
         verilator_fullpath = shutil.which('verilator')
@@ -659,6 +659,31 @@ class TestsRequiresIVerilog(Helpers):
         assert rc == 0
 
 
+@pytest.mark.skipif(not can_run_eda_sim(), reason='no tool found to handle command: sim')
+class TestArgs(Helpers):
+    '''Test some args features, needs a sim tool'''
+    DEFAULT_DIR = os.path.join(THISPATH, '..', '..', 'lib', 'tests')
+
+    def test_duplicate_args(self):
+        '''Use oclib_fifo_test to make sure we don't lose (do NOT uniquify) duplicate
+        list-style args'''
+        self.chdir()
+        rc = self.log_it(
+            'sim --stop-before-compile oclib_fifo_test --compile-args=-hi --compile-args=-hi',
+            use_eda_wrap=False
+            )
+        assert rc == 0
+        # Confirm we have two args in self.args['compile-args'] for: -hi
+        eda_config_yml_path = os.path.join(
+            os.getcwd(), 'eda.work', 'oclib_fifo_test.sim', 'eda_output_config.yml'
+        )
+        data = yaml_safe_load(eda_config_yml_path)
+        assert 'args' in data
+        assert 'compile-args' in data['args']
+        assert len(data['args']['compile-args']) == 2
+        assert data['args']['compile-args'] == ['-hi', '-hi']
+
+
 @pytest.mark.skipif(not can_run_eda_sim(), reason='no tool found to handle command: sim')
 class TestDepsReqs:
     '''Tests for 'reqs' in the DEPS files. 'reqs' are requirements, like a .pcap or file
@@ -708,65 +733,6 @@ class TestDepsReqs:
         assert rc > 1
 
 
-@pytest.mark.parametrize("command", ['sim', 'shell'])
-def test_deps_command_order(command):
-    '''Test for various "commands" within a DEPS target. This test checks that command
-    order is preserved in the top-to-bottom deps order, meaning that eda.py has to collect
-    all commands deps order, and then execute them in that order.'''
-
-    chdir_remove_work_dir('deps_files/command_order')
-    if command == 'sim' and not can_run_eda_sim():
-        pytest.skip(f'sim skipped, {can_run_eda_sim()=}')
-        return # skip/pass
-
-    if command == 'shell':
-        cmd_list = 'shell target_test'.split()
-    else:
-        cmd_list = 'sim --stop-before-compile target_test'.split()
-
-    with open('eda.log', 'w', encoding='utf-8') as f:
-        with redirect_stdout(f):
-            with redirect_stderr(f):
-                rc = eda.main(*cmd_list)
-
-    print(f'{rc=}')
-    assert rc == 0
-
-    # We should see "hi" before "bye" to confirm deps + command order is correct.
-    # see ./deps_files/command_order/DEPS.yml - target = target_test
-    found_str_list = [
-        'exec: echo "hi"',
-        'exec: echo "bye"',
-    ]
-    found_lines_list = [None, None]
-
-    with open('eda.log', encoding='utf-8') as f:
-        for lineno, line in enumerate(f.readlines()):
-            line = line.rstrip()
-            for idx,key in enumerate(found_str_list):
-                if key in line:
-                    found_lines_list[idx] = lineno
-
-    assert found_lines_list[0] # found hi
-    assert found_lines_list[1] # found bye
-    assert found_lines_list[0] < found_lines_list[1] # hi before bye
-
-    # Added check, we redirected to create eda.log earlier to confirm the targets worked,
-    # but as a general eda.py check, all shell commands should create their own
-    # {target}__shell_0.log file:
-    work_dir = os.path.join(
-        THISPATH, 'deps_files', 'command_order', 'eda.work', f'target_test.{command}'
-    )
-    # Note that eda will write out the returncode INFO line to tee'd log files, so
-    # there is more in the log file than "hi" or "bye".
-    with open(os.path.join(work_dir, 'target_echo_hi__shell_0.log'), encoding='utf-8') as f:
-        text = ' '.join(f.readlines()).strip()
-        assert any(text.startswith(x) for x in ['hi', '"hi"', '\\"hi\\"'])
-    # Added check, one of the targets uses a custom 'tee' file name, instead of the default log.
-    with open(os.path.join(work_dir, 'custom_tee_echo_bye.log'), encoding='utf-8') as f:
-        text = ''.join(f.readlines()).strip()
-        assert any(text.startswith(x) for x in ['bye', '"bye"', '\\"bye\\"'])
-
 
 @pytest.mark.skipif('verilator' not in tools_loaded, reason="requires verilator")
 class TestDepsOtherMarkup:

opencos/tools/modelsim_ase.py

@@ -32,6 +32,14 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
         self.args.update({
             'tool': self._TOOL, # override
             'gui': False,
+            'vopt': self.use_vopt,
+        })
+        self.args_help.update({
+            'vopt': (
+                'Boolean to enable/disable use of vopt step prior to vsim step'
+                ' Note that vopt args can be controlled with --elab-args=<value1>'
+                ' --elab-args=<value2> ...'
+            )
         })
 
     def set_tool_defines(self):
@@ -158,7 +166,7 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
                 'compile-waivers',
                 [ #defaults:
                     '2275', # 2275 - Existing package 'foo_pkg' will be overwritten.
-                ]):
+                ]) + self.args['compile-waivers']:
             vlog_dot_f_lines += ['-suppress', str(waiver)]
 
         if self.args['gui'] or self.args['waves']:
@@ -252,15 +260,18 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
 
         sim_plusargs_str = self._get_sim_plusargs_str()
         vsim_suppress_list_str = self._get_vsim_suppress_list_str()
+        vsim_ext_args = ' '.join(self.args.get('sim-args', []))
 
-        voptargs_str = ""
+        voptargs_str = self.tool_config.get('elab-args', '')
+        voptargs_str += ' '.join(self.args.get('elab-args', []))
         if self.args['gui'] or self.args['waves']:
-            voptargs_str = self.tool_config.get('simulate-waves-args', '+acc')
+            voptargs_str += ' ' + self.tool_config.get('simulate-waves-args', '+acc')
             util.artifacts.add_extension(
                 search_paths=self.args['work-dir'], file_extension='wlf',
                 typ='waveform', description='Modelsim/Questa Waveform WLF (Wave Log Format) file'
             )
 
+        # TODO(drew): support self.args['sim_libary'] (1 lists)
         vlog_do_lines = []
         vsim_do_lines = []
 
@@ -269,9 +280,6 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
         voptargs_str += more_voptargs_str
 
 
-        # TODO(drew): support self.args['sim_libary', 'elab-args', sim-args'] (3 lists)
-        # to add to vsim_one_liner.
-
         vopt_one_liner = ""
         if self.use_vopt:
             vopt_one_liner = (
@@ -283,12 +291,12 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
 
             vsim_one_liner = "vsim -onfinish stop" \
                 + f" -sv_seed {self.args['seed']} {sim_plusargs_str} {vsim_suppress_list_str}" \
-                + f" opt__{self.args['top']}"
+                + f" {vsim_ext_args} opt__{self.args['top']}"
         else:
             # vopt doesn't exist, use single vsim call after vlog call:
             vsim_one_liner = "vsim -onfinish stop" \
                 + f" -sv_seed {self.args['seed']} {sim_plusargs_str} {vsim_suppress_list_str}" \
-                + f" {voptargs_str} work.{self.args['top']}"
+                + f" {voptargs_str} {vsim_ext_args} work.{self.args['top']}"
 
 
         vsim_one_liner = vsim_one_liner.replace('\n', ' ')
@@ -393,7 +401,7 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
                     #defaults:
                     '3009', # 3009: [TSCALE] - Module 'foo' does not have a timeunit/timeprecision
                             #       specification in effect, but other modules do.
-                ]):
+                ]) + self.args['sim-waivers']:
             vsim_suppress_list += ['-suppress', str(waiver)]
 
         return ' '.join(vsim_suppress_list)

opencos/tools/riviera.py

@@ -59,6 +59,17 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
         self.args.update({
             'tool': self._TOOL, # override
             'gui': False,
+            'waves-fst': True,
+            'waves-vcd': False,
+        })
+        self.args_help.update({
+            'waves-fst': (
+                '(Default True) If using --waves, apply simulation runtime arg +trace.'
+                ' Note that if you do not have SV code using $dumpfile, eda will add'
+                ' _waves_pkg.sv to handle this for you with +trace runtime plusarg.'
+            ),
+            'waves-vcd': 'If using --waves, apply simulation runtime arg +trace=vcd',
+            'waves': 'Save a .asdb offline wavefile, can be used with --waves-fst or --waves-vcd',
         })
 
     def set_tool_defines(self):
@@ -76,6 +87,9 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
 
     def compile(self):
         '''Override for CommandSimModelsimAse.compile() so we can set our own must_strings'''
+
+        self.add_waves_pkg_file()
+
         if self.args['stop-before-compile']:
             # don't run anything, save everyting we've already run in _prep_compile()
             return
@@ -126,7 +140,8 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
             '-sv -input_ports net').split()
 
         # Add waivers from config.tool.riviera, convert to warning:
-        for waiver in self.tool_config.get('compile-waivers', []):
+        for waiver in self.tool_config.get('compile-waivers', []) + \
+                self.args['compile-waivers']:
             vlog_dot_f_lines += [f'-err {waiver} W1']
 
         vlog_dot_f_fname = filename
@@ -167,6 +182,7 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
             f.writelines(line + "\n" for line in vlog_dot_f_lines)
 
 
+
     def write_vsim_dot_do(self, dot_do_to_write: list) -> None:
         '''Writes files(s) based on dot_do_to_write(list of str)
 
@@ -177,9 +193,18 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
         vsim_vlogonly_dot_do_fpath = os.path.join(self.args['work-dir'], 'vsim_vlogonly.do')
 
         sim_plusargs_str = self._get_sim_plusargs_str()
-
-        voptargs_str = ""
-        if self.args['gui'] or self.args['waves'] or self.args['coverage']:
+        vsim_ext_args = ' '.join(self.args.get('sim-args', []))
+
+        if self.args['waves'] and '+trace' not in sim_plusargs_str:
+            if self.args.get('waves-vcd', False):
+                sim_plusargs_str += ' +trace=vcd'
+            elif self.args.get('waves-fst', False):
+                sim_plusargs_str += ' +trace'
+
+        voptargs_str = self.tool_config.get('elab-args', '')
+        voptargs_str += ' '.join(self.args.get('elab-args', []))
+        if self.args['gui'] or self.args['waves'] or self.args['coverage']: # \
+           #or self.args['waves-asdb']:
             voptargs_str += self.tool_config.get('simulate-waves-args',
                                                  '+accb +accr +access +r+w')
         if self.args['coverage']:
@@ -195,7 +220,7 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
         vsim_one_liner = (
             "vsim"
             f" -sv_seed {self.args['seed']} {sim_plusargs_str}"
-            f" {voptargs_str} work.{self.args['top']}"
+            f" {voptargs_str} {vsim_ext_args} work.{self.args['top']}"
         )
 
         vsim_one_liner = vsim_one_liner.replace('\n', ' ') # needs to be a one-liner
@@ -294,7 +319,7 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
         for waiver in self.tool_config.get(
                 'simulate-waivers', [
                     #defaults: none
-                ]):
+                ]) + self.args['sim-waivers']:
             vsim_suppress_list += ['-filter', str(waiver)]
 
         return ' '.join(vsim_suppress_list)

opencos/tools/verilator.py

@@ -76,6 +76,8 @@ class VerilatorSim(CommandSim, ToolVerilator):
             'gui': False,
             'tcl-file': None,
             'dump-vcd': False,
+            'waves-fst': True,
+            'waves-vcd': False,
             'lint-only': False,
             'cc-mode': False,
             'verilator-coverage-args': [],
@@ -84,12 +86,22 @@ class VerilatorSim(CommandSim, ToolVerilator):
         })
 
         self.args_help.update({
-            'waves':    ('Include waveforms, if possible for Verilator by applying'
-                         ' simulation runtime arg +trace. User will need SV code to interpret the'
-                         'plusarg and apply $dumpfile("dump.fst").'),
-            'dump-vcd': ('If using --waves, apply simulation runtime arg +trace=vcd. User'
-                         ' will need SV code to interpret the plusarg and apply'
-                         ' $dumpfile("dump.vcd").'),
+            'waves': (
+                'Include waveforms, if possible for Verilator by applying'
+                ' simulation runtime arg +trace. User will need SV code to interpret the'
+                ' plusarg and apply $dumpfile("dump.fst").'
+            ),
+            'waves-fst': (
+                '(Default True) If using --waves, apply simulation runtime arg +trace.'
+                ' Note that if you do not have SV code using $dumpfile, eda will add'
+                ' _waves_pkg.sv to handle this for you with +trace runtime plusarg.'
+            ),
+            'waves-vcd': (
+                'If using --waves, apply simulation runtime arg +trace=vcd. User'
+                ' will need SV code to interpret the plusarg and apply'
+                ' $dumpfile("dump.vcd").'
+            ),
+            'dump-vcd': 'Same as --waves-vcd',
             'lint-only': 'Run verilator with --lint-only, instead of --binary',
             'gui':       'Not supported for Verilator',
             'cc-mode':   'Run verilator with --cc, requires a sim_main.cpp or similar sources',
@@ -124,7 +136,7 @@ class VerilatorSim(CommandSim, ToolVerilator):
         if self.files_cpp:
             self.args['cc-mode'] = True
 
-        self._add_verilator_waves_files()
+        self.add_waves_pkg_file()
 
         # Each of these should be a list of util.ShellCommandList()
         self.verilate_command_lists = self.get_compile_command_lists()
@@ -300,9 +312,10 @@ class VerilatorSim(CommandSim, ToolVerilator):
                 # Built-in support for eda args --waves and/or --dump-vcd to become runtime
                 # plusargs +trace or +trace=vcd, if +trace or +trace= was not already in our
                 # plusargs.
-                if self.args.get('dump-vcd', False):
+                if self.args.get('dump-vcd', False) or \
+                   self.args.get('waves-vcd', False):
                     sim_plusargs.append('+trace=vcd')
-                else:
+                elif self.args.get('waves-fst', False):
                     sim_plusargs.append('+trace')
 
         verilated_exec_command_list += config_sim_args + sim_plusargs + self.args['sim-args']
@@ -351,40 +364,17 @@ class VerilatorSim(CommandSim, ToolVerilator):
 
         return []
 
-    def _add_verilator_waves_files(self) -> None:
+    def add_waves_pkg_file(self) -> None:
         '''If --waves present, and the user is missing any $dumpfile(), then adds a pre-written
         SystemVerilog package to their source code.
         '''
-        if not self.args['waves']:
-            return
         if self.args['cc-mode']:
-            # We won't do this if the user bround a .cpp file and verilator not
+            # We won't do this if the user brought a .cpp file and verilator not
             # called with --binary.
             return
-        found_dumpfile = False
-        for fname in self.files_v + self.files_sv:
-            if found_dumpfile:
-                break
-            with open(fname, encoding='utf-8') as f:
-                for line in f.readlines():
-                    if '$dumpfile' in line:
-                        found_dumpfile = True
-                        break
-        if not found_dumpfile:
-            thispath = os.path.dirname(__file__)
-            file_to_add = os.path.join(thispath, '..', '_waves_pkg.sv')
-            util.info(f'--waves arg present, no $dumpfile found, adding SV file: {file_to_add}')
-            self.add_file(file_to_add)
-
-        # register .vcd or .fst artifacts:
-        util.artifacts.add_extension(
-            search_paths=self.args['work-dir'], file_extension='fst',
-            typ='waveform', description='Simulation Waveform FST (Fast Signal Trace) file'
-        )
-        util.artifacts.add_extension(
-            search_paths=self.args['work-dir'], file_extension='vcd',
-            typ='waveform', description='Simulation Waveform VCD (Value Change Dump) file'
-        )
+
+        super().add_waves_pkg_file() # call from CommandSim
+
 
 
     def _get_start_verilator_command_list(self, lint_only: bool = False) -> list:
@@ -415,7 +405,7 @@ class VerilatorSim(CommandSim, ToolVerilator):
                 [ #defaults:
                     'CASEINCOMPLETE',
                     'TIMESCALEMOD', # If one file has `timescale, then they all must
-                ]):
+                ]) + self.args['compile-waivers']:
             ret.append(f'-Wno-{waiver}')
         return ret