opencos-eda 0.2.56__py3-none-any.whl → 0.3.0__py3-none-any.whl

opencos/tools/cocotb.py

@@ -100,9 +100,34 @@ class CommandSimCocotb(CommandSim, ToolCocotb):
     def set_tool_defines(self):
         ToolCocotb.set_tool_defines(self)
 
+    def help( # pylint: disable=dangerous-default-value
+            self, tokens: list = [], no_targets: bool = False
+    ) -> None:
+        '''Override for Command.help(...)'''
+
+        super().help(tokens=tokens, no_targets=no_targets)
+        self._warn_if_simulator_not_present()
+
+    def _warn_if_simulator_not_present(self) -> None:
+        '''Warn if --cocotb-simulator is not set, or if the exe is not in PATH'''
+
+        simulator = self.args['cocotb-simulator']
+        if not simulator:
+            util.warning('--cocotb-simulator is not set, a simulation cannot be run with'
+                         'this arg value')
+            return
+        exe = shutil.which(simulator)
+        if not exe:
+            util.warning(f'--cocotb-simulator={simulator}, {simulator} is not present in PATH',
+                         'a simulation cannot be run with this arg value')
+
+
     def prepare_compile(self):
         self.set_tool_defines()
 
+        # Check existence of cocotb-simulator:
+        self._warn_if_simulator_not_present()
+
         # Fix iverilog -> icarus
         if self.args['cocotb-simulator'] == 'iverilog':
             self.args['cocotb-simulator'] = 'icarus'

opencos/tools/modelsim_ase.py

@@ -10,7 +10,7 @@ Note that this is for 32-bit Modelsim Student Edition. Consider using --tool=que
 import os
 
 from opencos import util
-from opencos.commands import CommandSim
+from opencos.commands import sim, CommandSim
 from opencos.tools.questa import ToolQuesta
 from opencos.utils.str_helpers import sanitize_defines_for_sh
 
@@ -32,6 +32,14 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
         self.args.update({
             'tool': self._TOOL, # override
             'gui': False,
+            'vopt': self.use_vopt,
+        })
+        self.args_help.update({
+            'vopt': (
+                'Boolean to enable/disable use of vopt step prior to vsim step'
+                ' Note that vopt args can be controlled with --elab-args=<value1>'
+                ' --elab-args=<value2> ...'
+            )
         })
 
     def set_tool_defines(self):
@@ -158,7 +166,7 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
                 'compile-waivers',
                 [ #defaults:
                     '2275', # 2275 - Existing package 'foo_pkg' will be overwritten.
-                ]):
+                ]) + self.args['compile-waivers']:
             vlog_dot_f_lines += ['-suppress', str(waiver)]
 
         if self.args['gui'] or self.args['waves']:
@@ -201,6 +209,44 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
         with open(vlog_dot_f_fpath, 'w', encoding='utf-8') as f:
             f.writelines(line + "\n" for line in vlog_dot_f_lines)
 
+    def vopt_handle_parameters(self) -> (str, list):
+        '''Returns str for vopt or voptargs, and list of vopt tcl
+
+        Note this is used for self.use_vopt = True or False.
+        '''
+
+        voptargs_str = ''
+        vopt_do_lines = []
+
+        # Note that if self.use_vopt=True, we have to do some workarounds for how
+        # some questa-like tools behave for: tcl/.do + vopt arg processing
+        # This affects string based parameters that have spaces (vopt treats spaces unique args,
+        # vsim does not). Since we'd like to keep the vopt/vsim split into separate steps, we can
+        # work around this by setting tcl varaibles for each parameter.
+        if self.parameters:
+            if not self.use_vopt:
+                voptargs_str += ' ' + ' '.join(self.process_parameters_get_list(arg_prefix='-G'))
+            else:
+                for k,v in self.parameters.items():
+                    s = sim.parameters_dict_get_command_list(params={k: v}, arg_prefix='')[0]
+                    # At this point, s should be a str in form {k}={v}
+                    if not s or '=' not in s:
+                        continue
+                    if ' ' in s:
+                        # Instead of:
+                        #   vopt -GMyParam="hi bye"
+                        # we'll do:
+                        #   set PARAMETERS(MyParam) "hi bye"
+                        #  vopt -GMyParam=$PARAMETERS(MyParam)
+                        s = s.replace(f'{k}=', f'set PARAMETERS({k}) ')
+                        vopt_do_lines.append(s)
+                        voptargs_str += f' -G{k}=$PARAMETERS({k}) '
+                    else:
+                        voptargs_str += f' -G{s} '
+
+        return voptargs_str, vopt_do_lines
+
+
     def write_vsim_dot_do( # pylint: disable=too-many-locals
             self, dot_do_to_write: list
     ) -> None:
@@ -214,21 +260,25 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
 
         sim_plusargs_str = self._get_sim_plusargs_str()
         vsim_suppress_list_str = self._get_vsim_suppress_list_str()
+        vsim_ext_args = ' '.join(self.args.get('sim-args', []))
 
-        voptargs_str = ""
+        voptargs_str = self.tool_config.get('elab-args', '')
+        voptargs_str += ' '.join(self.args.get('elab-args', []))
         if self.args['gui'] or self.args['waves']:
-            voptargs_str = self.tool_config.get('simulate-waves-args', '+acc')
+            voptargs_str += ' ' + self.tool_config.get('simulate-waves-args', '+acc')
             util.artifacts.add_extension(
                 search_paths=self.args['work-dir'], file_extension='wlf',
                 typ='waveform', description='Modelsim/Questa Waveform WLF (Wave Log Format) file'
             )
 
-        # parameters
-        if self.parameters:
-            voptargs_str += ' ' + ' '.join(self.process_parameters_get_list(arg_prefix='-G'))
+        # TODO(drew): support self.args['sim_libary'] (1 lists)
+        vlog_do_lines = []
+        vsim_do_lines = []
+
+        # parameters, use helper method to get voptargs_str and vopt_do_lines
+        more_voptargs_str, vopt_do_lines = self.vopt_handle_parameters()
+        voptargs_str += more_voptargs_str
 
-        # TODO(drew): support self.args['sim_libary', 'elab-args', sim-args'] (3 lists)
-        # to add to vsim_one_liner.
 
         vopt_one_liner = ""
         if self.use_vopt:
@@ -241,17 +291,17 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
 
             vsim_one_liner = "vsim -onfinish stop" \
                 + f" -sv_seed {self.args['seed']} {sim_plusargs_str} {vsim_suppress_list_str}" \
-                + f" opt__{self.args['top']}"
+                + f" {vsim_ext_args} opt__{self.args['top']}"
         else:
             # vopt doesn't exist, use single vsim call after vlog call:
             vsim_one_liner = "vsim -onfinish stop" \
                 + f" -sv_seed {self.args['seed']} {sim_plusargs_str} {vsim_suppress_list_str}" \
-                + f" {voptargs_str} work.{self.args['top']}"
+                + f" {voptargs_str} {vsim_ext_args} work.{self.args['top']}"
 
 
         vsim_one_liner = vsim_one_liner.replace('\n', ' ')
 
-        vlog_do_lines = [
+        vlog_do_lines += [
             "if {[file exists work]} { vdel -all work; }",
             "vlib work;",
             "quietly set qc 30;",
@@ -263,9 +313,8 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
             "}",
         ]
 
-        vopt_do_lines = []
         if self.use_vopt:
-            vopt_do_lines = [
+            vopt_do_lines += [
                 "if {[catch { " + vopt_one_liner + " } result] } {",
                 "    echo \"Caught $result\";",
                 "    if {[batch_mode]} {",
@@ -274,7 +323,7 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
                 "}",
             ]
 
-        vsim_do_lines = [
+        vsim_do_lines += [
             "if {[catch { " + vsim_one_liner + " } result] } {",
             "    echo \"Caught $result\";",
             "    if {[batch_mode]} {",
@@ -352,7 +401,7 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
                     #defaults:
                     '3009', # 3009: [TSCALE] - Module 'foo' does not have a timeunit/timeprecision
                             #       specification in effect, but other modules do.
-                ]):
+                ]) + self.args['sim-waivers']:
             vsim_suppress_list += ['-suppress', str(waiver)]
 
         return ' '.join(vsim_suppress_list)

opencos/tools/riviera.py

@@ -59,6 +59,17 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
         self.args.update({
             'tool': self._TOOL, # override
             'gui': False,
+            'waves-fst': True,
+            'waves-vcd': False,
+        })
+        self.args_help.update({
+            'waves-fst': (
+                '(Default True) If using --waves, apply simulation runtime arg +trace.'
+                ' Note that if you do not have SV code using $dumpfile, eda will add'
+                ' _waves_pkg.sv to handle this for you with +trace runtime plusarg.'
+            ),
+            'waves-vcd': 'If using --waves, apply simulation runtime arg +trace=vcd',
+            'waves': 'Save a .asdb offline wavefile, can be used with --waves-fst or --waves-vcd',
         })
 
     def set_tool_defines(self):
@@ -76,6 +87,9 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
 
     def compile(self):
         '''Override for CommandSimModelsimAse.compile() so we can set our own must_strings'''
+
+        self.add_waves_pkg_file()
+
         if self.args['stop-before-compile']:
             # don't run anything, save everyting we've already run in _prep_compile()
             return
@@ -126,7 +140,8 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
             '-sv -input_ports net').split()
 
         # Add waivers from config.tool.riviera, convert to warning:
-        for waiver in self.tool_config.get('compile-waivers', []):
+        for waiver in self.tool_config.get('compile-waivers', []) + \
+                self.args['compile-waivers']:
             vlog_dot_f_lines += [f'-err {waiver} W1']
 
         vlog_dot_f_fname = filename
@@ -167,6 +182,7 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
             f.writelines(line + "\n" for line in vlog_dot_f_lines)
 
 
+
     def write_vsim_dot_do(self, dot_do_to_write: list) -> None:
         '''Writes files(s) based on dot_do_to_write(list of str)
 
@@ -177,9 +193,18 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
         vsim_vlogonly_dot_do_fpath = os.path.join(self.args['work-dir'], 'vsim_vlogonly.do')
 
         sim_plusargs_str = self._get_sim_plusargs_str()
-
-        voptargs_str = ""
-        if self.args['gui'] or self.args['waves'] or self.args['coverage']:
+        vsim_ext_args = ' '.join(self.args.get('sim-args', []))
+
+        if self.args['waves'] and '+trace' not in sim_plusargs_str:
+            if self.args.get('waves-vcd', False):
+                sim_plusargs_str += ' +trace=vcd'
+            elif self.args.get('waves-fst', False):
+                sim_plusargs_str += ' +trace'
+
+        voptargs_str = self.tool_config.get('elab-args', '')
+        voptargs_str += ' '.join(self.args.get('elab-args', []))
+        if self.args['gui'] or self.args['waves'] or self.args['coverage']: # \
+           #or self.args['waves-asdb']:
             voptargs_str += self.tool_config.get('simulate-waves-args',
                                                  '+accb +accr +access +r+w')
         if self.args['coverage']:
@@ -195,7 +220,7 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
         vsim_one_liner = (
             "vsim"
             f" -sv_seed {self.args['seed']} {sim_plusargs_str}"
-            f" {voptargs_str} work.{self.args['top']}"
+            f" {voptargs_str} {vsim_ext_args} work.{self.args['top']}"
         )
 
         vsim_one_liner = vsim_one_liner.replace('\n', ' ') # needs to be a one-liner
@@ -294,7 +319,7 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
         for waiver in self.tool_config.get(
                 'simulate-waivers', [
                     #defaults: none
-                ]):
+                ]) + self.args['sim-waivers']:
             vsim_suppress_list += ['-filter', str(waiver)]
 
         return ' '.join(vsim_suppress_list)

opencos/tools/slang_yosys.py

@@ -118,7 +118,10 @@ class CommandSynthSlangYosys(CommonSynthYosys, ToolSlangYosys):
             params=self.parameters, arg_prefix='-G '
         )
 
-        read_slang_cmd.append(f'--top {self.args["top"]}')
+        # In case --top was not set:
+        if not any(x.startswith('--top') for x in read_slang_cmd):
+            read_slang_cmd.append(f'--top {self.args["top"]}')
+
         return ' '.join(read_slang_cmd)
 
 

opencos/tools/verilator.py

@@ -76,6 +76,8 @@ class VerilatorSim(CommandSim, ToolVerilator):
             'gui': False,
             'tcl-file': None,
             'dump-vcd': False,
+            'waves-fst': True,
+            'waves-vcd': False,
             'lint-only': False,
             'cc-mode': False,
             'verilator-coverage-args': [],
@@ -84,12 +86,22 @@ class VerilatorSim(CommandSim, ToolVerilator):
         })
 
         self.args_help.update({
-            'waves':    ('Include waveforms, if possible for Verilator by applying'
-                         ' simulation runtime arg +trace. User will need SV code to interpret the'
-                         'plusarg and apply $dumpfile("dump.fst").'),
-            'dump-vcd': ('If using --waves, apply simulation runtime arg +trace=vcd. User'
-                         ' will need SV code to interpret the plusarg and apply'
-                         ' $dumpfile("dump.vcd").'),
+            'waves': (
+                'Include waveforms, if possible for Verilator by applying'
+                ' simulation runtime arg +trace. User will need SV code to interpret the'
+                ' plusarg and apply $dumpfile("dump.fst").'
+            ),
+            'waves-fst': (
+                '(Default True) If using --waves, apply simulation runtime arg +trace.'
+                ' Note that if you do not have SV code using $dumpfile, eda will add'
+                ' _waves_pkg.sv to handle this for you with +trace runtime plusarg.'
+            ),
+            'waves-vcd': (
+                'If using --waves, apply simulation runtime arg +trace=vcd. User'
+                ' will need SV code to interpret the plusarg and apply'
+                ' $dumpfile("dump.vcd").'
+            ),
+            'dump-vcd': 'Same as --waves-vcd',
             'lint-only': 'Run verilator with --lint-only, instead of --binary',
             'gui':       'Not supported for Verilator',
             'cc-mode':   'Run verilator with --cc, requires a sim_main.cpp or similar sources',
@@ -124,7 +136,7 @@ class VerilatorSim(CommandSim, ToolVerilator):
         if self.files_cpp:
             self.args['cc-mode'] = True
 
-        self._add_verilator_waves_files()
+        self.add_waves_pkg_file()
 
         # Each of these should be a list of util.ShellCommandList()
         self.verilate_command_lists = self.get_compile_command_lists()
@@ -300,9 +312,10 @@ class VerilatorSim(CommandSim, ToolVerilator):
                 # Built-in support for eda args --waves and/or --dump-vcd to become runtime
                 # plusargs +trace or +trace=vcd, if +trace or +trace= was not already in our
                 # plusargs.
-                if self.args.get('dump-vcd', False):
+                if self.args.get('dump-vcd', False) or \
+                   self.args.get('waves-vcd', False):
                     sim_plusargs.append('+trace=vcd')
-                else:
+                elif self.args.get('waves-fst', False):
                     sim_plusargs.append('+trace')
 
         verilated_exec_command_list += config_sim_args + sim_plusargs + self.args['sim-args']
@@ -351,40 +364,17 @@ class VerilatorSim(CommandSim, ToolVerilator):
 
         return []
 
-    def _add_verilator_waves_files(self) -> None:
+    def add_waves_pkg_file(self) -> None:
         '''If --waves present, and the user is missing any $dumpfile(), then adds a pre-written
         SystemVerilog package to their source code.
         '''
-        if not self.args['waves']:
-            return
         if self.args['cc-mode']:
-            # We won't do this if the user bround a .cpp file and verilator not
+            # We won't do this if the user brought a .cpp file and verilator not
             # called with --binary.
             return
-        found_dumpfile = False
-        for fname in self.files_v + self.files_sv:
-            if found_dumpfile:
-                break
-            with open(fname, encoding='utf-8') as f:
-                for line in f.readlines():
-                    if '$dumpfile' in line:
-                        found_dumpfile = True
-                        break
-        if not found_dumpfile:
-            thispath = os.path.dirname(__file__)
-            file_to_add = os.path.join(thispath, '..', '_waves_pkg.sv')
-            util.info(f'--waves arg present, no $dumpfile found, adding SV file: {file_to_add}')
-            self.add_file(file_to_add)
-
-        # register .vcd or .fst artifacts:
-        util.artifacts.add_extension(
-            search_paths=self.args['work-dir'], file_extension='fst',
-            typ='waveform', description='Simulation Waveform FST (Fast Signal Trace) file'
-        )
-        util.artifacts.add_extension(
-            search_paths=self.args['work-dir'], file_extension='vcd',
-            typ='waveform', description='Simulation Waveform VCD (Value Change Dump) file'
-        )
+
+        super().add_waves_pkg_file() # call from CommandSim
+
 
 
     def _get_start_verilator_command_list(self, lint_only: bool = False) -> list:
@@ -415,7 +405,7 @@ class VerilatorSim(CommandSim, ToolVerilator):
                 [ #defaults:
                     'CASEINCOMPLETE',
                     'TIMESCALEMOD', # If one file has `timescale, then they all must
-                ]):
+                ]) + self.args['compile-waivers']:
             ret.append(f'-Wno-{waiver}')
         return ret
 

opencos/tools/yosys.py

@@ -536,7 +536,6 @@ class CommandLecYosys(CommandLec, ToolYosys):
 
         self.synth_designs_tops = [None, None]
         self.synth_designs_fpaths = [None, None]
-        self.synth_design_top_module_names = [None, None]
 
     def get_synth_result_fpath(self, target: str) -> str:
         '''Overridden from CommandLec'''
@@ -547,7 +546,7 @@ class CommandLecYosys(CommandLec, ToolYosys):
     def get_synth_command_list(self, design_num: int) -> list:
         '''Returns one of the synthesis command lists, for design_num=0 or 1'''
 
-        if not design_num in [0, 1]:
+        if not design_num in (0, 1):
             self.error(f'{design_num=} we only support LEC on designs 0 and 1')
 
         synth_cmd_list = [
@@ -561,31 +560,43 @@ class CommandLecYosys(CommandLec, ToolYosys):
         synth_cmd_list += [
             '--work-dir=' + self.synth_work_dirs[design_num],
             self.args['designs'][design_num],
-            f'--rename-module=Design{design_num + 1}'
+            f'--rename-module=Design{design_num + 1}',
         ]
 
-        self.synth_design_top_module_names[design_num] = f'Design{design_num + 1}'
+        if self.args['flatten-all']:
+            # We have to do this or may get conflicts on black-boxed modules, but can
+            # be avoided with --no-flatten-all.
+            synth_cmd_list.append(
+                '--flatten-all'
+            )
+
+        self.synth_designs_tops[design_num] = f'Design{design_num + 1}'
 
         return synth_cmd_list
 
 
-    def get_synth_top_from_output_config(self, design_num: int) -> str:
-        '''Returns the top name given the design number that we synthesized'''
+    def get_synth_top_from_output_config(self, design_num: int) -> (str, str):
+        '''Returns the (orignal top name, module name) tuple given the design number
+
+        that we synthesized'''
 
         work_dir = self.synth_work_dirs[design_num]
         output_cfg_fpath = os.path.join(work_dir, eda_config.EDA_OUTPUT_CONFIG_FNAME)
         data = yaml_safe_load(output_cfg_fpath)
         top = data.get('args', {}).get('top', '')
-        if not top:
+        rename_module = data.get('args', {}).get('rename-module', '')
+        if not top and not rename_module:
             self.error(f'"top" not found in synth run from {work_dir=} in',
                        f'config {output_cfg_fpath}')
-        return top
+        if not rename_module:
+            return top, top
+        return top, rename_module
 
 
     def get_synth_results_fpath(self, design_num: int, top: str) -> str:
-        '''Returns the synthesized .v file fpath'''
+        '''Returns the synthesized .v file fpath, using orignal top (not renamed)'''
         if not top:
-            top = self.get_synth_top_from_output_config(design_num=design_num)
+            top, _ = self.get_synth_top_from_output_config(design_num=design_num)
 
         work_dir = self.synth_work_dirs[design_num]
         fpath = os.path.join(work_dir, 'yosys', f'{top}.v')
@@ -594,7 +605,7 @@ class CommandLecYosys(CommandLec, ToolYosys):
         return fpath
 
 
-    def do_it(self) -> None:
+    def do_it(self) -> None: # pylint: disable=too-many-locals,too-many-statements,too-many-branches
         self.set_tool_defines()
         self.write_eda_config_and_args()
 
@@ -622,6 +633,9 @@ class CommandLecYosys(CommandLec, ToolYosys):
                     self.exec(work_dir=self.args['work-dir'], command_list=x,
                               tee_fpath=x.tee_fpath)
 
+            util.info(f'LEC ran via --yosys-scriptfile: {self.args["yosys-scriptfile"]}')
+            return
+
 
         if self.args['synth']:
             synth1_cmd_list = self.get_synth_command_list(design_num=0)
@@ -636,23 +650,23 @@ class CommandLecYosys(CommandLec, ToolYosys):
             self.exec(pwd, synth2_cmd_list, background=True)
             util.info(f'Finished with 2nd LEC synthesis {self.args["designs"][1]}')
 
-            self.synth_designs_tops = [
-                self.get_synth_top_from_output_config(design_num=0),
-                self.get_synth_top_from_output_config(design_num=1)
-            ]
+
+            top0, module0 = self.get_synth_top_from_output_config(design_num=0)
+            top1, module1 = self.get_synth_top_from_output_config(design_num=1)
+            self.synth_designs_tops = [module0, module1]
             util.info(f'Design tops: {self.synth_designs_tops}')
 
             # read the output config
             self.synth_designs_fpaths = [
                 os.path.abspath(
-                    self.get_synth_results_fpath(design_num=0, top=self.synth_designs_tops[0])),
+                    self.get_synth_results_fpath(design_num=0, top=top0)),
                 os.path.abspath(
-                    self.get_synth_results_fpath(design_num=1, top=self.synth_designs_tops[1]))
+                    self.get_synth_results_fpath(design_num=1, top=top1))
             ]
             util.info(f'Design tops: {self.synth_designs_fpaths}')
 
         else:
-            # don't run synthesis, need the two top level .v files in
+            # don't run synthesis, need the two top level .v|.sv files in
             # self.synth_designs_fpaths, and need the two top module names in
             # self.synth_designs_tops
             self.synth_designs_fpaths = [
@@ -660,11 +674,19 @@ class CommandLecYosys(CommandLec, ToolYosys):
                 os.path.abspath(self.args['designs'][1])
             ]
 
+            for i in (0, 1):
+                if not os.path.isfile(self.args['designs'][i]):
+                    self.error(
+                        'Using synth=False (--no-synth) --designs=<value> must be a single',
+                        f'filename, however {self.args["designs"][i]} does not exist'
+                    )
+
             path, fname = os.path.split(self.synth_designs_fpaths[0])
             module_guess, _ = os.path.splitext(fname)
             top1 = util.get_inferred_top_module_name(
                 module_guess=module_guess, module_fpath=self.synth_designs_fpaths[0]
             )
+            util.debug(f'design1 {module_guess=} {fname=} {path=}')
             util.info(f'design1 top module name = {top1} (from {path} / {fname})')
 
             path, fname = os.path.split(self.synth_designs_fpaths[1])
@@ -672,6 +694,7 @@ class CommandLecYosys(CommandLec, ToolYosys):
             top2 = util.get_inferred_top_module_name(
                 module_guess=module_guess, module_fpath=self.synth_designs_fpaths[1]
             )
+            util.debug(f'design2 {module_guess=} {fname=} {path=}')
             util.info(f'design2 top module name = {top2} (from {path} / {fname})')
 
             self.synth_designs_tops = [top1, top2]
@@ -691,13 +714,20 @@ class CommandLecYosys(CommandLec, ToolYosys):
                     ]
                 else:
                     self.error(f' --pre-read-verilog file {x} does not exist')
+
+        nooverwrite = ''
+        if self.args['synth'] and not self.args['flatten-all']:
+            # If we don't flatten-all from synthesis, and we had to run synthesis,
+            # then read the 2nd file with -overwrite
+            nooverwrite = '-nooverwrite'
+
         lec_cmd_f_list += [
             '# Design1 (module):',
             f'read_verilog -sv -icells {self.synth_designs_fpaths[0]}',
             '# Design2 (module):',
-            f'read_verilog -sv -icells {self.synth_designs_fpaths[1]}',
+            f'read_verilog -sv -icells {self.synth_designs_fpaths[1]} {nooverwrite}',
             'clk2fflogic;',
-            f'miter -equiv -flatten {" ".join(self.synth_design_top_module_names)} miter',
+            f'miter -equiv -flatten {" ".join(self.synth_designs_tops)} miter',
             ('sat -seq 50 -verify -prove trigger 0 -show-all -show-inputs -show-outputs'
              ' -set-init-zero miter'),
         ]