opencos-eda 0.2.55__py3-none-any.whl → 0.2.57__py3-none-any.whl

opencos/tests/helpers.py

@@ -39,6 +39,15 @@ def can_run_eda_command(*commands, config: dict) -> bool:
         if handler and getattr(handler, 'CHECK_REQUIRES', []):
             if not all(issubclass(handler, x) for x in getattr(handler, 'CHECK_REQUIRES', [])):
                 return False
+
+        # We cannot run tools that have disable-auto set:
+        tool = getattr(handler, '_TOOL', '')
+        if handler and tool:
+            entry = config['auto_tools_order'][0].get(tool, {})
+            if entry and entry.get('disable-auto', False):
+                # This tool cannot automatically run our command.
+                return False
+
         runnable.append(True)
     return runnable and all(runnable)
 

opencos/tests/test_eda_synth.py

@@ -8,6 +8,7 @@ import pytest
 from opencos import eda, eda_tool_helper
 from opencos.tests import helpers
 from opencos.tests.helpers import Helpers
+from opencos.utils.markup_helpers import yaml_safe_load
 
 
 THISPATH = os.path.dirname(__file__)
@@ -108,6 +109,17 @@ class TestsSlangYosys(Helpers):
         rc = self.log_it(cmd_str, use_eda_wrap=False)
         assert rc == 0
 
+        # Since vanilla yosys won't use the SDC file, let's at least confirm
+        # that EDA used it and tracked it:
+        eda_config_yml_path = os.path.join(
+            os.getcwd(), 'eda.work', 'oclib_fifo_with_sdc.synth', 'eda_output_config.yml'
+        )
+        data = yaml_safe_load(eda_config_yml_path)
+        assert 'files_sdc' in data
+        assert data['files_sdc']
+        assert data['files_sdc'][0].endswith('oclib_fifo_yosys.sdc')
+
+
 @pytest.mark.skipif('vivado' not in tools_loaded, reason="requires vivado")
 @pytest.mark.skipif(not vivado_has_xpms(), reason="requires install to have XPMs")
 class TestsVivado(Helpers):

opencos/tools/cocotb.py

@@ -100,9 +100,34 @@ class CommandSimCocotb(CommandSim, ToolCocotb):
     def set_tool_defines(self):
         ToolCocotb.set_tool_defines(self)
 
+    def help( # pylint: disable=dangerous-default-value
+            self, tokens: list = [], no_targets: bool = False
+    ) -> None:
+        '''Override for Command.help(...)'''
+
+        super().help(tokens=tokens, no_targets=no_targets)
+        self._warn_if_simulator_not_present()
+
+    def _warn_if_simulator_not_present(self) -> None:
+        '''Warn if --cocotb-simulator is not set, or if the exe is not in PATH'''
+
+        simulator = self.args['cocotb-simulator']
+        if not simulator:
+            util.warning('--cocotb-simulator is not set, a simulation cannot be run with'
+                         'this arg value')
+            return
+        exe = shutil.which(simulator)
+        if not exe:
+            util.warning(f'--cocotb-simulator={simulator}, {simulator} is not present in PATH',
+                         'a simulation cannot be run with this arg value')
+
+
     def prepare_compile(self):
         self.set_tool_defines()
 
+        # Check existence of cocotb-simulator:
+        self._warn_if_simulator_not_present()
+
         # Fix iverilog -> icarus
         if self.args['cocotb-simulator'] == 'iverilog':
             self.args['cocotb-simulator'] = 'icarus'

opencos/tools/invio_helpers.py

@@ -61,6 +61,12 @@ def write_py_file(
         'from invio import init, define_macro, add_include_directory, \\',
         '    add_verilog_file, add_sv_file, elaborate, elaborate_pct, analyze, \\',
         '    print_instance_hierarchy, write_design, report_analyzed_files',
+    ]
+    if command_design_obj.parameters:
+        lines += [
+            'from invio import get_parameters, report_parameters, replace_expression_of_parameter'
+        ]
+    lines += [
         'import os, shutil',
         '',
         'for p in ["invio"]:',
@@ -138,18 +144,34 @@ def write_py_file(
                                             tee_fpath = 'invio.log')]
     })
 
+    lines += [
+        'assert analyze()',
+    ]
+
+    if command_design_obj.parameters:
+        lines += [
+            '',
+            f'new_parameters = {command_design_obj.parameters}',
+            'for x in get_parameters():',
+            '    name_parts = x.full_name.split("::")',
+            '    mod, pname = name_parts[-2], name_parts[-1]',
+            f'    if pname in new_parameters and mod == "{top}":',
+            '        new_value = str(new_parameters[pname]) # invio needs str type for all',
+            '        print(f"PARAMETER UPDATE: {mod}.{pname} ---> {new_value}")',
+            '        replace_expression_of_parameter(x, new_value)',
+            'report_parameters()',
+            '',
+        ]
+
     if sim_lint:
         # lint (skip elaborate steps -- from eda.CommandLintInvio)
         lines += [
-            'assert analyze()',
-            '',
             'report_analyzed_files()',
             'print_instance_hierarchy()',
         ]
     elif sim_elab:
         # elab (non-synthesis), runs the following (from eda.CommandElabInvio)
         lines += [
-            'assert analyze()',
             f"assert elaborate('{top}', pct_elaboration=True, forceBlackbox={blackbox_list})",
             'assert elaborate_pct()',
             '',
@@ -159,7 +181,6 @@ def write_py_file(
     else:
         # synthesis-style elab (from eda.CommandElabInvioYosys)
         lines += [
-            'assert analyze()',
             f"assert elaborate('{top}', rtl_elaboration=True, forceBlackbox={blackbox_list})",
             '',
             'report_analyzed_files()',

opencos/tools/iverilog.py

@@ -136,6 +136,11 @@ class CommandSimIverilog(CommandSim, ToolIverilog):
                 # +define+{k}={v}, but also for SystemVerilog plusargs
                 command_list += [ '-D', f'{k}={sanitize_defines_for_sh(v)}' ]
 
+        # parameters
+        command_list.extend(
+            self.process_parameters_get_list(arg_prefix=f'-P{self.args["top"]}.')
+        )
+
         if not self.files_sv and not self.files_v:
             if not self.args['stop-before-compile']:
                 self.error(f'{self.target=} {self.files_sv=} and {self.files_v=} are empty,',

opencos/tools/modelsim_ase.py

@@ -10,7 +10,7 @@ Note that this is for 32-bit Modelsim Student Edition. Consider using --tool=que
 import os
 
 from opencos import util
-from opencos.commands import CommandSim
+from opencos.commands import sim, CommandSim
 from opencos.tools.questa import ToolQuesta
 from opencos.utils.str_helpers import sanitize_defines_for_sh
 
@@ -94,7 +94,8 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
             return
         if self.args['stop-after-compile']:
             vsim_command_lists = self.get_compile_command_lists()
-            self.run_commands_check_logs(vsim_command_lists, log_filename='sim.log')
+            self.run_commands_check_logs(vsim_command_lists, log_filename='sim.log',
+                                         must_strings=['Errors: 0'], use_must_strings=False)
 
     def elaborate(self):
         if self.args['stop-before-compile']:
@@ -200,6 +201,44 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
         with open(vlog_dot_f_fpath, 'w', encoding='utf-8') as f:
             f.writelines(line + "\n" for line in vlog_dot_f_lines)
 
+    def vopt_handle_parameters(self) -> (str, list):
+        '''Returns str for vopt or voptargs, and list of vopt tcl
+
+        Note this is used for self.use_vopt = True or False.
+        '''
+
+        voptargs_str = ''
+        vopt_do_lines = []
+
+        # Note that if self.use_vopt=True, we have to do some workarounds for how
+        # some questa-like tools behave for: tcl/.do + vopt arg processing
+        # This affects string based parameters that have spaces (vopt treats spaces unique args,
+        # vsim does not). Since we'd like to keep the vopt/vsim split into separate steps, we can
+        # work around this by setting tcl varaibles for each parameter.
+        if self.parameters:
+            if not self.use_vopt:
+                voptargs_str += ' ' + ' '.join(self.process_parameters_get_list(arg_prefix='-G'))
+            else:
+                for k,v in self.parameters.items():
+                    s = sim.parameters_dict_get_command_list(params={k: v}, arg_prefix='')[0]
+                    # At this point, s should be a str in form {k}={v}
+                    if not s or '=' not in s:
+                        continue
+                    if ' ' in s:
+                        # Instead of:
+                        #   vopt -GMyParam="hi bye"
+                        # we'll do:
+                        #   set PARAMETERS(MyParam) "hi bye"
+                        #  vopt -GMyParam=$PARAMETERS(MyParam)
+                        s = s.replace(f'{k}=', f'set PARAMETERS({k}) ')
+                        vopt_do_lines.append(s)
+                        voptargs_str += f' -G{k}=$PARAMETERS({k}) '
+                    else:
+                        voptargs_str += f' -G{s} '
+
+        return voptargs_str, vopt_do_lines
+
+
     def write_vsim_dot_do( # pylint: disable=too-many-locals
             self, dot_do_to_write: list
     ) -> None:
@@ -222,6 +261,14 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
                 typ='waveform', description='Modelsim/Questa Waveform WLF (Wave Log Format) file'
             )
 
+        vlog_do_lines = []
+        vsim_do_lines = []
+
+        # parameters, use helper method to get voptargs_str and vopt_do_lines
+        more_voptargs_str, vopt_do_lines = self.vopt_handle_parameters()
+        voptargs_str += more_voptargs_str
+
+
         # TODO(drew): support self.args['sim_libary', 'elab-args', sim-args'] (3 lists)
         # to add to vsim_one_liner.
 
@@ -246,7 +293,7 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
 
         vsim_one_liner = vsim_one_liner.replace('\n', ' ')
 
-        vlog_do_lines = [
+        vlog_do_lines += [
             "if {[file exists work]} { vdel -all work; }",
             "vlib work;",
             "quietly set qc 30;",
@@ -258,9 +305,8 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
             "}",
         ]
 
-        vopt_do_lines = []
         if self.use_vopt:
-            vopt_do_lines = [
+            vopt_do_lines += [
                 "if {[catch { " + vopt_one_liner + " } result] } {",
                 "    echo \"Caught $result\";",
                 "    if {[batch_mode]} {",
@@ -269,7 +315,7 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
                 "}",
             ]
 
-        vsim_do_lines = [
+        vsim_do_lines += [
             "if {[catch { " + vsim_one_liner + " } result] } {",
             "    echo \"Caught $result\";",
             "    if {[batch_mode]} {",

opencos/tools/quartus.py

@@ -19,6 +19,7 @@ from opencos.eda_base import Tool
 from opencos.commands import (
     CommandSynth, CommandBuild, CommandFList, CommandProj, CommandUpload, CommandOpen
 )
+from opencos.utils.str_helpers import sanitize_defines_for_sh, strip_outer_quotes
 
 class ToolQuartus(Tool):
     '''ToolQuartus used by opencos.eda for --tool=quartus'''
@@ -225,6 +226,18 @@ class CommandSynthQuartus(CommandSynth, ToolQuartus):
         for incdir in self.incdirs:
             tcl_lines.append(f"set_global_assignment -name SEARCH_PATH \"{incdir}\"")
 
+        # Parameters -->  set_parameter -name <Parameter_Name> <Value>
+        for k,v in self.parameters.items():
+            if not isinstance(v, (int, str)):
+                util.warning(f'parameter {k} has value: {v}, parameters must be int/string types')
+            if isinstance(v, int):
+                tcl_lines.append(f"set_parameter -name {k} {v}")
+            else:
+                v = strip_outer_quotes(v.strip('\n'))
+                v = '"' + v + '"'
+                tcl_lines.append(f"set_parameter -name {k} {sanitize_defines_for_sh(v)}")
+
+
         # Add all include directories as user libraries for better include resolution
         for incdir in self.incdirs:
             if os.path.exists(incdir):
@@ -307,7 +320,7 @@ class CommandBuildQuartus(CommandBuild, ToolQuartus):
             'flow-tcl-files': [],
         })
 
-    def do_it(self) -> None: # pylint: disable=too-many-branches,too-many-statements
+    def do_it(self) -> None: # pylint: disable=too-many-branches,too-many-statements,too-many-locals
         # add defines for this job
         self.set_tool_defines()
         self.write_eda_config_and_args()
@@ -340,15 +353,25 @@ class CommandBuildQuartus(CommandBuild, ToolQuartus):
         # create an eda.flist_input.f that we'll pass to flist:
         with open(os.path.join(self.args['work-dir'], 'eda.flist_input.f'),
                   'w', encoding='utf-8') as f:
+
+            # defines
+            for key,value in self.defines.items():
+                if value is None:
+                    f.write(f"+define+{key}\n")
+                else:
+                    f.write(shlex.quote(f"+define+{key}={value}") + "\n")
+
+            # incdirs:
+            for incdir in self.incdirs:
+                f.write(f'+incdir+{incdir}\n')
+
+            # files:
             f.write('\n'.join(self.files_v + self.files_sv + self.files_vhd + ['']))
+
+
         command_list.append('--input-file=eda.flist_input.f')
 
 
-        for key,value in self.defines.items():
-            if value is None:
-                command_list += [ f"+define+{key}" ]
-            else:
-                command_list += [ shlex.quote(f"+define+{key}={value}") ]
 
         # Write out a .sh command for debug
         command_list = util.ShellCommandList(command_list, tee_fpath='run_eda_flist.log')
@@ -487,6 +510,9 @@ class CommandFListQuartus(CommandFList, ToolQuartus):
     def __init__(self, config: dict):
         CommandFList.__init__(self, config=config)
         ToolQuartus.__init__(self, config=self.config)
+        self.args.update({
+            'emit-parameter': False
+        })
 
 
 class CommandProjQuartus(CommandProj, ToolQuartus):

opencos/tools/riviera.py

@@ -74,6 +74,17 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
     # Note: many of these we follow the same flow as CommandSimModelsimAse:
     # do_it, prepare_compile, compile, elaborate, simulate
 
+    def compile(self):
+        '''Override for CommandSimModelsimAse.compile() so we can set our own must_strings'''
+        if self.args['stop-before-compile']:
+            # don't run anything, save everyting we've already run in _prep_compile()
+            return
+        if self.args['stop-after-compile']:
+            vsim_command_lists = self.get_compile_command_lists()
+            self.run_commands_check_logs(vsim_command_lists, log_filename='sim.log',
+                                         must_strings=['Compile success 0 Errors'],
+                                         use_must_strings=False)
+
     def get_compile_command_lists(self, **kwargs) -> list:
         # This will also set up a compile.
         vsim_command_list = [
@@ -128,7 +139,6 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
             if v is None:
                 vlog_dot_f_lines += [ f'+define+{k}' ]
             else:
-
                 # if the value v is a double-quoted string, such as v='"hi"', the
                 # entire +define+NAME="hi" needs to wrapped in double quotes with the
                 # value v double-quotes escaped: "+define+NAME=\"hi\""
@@ -170,11 +180,15 @@ class CommandSimRiviera(CommandSimModelsimAse, ToolRiviera):
 
         voptargs_str = ""
         if self.args['gui'] or self.args['waves'] or self.args['coverage']:
-            voptargs_str = self.tool_config.get('simulate-waves-args',
-                                                '+accb +accr +access +r+w')
+            voptargs_str += self.tool_config.get('simulate-waves-args',
+                                                 '+accb +accr +access +r+w')
         if self.args['coverage']:
             voptargs_str += self.tool_config.get('coverage-args', '')
 
+        # parameters
+        if self.parameters:
+            voptargs_str += ' ' + ' '.join(self.process_parameters_get_list(arg_prefix='-G'))
+
         # TODO(drew): support self.args['sim_libary', 'elab-args', sim-args'] (3 lists)
         # to add to vsim_one_liner.
 

opencos/tools/slang.py

@@ -143,6 +143,11 @@ class CommandElabSlang(CommandElab, ToolSlang):
                 # --define-macro {k}={v}
                 command_list.append( f'{k}={sanitize_defines_for_sh(v)}' )
 
+        # parameters
+        command_list.extend(
+            self.process_parameters_get_list(arg_prefix='-G ')
+        )
+
         # Because many elab target-name won't match the --top needed for
         # slang, we'll leave this to arg --slang-top:
         if self.args.get('slang-top', None):

opencos/tools/slang_yosys.py

@@ -10,6 +10,8 @@ import os
 from opencos import util
 from opencos.tools.yosys import ToolYosys, CommonSynthYosys, CommandLecYosys
 
+from opencos.commands.sim import parameters_dict_get_command_list
+
 class ToolSlangYosys(ToolYosys):
     '''Uses slang.so in yosys plugins directory, called via yosys > plugin -i slang'''
     _TOOL = 'slang_yosys'
@@ -109,7 +111,17 @@ class CommandSynthSlangYosys(CommonSynthYosys, ToolSlangYosys):
         ]
 
         read_slang_cmd += self.get_yosys_read_verilog_defines_incdirs_files()
-        read_slang_cmd.append(f'--top {self.args["top"]}')
+
+        # For slang step, need to resolve parameters too. We do NOT do this on
+        # subsquent yosys read_verilog steps.
+        read_slang_cmd += parameters_dict_get_command_list(
+            params=self.parameters, arg_prefix='-G '
+        )
+
+        # In case --top was not set:
+        if not any(x.startswith('--top') for x in read_slang_cmd):
+            read_slang_cmd.append(f'--top {self.args["top"]}')
+
         return ' '.join(read_slang_cmd)
 
 

opencos/tools/surelog.py

@@ -109,6 +109,11 @@ class CommandElabSurelog(CommandElab, ToolSurelog):
         for value in self.incdirs:
             command_list.append('+incdir+' + value)
 
+        # parameters
+        command_list.extend(
+            self.process_parameters_get_list(arg_prefix='-P')
+        )
+
         # defines:
         for k,v in self.defines.items():
             if v is None:

opencos/tools/verilator.py

@@ -244,6 +244,11 @@ class VerilatorSim(CommandSim, ToolVerilator):
                 # +define+{k}={v}, but also for SystemVerilog plusargs
                 verilate_command_list += [ f'+define+{k}={sanitize_defines_for_sh(v)}' ]
 
+        # parameters
+        verilate_command_list.extend(
+            self.process_parameters_get_list(arg_prefix='-G')
+        )
+
         if not self.files_sv and not self.files_v:
             if not self.args['stop-before-compile']:
                 self.error(f'{self.target=} {self.files_sv=} and {self.files_v=} are empty,',

opencos/tools/vivado.py

@@ -22,6 +22,9 @@ from opencos.eda_base import Tool
 from opencos.commands import CommandSim, CommandSynth, CommandProj, CommandBuild, \
     CommandFList, CommandUpload, CommandOpen
 
+from opencos.commands import sim
+
+
 class ToolVivado(Tool):
     '''ToolVivado used by opencos.eda for --tool=vivado'''
 
@@ -214,6 +217,12 @@ class CommandSimVivado(CommandSim, ToolVivado):
             command_list[0] += ".bat"
         command_list += self.tool_config.get('elab-args',
                                              '-s snapshot -timescale 1ns/1ps --stats').split()
+
+        # parameters
+        command_list.extend(
+            self.process_parameters_get_list(arg_prefix='-generic_top ')
+        )
+
         if self.tool_config.get('elab-waves-args', ''):
             command_list += self.tool_config.get('elab-waves-args', '').split()
         elif self.args['gui'] and self.args['waves']:
@@ -412,6 +421,9 @@ class CommandSynthVivado(CommandSynth, ToolVivado):
         defines = ""
         for key, value in self.defines.items():
             defines += (f"-verilog_define {key}" + (" " if value is None else f"={value} "))
+        parameters = ' '.join(
+            sim.parameters_dict_get_command_list(params=self.parameters, arg_prefix='-generic ')
+        )
         incdirs = ' '.join([f'-include_dirs {x}' for x in self.incdirs])
         flatten = ""
         if self.args['flatten-all']:
@@ -457,10 +469,10 @@ class CommandSynthVivado(CommandSynth, ToolVivado):
         tcl_lines += [
             "# FIRST PASS -- auto_detect_xpm",
             "synth_design -rtl -rtl_skip_ip -rtl_skip_constraints -no_timing_driven -no_iobuf " \
-            + f"-top {top} {incdirs} {defines} {v}",
+            + f"-top {top} {incdirs} {defines} {parameters} {v}",
             f"auto_detect_xpm {v} ",
             f"synth_design -no_iobuf -part {part} {flatten} -constrset constraints_1 " \
-            + f"-top {top} {incdirs} {defines} {v}",
+            + f"-top {top} {incdirs} {defines} {parameters} {v}",
             f"write_verilog -force {top}.vg {v}",
             f"report_utilization -file {top}.flat.util.rpt {v}",
             f"report_utilization -file {top}.hier.util.rpt {v} -hierarchical " \
@@ -753,6 +765,7 @@ class CommandFListVivado(CommandFList, ToolVivado):
         CommandFList.__init__(self, config=config)
         ToolVivado.__init__(self, config=self.config)
         self.args['all-sv'] = False
+        self.args['emit-parameter'] = False
 
 
 class CommandUploadVivado(CommandUpload, ToolVivado):

opencos/tools/yosys.py

@@ -536,7 +536,6 @@ class CommandLecYosys(CommandLec, ToolYosys):
 
         self.synth_designs_tops = [None, None]
         self.synth_designs_fpaths = [None, None]
-        self.synth_design_top_module_names = [None, None]
 
     def get_synth_result_fpath(self, target: str) -> str:
         '''Overridden from CommandLec'''
@@ -547,7 +546,7 @@ class CommandLecYosys(CommandLec, ToolYosys):
     def get_synth_command_list(self, design_num: int) -> list:
         '''Returns one of the synthesis command lists, for design_num=0 or 1'''
 
-        if not design_num in [0, 1]:
+        if not design_num in (0, 1):
             self.error(f'{design_num=} we only support LEC on designs 0 and 1')
 
         synth_cmd_list = [
@@ -561,31 +560,43 @@ class CommandLecYosys(CommandLec, ToolYosys):
         synth_cmd_list += [
             '--work-dir=' + self.synth_work_dirs[design_num],
             self.args['designs'][design_num],
-            f'--rename-module=Design{design_num + 1}'
+            f'--rename-module=Design{design_num + 1}',
         ]
 
-        self.synth_design_top_module_names[design_num] = f'Design{design_num + 1}'
+        if self.args['flatten-all']:
+            # We have to do this or may get conflicts on black-boxed modules, but can
+            # be avoided with --no-flatten-all.
+            synth_cmd_list.append(
+                '--flatten-all'
+            )
+
+        self.synth_designs_tops[design_num] = f'Design{design_num + 1}'
 
         return synth_cmd_list
 
 
-    def get_synth_top_from_output_config(self, design_num: int) -> str:
-        '''Returns the top name given the design number that we synthesized'''
+    def get_synth_top_from_output_config(self, design_num: int) -> (str, str):
+        '''Returns the (orignal top name, module name) tuple given the design number
+
+        that we synthesized'''
 
         work_dir = self.synth_work_dirs[design_num]
         output_cfg_fpath = os.path.join(work_dir, eda_config.EDA_OUTPUT_CONFIG_FNAME)
         data = yaml_safe_load(output_cfg_fpath)
         top = data.get('args', {}).get('top', '')
-        if not top:
+        rename_module = data.get('args', {}).get('rename-module', '')
+        if not top and not rename_module:
             self.error(f'"top" not found in synth run from {work_dir=} in',
                        f'config {output_cfg_fpath}')
-        return top
+        if not rename_module:
+            return top, top
+        return top, rename_module
 
 
     def get_synth_results_fpath(self, design_num: int, top: str) -> str:
-        '''Returns the synthesized .v file fpath'''
+        '''Returns the synthesized .v file fpath, using orignal top (not renamed)'''
         if not top:
-            top = self.get_synth_top_from_output_config(design_num=design_num)
+            top, _ = self.get_synth_top_from_output_config(design_num=design_num)
 
         work_dir = self.synth_work_dirs[design_num]
         fpath = os.path.join(work_dir, 'yosys', f'{top}.v')
@@ -594,7 +605,7 @@ class CommandLecYosys(CommandLec, ToolYosys):
         return fpath
 
 
-    def do_it(self) -> None:
+    def do_it(self) -> None: # pylint: disable=too-many-locals,too-many-statements,too-many-branches
         self.set_tool_defines()
         self.write_eda_config_and_args()
 
@@ -622,6 +633,9 @@ class CommandLecYosys(CommandLec, ToolYosys):
                     self.exec(work_dir=self.args['work-dir'], command_list=x,
                               tee_fpath=x.tee_fpath)
 
+            util.info(f'LEC ran via --yosys-scriptfile: {self.args["yosys-scriptfile"]}')
+            return
+
 
         if self.args['synth']:
             synth1_cmd_list = self.get_synth_command_list(design_num=0)
@@ -636,23 +650,23 @@ class CommandLecYosys(CommandLec, ToolYosys):
             self.exec(pwd, synth2_cmd_list, background=True)
             util.info(f'Finished with 2nd LEC synthesis {self.args["designs"][1]}')
 
-            self.synth_designs_tops = [
-                self.get_synth_top_from_output_config(design_num=0),
-                self.get_synth_top_from_output_config(design_num=1)
-            ]
+
+            top0, module0 = self.get_synth_top_from_output_config(design_num=0)
+            top1, module1 = self.get_synth_top_from_output_config(design_num=1)
+            self.synth_designs_tops = [module0, module1]
             util.info(f'Design tops: {self.synth_designs_tops}')
 
             # read the output config
             self.synth_designs_fpaths = [
                 os.path.abspath(
-                    self.get_synth_results_fpath(design_num=0, top=self.synth_designs_tops[0])),
+                    self.get_synth_results_fpath(design_num=0, top=top0)),
                 os.path.abspath(
-                    self.get_synth_results_fpath(design_num=1, top=self.synth_designs_tops[1]))
+                    self.get_synth_results_fpath(design_num=1, top=top1))
             ]
             util.info(f'Design tops: {self.synth_designs_fpaths}')
 
         else:
-            # don't run synthesis, need the two top level .v files in
+            # don't run synthesis, need the two top level .v|.sv files in
             # self.synth_designs_fpaths, and need the two top module names in
             # self.synth_designs_tops
             self.synth_designs_fpaths = [
@@ -660,11 +674,19 @@ class CommandLecYosys(CommandLec, ToolYosys):
                 os.path.abspath(self.args['designs'][1])
             ]
 
+            for i in (0, 1):
+                if not os.path.isfile(self.args['designs'][i]):
+                    self.error(
+                        'Using synth=False (--no-synth) --designs=<value> must be a single',
+                        f'filename, however {self.args["designs"][i]} does not exist'
+                    )
+
             path, fname = os.path.split(self.synth_designs_fpaths[0])
             module_guess, _ = os.path.splitext(fname)
             top1 = util.get_inferred_top_module_name(
                 module_guess=module_guess, module_fpath=self.synth_designs_fpaths[0]
             )
+            util.debug(f'design1 {module_guess=} {fname=} {path=}')
             util.info(f'design1 top module name = {top1} (from {path} / {fname})')
 
             path, fname = os.path.split(self.synth_designs_fpaths[1])
@@ -672,6 +694,7 @@ class CommandLecYosys(CommandLec, ToolYosys):
             top2 = util.get_inferred_top_module_name(
                 module_guess=module_guess, module_fpath=self.synth_designs_fpaths[1]
             )
+            util.debug(f'design2 {module_guess=} {fname=} {path=}')
             util.info(f'design2 top module name = {top2} (from {path} / {fname})')
 
             self.synth_designs_tops = [top1, top2]
@@ -691,13 +714,20 @@ class CommandLecYosys(CommandLec, ToolYosys):
                     ]
                 else:
                     self.error(f' --pre-read-verilog file {x} does not exist')
+
+        nooverwrite = ''
+        if self.args['synth'] and not self.args['flatten-all']:
+            # If we don't flatten-all from synthesis, and we had to run synthesis,
+            # then read the 2nd file with -overwrite
+            nooverwrite = '-nooverwrite'
+
         lec_cmd_f_list += [
             '# Design1 (module):',
             f'read_verilog -sv -icells {self.synth_designs_fpaths[0]}',
             '# Design2 (module):',
-            f'read_verilog -sv -icells {self.synth_designs_fpaths[1]}',
+            f'read_verilog -sv -icells {self.synth_designs_fpaths[1]} {nooverwrite}',
             'clk2fflogic;',
-            f'miter -equiv -flatten {" ".join(self.synth_design_top_module_names)} miter',
+            f'miter -equiv -flatten {" ".join(self.synth_designs_tops)} miter',
             ('sat -seq 50 -verify -prove trigger 0 -show-all -show-inputs -show-outputs'
              ' -set-init-zero miter'),
         ]