opencos-eda 0.2.49__py3-none-any.whl → 0.2.51__py3-none-any.whl

opencos/eda_config_defaults.yml

@@ -230,17 +230,39 @@ tools:
     compile-args: |
       -sv -svinputport=net -lint
     compile-waivers:
-      - 2275 # 2275 - Existing package 'foo_pkg' will be overwritten.
-      - 2555 # 2555 - assignment to input port foo
+      - 2275 # 2275 - Existing package 'myname_pkg' will be overwritten.
+      - 2555 # 2555 - assignment to input port myname
       - 2583 # 2583 - [SVCHK] - Extra checking for conflicts with always_comb and
              #        always_latch variables is done at vopt time.
     simulate-waivers:
-      - 3009 # 3009: [TSCALE] - Module 'foo' does not have a timeunit/timeprecision
+      - 3009 # 3009: [TSCALE] - Module 'myname' does not have a timeunit/timeprecision
              #       specification in effect, but other modules do.
     simulate-waves-args: |
       +acc
 
 
+  questa_fse:
+    defines:
+      OC_TOOL_QUESTA_FSE: 1
+    log-bad-strings:
+      - "Error:"
+    log-must-strings:
+      - " vsim "
+      - "Errors: 0"
+    compile-args: |
+      -sv -svinputport=net -lint
+    compile-waivers:
+      - 2275 # 2275 - Existing package 'myname_pkg' will be overwritten.
+      - 2555 # 2555 - assignment to input port myname
+      - 2583 # 2583 - [SVCHK] - Extra checking for conflicts with always_comb and
+             #        always_latch variables is done at vopt time.
+    simulate-waivers:
+      - 3009 # 3009: [TSCALE] - Module 'myname' does not have a timeunit/timeprecision
+             #       specification in effect, but other modules do.
+    simulate-waves-args: |
+      -voptargs=+acc=bcgnprst
+
+
   iverilog:
     log-bad-strings:
       - "Error:"
@@ -303,7 +325,7 @@ auto_tools_order:
     # TODO(drew): surelog is disabled from `eda tools-multi`. It is still
     # enabled for `eda [multi] elab --tool surelog`. It does not support
     # type comparisons:
-    #   if type(foo) == type(bar)
+    #   if type(myname) == type(othername)
     # [ERR:UH0700] ... Unsupported expression
     # modelsim_ase also doesn't, but it won't fail elab, whereas surelog does.
     surelog:
@@ -376,9 +398,7 @@ auto_tools_order:
 
     questa:
       exe: qrun
-      requires_cmd:
-        - qrun -version
-        - vsim -version
+      requires_vsim_helper: True
       handlers:
         elab: opencos.tools.queta.CommandElabQuesta
         sim: opencos.tools.queta.CommandSimQuesta
@@ -386,24 +406,26 @@ auto_tools_order:
     riviera:
       exe: vsim
       requires_cmd:
-        - vsim -version
         - which riviera  # Do not run it, make sure it's in PATH
-      requires_in_exe_path:
-        - riviera
+      requires_vsim_helper: True
       handlers:
         elab: opencos.tools.riviera.CommandElabRiviera
         sim:  opencos.tools.riviera.CommandSimRiviera
 
     modelsim_ase:
       exe: vsim
-      requires_cmd:
-        - vsim -version
-      requires_in_exe_path:
-        - modelsim
+      requires_vsim_helper: True
       handlers:
         elab: opencos.tools.modelsim_ase.CommandElabModelsimAse
         sim:  opencos.tools.modelsim_ase.CommandSimModelsimAse
 
+    questa_fse:  # free student edition, works similar to modelsim_ase
+      exe: vsim
+      requires_vsim_helper: True
+      handlers:
+        elab: opencos.tools.questa_fse.CommandElabQuestaFse
+        sim:  opencos.tools.questa_fse.CommandSimQuestaFse
+
     iverilog:
       exe: iverilog
       handlers:

opencos/eda_deps_sanitize.py

@@ -0,0 +1,73 @@
+#!/usr/bin/env python3
+
+'''opencos.eda_deps_sanitize is an executable script
+
+Usage:
+    eda_deps_sanitize --dir=<path>
+
+Will print santized JSON data for the DEPS file found in --dir=<path>
+'''
+
+import argparse
+import os
+import sys
+
+from pathlib import Path
+
+from opencos import util
+from opencos.deps import deps_file
+from opencos.utils import status_constants
+
+
+def run(*args) -> (int, str):
+    '''Runs the DEPS sanitizer, prints results to stdout'''
+
+
+    bool_kwargs = util.get_argparse_bool_action_kwargs()
+
+    parser = argparse.ArgumentParser(
+        prog='opencos eda_deps_sanitize', add_help=True, allow_abbrev=False
+    )
+
+    parser.add_argument('--yaml', **bool_kwargs,
+                        help='Print output as YAML text, otherwise default is JSON text')
+    parser.add_argument('dir', type=str, default=str(Path('.')),
+                        help='Directory to look for DEPS.[markup] file')
+
+    try:
+        parsed, unparsed = parser.parse_known_args(list(args) + [''])
+        unparsed = list(filter(None, unparsed))
+    except argparse.ArgumentError:
+        return 1, f'problem attempting to parse_known_args for {args=}'
+
+    deps_path = parsed.dir
+    if os.path.isfile(deps_path):
+        deps_path, _ = os.path.split(deps_path)
+
+    try:
+        my_depsfile_obj = deps_file.DepsFile(None, deps_path, {})
+        if not my_depsfile_obj.deps_file:
+            return status_constants.EDA_DEPS_FILE_NOT_FOUND, f'No DEPS markup file at {parsed.dir}'
+
+        ret_str = my_depsfile_obj.str_sanitized_markup(as_yaml=parsed.yaml)
+        rc = util.get_return_code()
+        return rc, ret_str
+    except Exception as e:
+        rc = 1, str(e)
+
+    return 0, ''
+
+
+def main() -> None:
+    '''calls sys.exit(), main entrypoint'''
+    args = []
+    if len(sys.argv) > 1 and not args:
+        args = sys.argv[1:]
+
+    rc, deps_str = run(*args)
+    print(deps_str)
+    sys.exit(rc)
+
+
+if __name__ == '__main__':
+    main()

opencos/tests/test_eda_elab.py

@@ -22,7 +22,8 @@ list_of_elab_tools = [
     'slang',
     'verilator',
     'vivado',
-    'modelsim_ase',
+    'modelsim_ase'
+    'questa_fse',
     'invio',
     'surelog',
     'invio_yosys',

opencos/tests/test_tools.py

@@ -73,6 +73,7 @@ list_of_tools = [
     'verilator',
     'vivado',
     'modelsim_ase',
+    'questa_fse',
 ]
 
 list_of_deps_targets = [

opencos/tools/modelsim_ase.py

@@ -1,6 +1,8 @@
 ''' opencos.tools.modelsim_ase - Used by opencos.eda for sim/elab commands w/ --tool=modelsim_ase.
 
 Contains classes for ToolModelsimAse, CommandSimModelsimAse, CommandElabModelsimAse.
+
+Note that this is for 32-bit Modelsim Student Edition. Consider using --tool=questa_fse instead.
 '''
 
 # pylint: disable=R0801 # (duplicate code in derived classes, such as if-condition return.)
@@ -151,6 +153,9 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
                 ]):
             vlog_dot_f_lines += ['-suppress', str(waiver)]
 
+        if self.args['gui'] or self.args['waves']:
+            vlog_dot_f_lines += self.tool_config.get('compile-waves-args', '').split()
+
         vlog_dot_f_fname = filename
         vlog_dot_f_fpath = os.path.join(self.args['work-dir'], vlog_dot_f_fname)
 
@@ -203,6 +208,10 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
         voptargs_str = ""
         if self.args['gui'] or self.args['waves']:
             voptargs_str = self.tool_config.get('simulate-waves-args', '+acc')
+            util.artifacts.add_extension(
+                search_paths=self.args['work-dir'], file_extension='wlf',
+                typ='waveform', description='Modelsim/Questa Waveform WLF (Wave Log Format) file'
+            )
 
         # TODO(drew): support self.args['sim_libary', 'elab-args', sim-args'] (3 lists)
         # to add to vsim_one_liner.
@@ -331,6 +340,19 @@ class CommandSimModelsimAse(CommandSim, ToolModelsimAse):
         return ' '.join(vsim_suppress_list)
 
 
+    def artifacts_add(self, name: str, typ: str, description: str) -> None:
+        '''Override from Command.artifacts_add, so we can catch known file
+
+        names to make their typ/description better, such as CommandSim using
+        sim.log
+        '''
+        _, leafname = os.path.split(name)
+        if leafname == 'sim.log':
+            description = 'Modelsim/Questa Transcript log file'
+
+        super().artifacts_add(name=name, typ=typ, description=description)
+
+
 class CommandElabModelsimAse(CommandSimModelsimAse):
     '''CommandElabModelsimAse is a command handler for: eda elab --tool=modelsim_ase'''
 

opencos/tools/questa.py

@@ -40,9 +40,11 @@ class ToolQuesta(Tool):
             self.error(f"{self._EXE} not in path, need to setup",
                        "(i.e. source /opt/intelFPGA_pro/23.4/settings64.sh")
             util.debug(f"{path=}")
-            if self._EXE.endswith('qrun') and 'modelsim_ase' in path:
-                util.warning(f"{self._EXE=} Questa path is for starter edition (modelsim_ase),",
-                             "consider using --tool modelsim_ase")
+            if self._EXE.endswith('qrun') and \
+               any(x in path for x in ('modelsim_ase', 'questa_fse')):
+                util.warning(f"{self._EXE=} Questa path is for starter edition",
+                             "(modelsim_ase, questa_fse), consider using --tool=modelsim_ase",
+                             "or --tool=questa_fse")
         else:
             self.sim_exe = path
             self.sim_exe_base_path, _ = os.path.split(path)

opencos/tools/questa_fse.py

@@ -0,0 +1,59 @@
+''' opencos.tools.questa_fse - Used by opencos.eda for sim/elab commands w/ --tool=questa_fse.
+
+Contains classes for CommandSimQuestaFse, CommandElabQuestaFse.
+For: Questa Intel Starter FPGA Edition-64 vsim 20XX.X Simulator
+
+'''
+
+# pylint: disable=R0801 # (duplicate code in derived classes, such as if-condition return.)
+# pylint: disable=too-many-ancestors
+
+import os
+
+from opencos.tools.modelsim_ase import CommandSimModelsimAse
+
+
+class CommandSimQuestaFse(CommandSimModelsimAse):
+    '''CommandSimQuestaFse is a command handler for: eda sim --tool=questa_fse
+
+    Note this inherits 99% from CommandSimModelSimAse for command handling
+    '''
+    _TOOL = 'questa_fse'
+    _EXE = 'vsim'
+
+    def __init__(self, config: dict):
+        # this will setup with self._TOOL = modelsim_ase, which is not ideal so
+        # we have to repait it later.
+        CommandSimModelsimAse.__init__(self, config=config)
+
+        # repairs: override self._TOOL, and run get_versions() again.
+        self._TOOL = 'questa_fse'
+
+        self.shell_command = os.path.join(self.sim_exe_base_path, 'vsim')
+        self.starter_edition = True
+        self.args.update({
+            'tool': self._TOOL, # override
+            'gui': False,
+        })
+
+
+    def set_tool_defines(self):
+        '''Override from questa.ToolQuesta'''
+        # Update any defines from config.tools.questa_fse:
+        self.defines.update(
+            self.tool_config.get(
+                'defines',
+                # defaults, if not set:
+                {
+                 'OC_TOOL_QUESTA_FSE': 1
+                }
+            )
+        )
+
+
+class CommandElabQuestaFse(CommandSimQuestaFse):
+    '''CommandElabQuestaFse is a command handler for: eda elab --tool=questa_fse'''
+
+    def __init__(self, config:dict):
+        super().__init__(config)
+        self.args['stop-after-elaborate'] = True

opencos/tools/slang.py

@@ -191,14 +191,20 @@ class CommandElabSlang(CommandElab, ToolSlang):
 
         return command_list
 
-    def _get_slang_json_args(self, command_exe:str) -> list:
+    def _get_slang_json_args(self, command_exe: str) -> list:
         command_list = []
 
-        if self.args.get('slang-json', False) and command_exe == 'slang':
+        _, command_exe_leaf = os.path.split(command_exe)
+        if self.args.get('slang-json', False) and command_exe_leaf == 'slang':
             for arg in self.all_json_args:
                 if arg not in command_list:
                     command_list.append(arg)
                     if arg == '--ast-json': # needs filename
                         command_list.append('slang.json')
+                        util.artifacts.add(
+                            name=os.path.join(self.args['work-dir'], 'slang.json'),
+                            typ='json',
+                            description='Abstract syntax tree from slang --ast-json'
+                        )
 
         return command_list

opencos/tools/verilator.py

@@ -346,6 +346,16 @@ class VerilatorSim(CommandSim, ToolVerilator):
             util.info(f'--waves arg present, no $dumpfile found, adding SV file: {file_to_add}')
             self.add_file(file_to_add)
 
+        # register .vcd or .fst artifacts:
+        util.artifacts.add_extension(
+            search_paths=self.args['work-dir'], file_extension='fst',
+            typ='waveform', description='Simulation Waveform FST (Fast Signal Trace) file'
+        )
+        util.artifacts.add_extension(
+            search_paths=self.args['work-dir'], file_extension='vcd',
+            typ='waveform', description='Simulation Waveform VCD (Value Change Dump) file'
+        )
+
 
     def _get_start_verilator_command_list(self, lint_only: bool = False) -> list:
 
@@ -447,6 +457,21 @@ class VerilatorSim(CommandSim, ToolVerilator):
         return verilate_args
 
 
+    def artifacts_add(self, name: str, typ: str, description: str) -> None:
+        '''Override from Command.artifacts_add, so we can catch known file
+
+        names to make their typ/description better, such as CommandSim using
+        sim.log or compile.log
+        '''
+        _, leafname = os.path.split(name)
+        if leafname == 'sim.log':
+            description = 'Verilated executable log from stdout/stderr'
+        elif leafname == 'compile.log':
+            description = 'Verilator compile step log from verilator call'
+
+        super().artifacts_add(name=name, typ=typ, description=description)
+
+
 class VerilatorElab(VerilatorSim):
     '''VerilatorElab is a command handler for: eda elab --tool=verilator'''
 

opencos/tools/vivado.py

@@ -63,29 +63,14 @@ class ToolVivado(Tool):
             util.info("environment for XILINX_VIVADO is not set or doesn't match the vivado path:",
                       f"XILINX_VIVADO={xilinx_vivado} EXE PATH={self.vivado_exe}")
 
-        version = None
-        # Note this is commented out b/c it's a bit slow, up to 1.0 second to
-        # run their tool just to query the version information.
-        # Do this if you need the extra minor version like 2024.2.1.
-        #try:
-        #    # Get version from vivado -version, or xsim --version:
-        #    vivado_ret = subprocess.run(['vivado', '-version'], capture_output=True)
-        #    lines = vivado_ret.stdout.decode('utf-8', errors='replace').split('\n')
-        #    words = lines[0].split() # vivado v2024.2.1 (64-bit)
-        #    version = words[1][1:] # 2024.2.1
-        #    self._VERSION = version
-        #except:
-        #    pass
-
-        if not version:
-            # Get version based on install path name:
-            util.debug(f"vivado path = {self.vivado_exe}")
-            m = re.search(r'(\d\d\d\d)\.(\d)', self.vivado_exe)
-            if m:
-                version = m.group(1) + '.' + m.group(2)
-                self._VERSION = version
-            else:
-                self.error("Vivado path doesn't specificy version, expecting (dddd.d)")
+        # Get version based on install path name. Calling vivado -verison is too slow.
+        util.debug(f"vivado path = {self.vivado_exe}")
+        m = re.search(r'(\d\d\d\d)\.(\d)', self.vivado_exe)
+        if m:
+            version = m.group(1) + '.' + m.group(2)
+            self._VERSION = version
+        else:
+            self.error("Vivado path doesn't specificy version, expecting (dddd.d)")
 
         if version:
             numbers_list = version.split('.')
@@ -260,6 +245,14 @@ class CommandSimVivado(CommandSim, ToolVivado):
     def get_simulate_command_lists(self, **kwargs) -> list:
         # create TCL
         tcl_name = os.path.abspath(os.path.join(self.args['work-dir'], self.args['tcl-file']))
+
+        if self.args['waves']:
+            util.artifacts.add_extension(
+                search_paths=self.args['work-dir'], file_extension='wdb',
+                typ='waveform', description='Vivado XSim Waveform WDB (Wave DataBase) file'
+            )
+
+
         with open( tcl_name, 'w', encoding='utf-8' ) as fo:
             if self.args['waves']:
                 if self.args['waves-start']:
@@ -345,6 +338,23 @@ class CommandSimVivado(CommandSim, ToolVivado):
             self.files_v.insert(0, glbl_v)
 
 
+    def artifacts_add(self, name: str, typ: str, description: str) -> None:
+        '''Override from Command.artifacts_add, so we can catch known file
+
+        names to make their typ/description better, such as CommandSim using
+        sim.log or compile.log
+        '''
+        _, leafname = os.path.split(name)
+        if leafname == 'xsim.log':
+            description = 'Vivado XSim simulation step (3/3) log from stdout/stderr'
+        elif leafname == 'xelab.log':
+            description = 'Vivado XSim elaboration step (2/3) log from stdout/stderr'
+        elif leafname == 'xvlog.log':
+            description = 'Vivado XSim compile step (1/3) log from stdout/stderr'
+
+        super().artifacts_add(name=name, typ=typ, description=description)
+
+
 class CommandElabVivado(CommandSimVivado):
     '''CommandElabVivado is a command handler for: eda elab --tool=vivado, uses xvlog, xelab'''
     def __init__(self, config: dict):
@@ -933,9 +943,6 @@ class CommandUploadVivado(CommandUpload, ToolVivado):
         util.info("Upload done")
 
 
-
-
-
 class CommandOpenVivado(CommandOpen, ToolVivado):
     '''CommandOpenVivado command handler class used by: eda open --tool vivado'''
     def __init__(self, config: dict):

opencos/tools/yosys.py

@@ -117,6 +117,7 @@ class CommonSynthYosys(CommandSynth, ToolYosys):
             'yosys-blackbox': [],                # list of modules that yosys will blackbox.
             'yosys-scriptfile': [],
             'sta-scriptfile': [],
+            'rename-module': ''
         })
         self.args_help.update({
             'sta': (
@@ -150,12 +151,14 @@ class CommonSynthYosys(CommandSynth, ToolYosys):
                 ' via: sta -no_init -exit <this-arg>.  You can set multiple args for multiple'
                 ' scriptfile (appends)'
             ),
+            'rename-module': 'Renames the output .v and module name',
         })
 
         self.yosys_out_dir = ''
         self.yosys_v_path = ''
         self.full_work_dir = ''
         self.blackbox_list = []
+        self.top_module = ''
 
     def do_it(self) -> None:
         self.set_tool_defines()
@@ -333,6 +336,13 @@ class CommonSynthYosys(CommandSynth, ToolYosys):
             ]
         lines += [
             'opt_clean',
+        ]
+        if self.args['rename-module']:
+            lines += [f'rename {self.args["top"]} {self.args["rename-module"]}']
+            self.top_module = self.args['rename-module']
+        else:
+            self.top_module = self.args["top"]
+        lines += [
             f'write_verilog {self.yosys_v_path}',
             f'write_json {self.yosys_v_path}.json',
         ]
@@ -388,7 +398,7 @@ class CommonSynthYosys(CommandSynth, ToolYosys):
             lines = [
                 'read_liberty ' + self.args['liberty-file'],
                 'read_verilog ' + self.yosys_v_path,
-                'link_design ' + self.args['top'],
+                'link_design ' + self.top_module,
             ]
             for _file in self.files_sdc:
                 lines.append('read_sdc ' + _file)
@@ -505,12 +515,13 @@ class CommandLecYosys(CommandLec, ToolYosys):
         })
 
         self.synth_work_dirs = [
-            os.path.join('eda.work', 'lec.design1.synth'),
-            os.path.join('eda.work', 'lec.design2.synth')
+            os.path.join('eda.work', 'lec.Design1.synth'),
+            os.path.join('eda.work', 'lec.Design2.synth')
         ]
 
         self.synth_designs_tops = [None, None]
         self.synth_designs_fpaths = [None, None]
+        self.synth_design_top_module_names = [None, None]
 
     def get_synth_result_fpath(self, target: str) -> str:
         '''Overridden from CommandLec'''
@@ -534,9 +545,12 @@ class CommandLecYosys(CommandLec, ToolYosys):
 
         synth_cmd_list += [
             '--work-dir=' + self.synth_work_dirs[design_num],
-            self.args['designs'][design_num]
+            self.args['designs'][design_num],
+            f'--rename-module=Design{design_num + 1}'
         ]
 
+        self.synth_design_top_module_names[design_num] = f'Design{design_num + 1}'
+
         return synth_cmd_list
 
 
@@ -663,10 +677,12 @@ class CommandLecYosys(CommandLec, ToolYosys):
                 else:
                     self.error(f' --pre-read-verilog file {x} does not exist')
         lec_cmd_f_list += [
+            '# Design1 (module):',
             f'read_verilog -sv -icells {self.synth_designs_fpaths[0]}',
+            '# Design2 (module):',
             f'read_verilog -sv -icells {self.synth_designs_fpaths[1]}',
             'clk2fflogic;',
-            f'miter -equiv -flatten {" ".join(self.synth_designs_tops)} miter',
+            f'miter -equiv -flatten {" ".join(self.synth_design_top_module_names)} miter',
             ('sat -seq 50 -verify -prove trigger 0 -show-all -show-inputs -show-outputs'
              ' -set-init-zero miter'),
         ]