nvidia-cudnn-cu12 9.5.1.17__py3-none-win_amd64.whl → 9.7.0.66__py3-none-win_amd64.whl

nvidia/cudnn/include/cudnn_adv.h

@@ -61,8 +61,8 @@
 
 /* These version numbers are autogenerated, do not edit manually. */
 #define CUDNN_ADV_MAJOR 9
-#define CUDNN_ADV_MINOR 5
-#define CUDNN_ADV_PATCH 1
+#define CUDNN_ADV_MINOR 7
+#define CUDNN_ADV_PATCH 0
 
 #if (CUDNN_ADV_MAJOR != CUDNN_MAJOR) || (CUDNN_ADV_MINOR != CUDNN_MINOR) || (CUDNN_ADV_PATCH != CUDNN_PATCHLEVEL)
 #error Version mismatch in cuDNN ADV INFER!!!

nvidia/cudnn/include/cudnn_cnn.h

@@ -62,8 +62,8 @@
 
 /* These version numbers are autogenerated, do not edit manually. */
 #define CUDNN_CNN_MAJOR 9
-#define CUDNN_CNN_MINOR 5
-#define CUDNN_CNN_PATCH 1
+#define CUDNN_CNN_MINOR 7
+#define CUDNN_CNN_PATCH 0
 
 #if (CUDNN_CNN_MAJOR != CUDNN_MAJOR) || (CUDNN_CNN_MINOR != CUDNN_MINOR) || (CUDNN_CNN_PATCH != CUDNN_PATCHLEVEL)
 #error Version mismatch in cuDNN CNN INFER!!!

nvidia/cudnn/include/cudnn_graph.h

@@ -63,8 +63,8 @@
 
 /* These version numbers are autogenerated, do not edit manually. */
 #define CUDNN_GRAPH_MAJOR 9
-#define CUDNN_GRAPH_MINOR 5
-#define CUDNN_GRAPH_PATCH 1
+#define CUDNN_GRAPH_MINOR 7
+#define CUDNN_GRAPH_PATCH 0
 
 #if (CUDNN_GRAPH_MAJOR != CUDNN_MAJOR) || (CUDNN_GRAPH_MINOR != CUDNN_MINOR) || (CUDNN_GRAPH_PATCH != CUDNN_PATCHLEVEL)
 #error Version mismatch in cuDNN GRAPH!!!
@@ -141,6 +141,7 @@ typedef enum {
     CUDNN_STATUS_BAD_PARAM_DUPLICATED_ENTRIES  = 2009,
     CUDNN_STATUS_BAD_PARAM_ATTRIBUTE_TYPE      = 2010,
     CUDNN_STATUS_BAD_PARAM_CUDA_GRAPH_MISMATCH = 2011,
+    CUDNN_STATUS_BAD_PARAM_DESCRIPTOR_TYPE     = 2012,
 
     CUDNN_STATUS_NOT_SUPPORTED                              = 3000,
     CUDNN_STATUS_NOT_SUPPORTED_GRAPH_PATTERN                = 3001,
@@ -233,6 +234,8 @@ typedef enum {
     CUDNN_DATA_FP8_E4M3                      = 12,
     CUDNN_DATA_FP8_E5M2                      = 13,
     CUDNN_DATA_FAST_FLOAT_FOR_FP8            = 14,
+    CUDNN_DATA_FP8_E8M0                      = 15,
+    CUDNN_DATA_FP4_E2M1                      = 16,
 } cudnnDataType_t;
 
 /*
@@ -560,6 +563,7 @@ typedef enum {
     CUDNN_ATTR_OPERATIONGRAPH_OPS                      = 801,
     CUDNN_ATTR_OPERATIONGRAPH_ENGINE_GLOBAL_COUNT      = 802,
     CUDNN_ATTR_OPERATIONGRAPH_IS_DYNAMIC_SHAPE_ENABLED = 803,
+    CUDNN_ATTR_OPERATIONGRAPH_IS_SAME_TOPOLOGY         = 804,
 
     CUDNN_ATTR_TENSOR_BYTE_ALIGNMENT       = 900,
     CUDNN_ATTR_TENSOR_DATA_TYPE            = 901,
@@ -711,7 +715,20 @@ typedef enum {
     CUDNN_ATTR_OPERATION_RNG_OFFSET_DESC = 2313,
 
     CUDNN_ATTR_KERNEL_CACHE_OPERATION_GRAPH            = 2400,
-    CUDNN_ATTR_KERNEL_CACHE_IS_ENGINECFG_KERNEL_CACHED = 2401
+    CUDNN_ATTR_KERNEL_CACHE_IS_ENGINECFG_KERNEL_CACHED = 2401,
+
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_QUANTIZE_XDESC             = 2500,
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_QUANTIZE_YDESC             = 2501,
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_QUANTIZE_SCALE_DESC        = 2502,
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_QUANTIZE_MATH_PREC         = 2503,
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_QUANTIZE_BLOCK_SIZE        = 2504,
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_QUANTIZE_DENOM_FACTOR_MODE = 2505,
+
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_DEQUANTIZE_XDESC      = 2600,
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_DEQUANTIZE_SCALE_DESC = 2601,
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_DEQUANTIZE_YDESC      = 2602,
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_DEQUANTIZE_MATH_PREC  = 2603,
+    CUDNN_ATTR_OPERATION_BLOCK_SCALE_DEQUANTIZE_BLOCK_SIZE = 2604,
 
 } cudnnBackendAttributeName_t;
 
@@ -745,7 +762,7 @@ typedef enum {
     CUDNN_TYPE_FRACTION,
     CUDNN_TYPE_NORM_MODE,
     CUDNN_TYPE_NORM_FWD_PHASE,
-    CUDNN_TYPE_RNG_DISTRIBUTION
+    CUDNN_TYPE_RNG_DISTRIBUTION,
 } cudnnBackendAttributeType_t;
 
 typedef enum {
@@ -785,6 +802,8 @@ typedef enum {
     CUDNN_BACKEND_OPERATION_RNG_DESCRIPTOR,
     CUDNN_BACKEND_KERNEL_CACHE_DESCRIPTOR,
     CUDNN_BACKEND_OPERATION_PAGED_CACHE_LOAD_DESCRIPTOR,
+    CUDNN_BACKEND_OPERATION_BLOCK_SCALE_QUANTIZE_DESCRIPTOR,
+    CUDNN_BACKEND_OPERATION_BLOCK_SCALE_DEQUANTIZE_DESCRIPTOR,
 } cudnnBackendDescriptorType_t;
 
 typedef enum {
@@ -828,7 +847,7 @@ typedef enum {
     CUDNN_KNOB_TYPE_REDUCTION_MODE                         = 15,
     CUDNN_KNOB_TYPE_CTA_SPLIT_K_MODE CUDNN_DEPRECATED_ENUM = 16,
     CUDNN_KNOB_TYPE_SPLIT_K_SLC                            = 17,
-    CUDNN_KNOB_TYPE_IDX_MODE CUDNN_DEPRECATED_ENUM         = 18,
+    CUDNN_KNOB_TYPE_IDX_MODE                               = 18,
     CUDNN_KNOB_TYPE_SLICED CUDNN_DEPRECATED_ENUM           = 19,
     CUDNN_KNOB_TYPE_SPLIT_RS CUDNN_DEPRECATED_ENUM         = 20,
     CUDNN_KNOB_TYPE_SINGLEBUFFER CUDNN_DEPRECATED_ENUM     = 21,
@@ -847,6 +866,12 @@ typedef enum {
     CUDNN_KNOB_TYPE_TILE_ROWS                              = 34,
     CUDNN_KNOB_TYPE_TILE_COLS                              = 35,
     CUDNN_KNOB_TYPE_LOAD_SIZE                              = 36,
+    CUDNN_KNOB_TYPE_CTA_COUNT                              = 37,
+    CUDNN_KNOB_TYPE_STREAM_K                               = 38,
+    CUDNN_KNOB_TYPE_SPLIT_P_SLC                            = 39,
+    CUDNN_KNOB_TYPE_TILE_M                                 = 40,
+    CUDNN_KNOB_TYPE_TILE_N                                 = 41,
+    CUDNN_KNOB_TYPE_WARP_SPEC_CFG                          = 42,
     CUDNN_KNOB_TYPE_COUNTS,
 } cudnnBackendKnobType_t;
 
@@ -867,9 +892,10 @@ typedef enum {
 } cudnnBackendHeurMode_t;
 
 typedef enum {
-    CUDNN_TENSOR_REORDERING_NONE    = 0,
-    CUDNN_TENSOR_REORDERING_INT8x32 = 1,
-    CUDNN_TENSOR_REORDERING_F16x16  = 2,
+    CUDNN_TENSOR_REORDERING_NONE     = 0,
+    CUDNN_TENSOR_REORDERING_INT8x32  = 1,
+    CUDNN_TENSOR_REORDERING_F16x16   = 2,
+    CUDNN_TENSOR_REORDERING_F8_128x4 = 3,
 } cudnnBackendTensorReordering_t;
 
 typedef enum {
@@ -879,11 +905,12 @@ typedef enum {
 } cudnnPaddingMode_t;
 
 typedef enum {
-    CUDNN_LAYER_NORM    = 0,
-    CUDNN_INSTANCE_NORM = 1,
-    CUDNN_BATCH_NORM    = 2,
-    CUDNN_GROUP_NORM    = 3,
-    CUDNN_RMS_NORM      = 4,
+    CUDNN_LAYER_NORM     = 0,
+    CUDNN_INSTANCE_NORM  = 1,
+    CUDNN_BATCH_NORM     = 2,
+    CUDNN_GROUP_NORM     = 3,
+    CUDNN_RMS_NORM       = 4,
+    CUDNN_ADA_LAYER_NORM = 5,
 } cudnnBackendNormMode_t;
 
 typedef enum {

nvidia/cudnn/include/cudnn_ops.h

@@ -61,8 +61,8 @@
 
 /* These version numbers are autogenerated, do not edit manually. */
 #define CUDNN_OPS_MAJOR 9
-#define CUDNN_OPS_MINOR 5
-#define CUDNN_OPS_PATCH 1
+#define CUDNN_OPS_MINOR 7
+#define CUDNN_OPS_PATCH 0
 
 #if (CUDNN_OPS_MAJOR != CUDNN_MAJOR) || (CUDNN_OPS_MINOR != CUDNN_MINOR) || (CUDNN_OPS_PATCH != CUDNN_PATCHLEVEL)
 #error Version mismatch in cuDNN OPS INFER!!!

nvidia/cudnn/include/cudnn_version.h

@@ -55,15 +55,15 @@
 #define CUDNN_VERSION_H_
 
 #define CUDNN_MAJOR 9
-#define CUDNN_MINOR 5
-#define CUDNN_PATCHLEVEL 1
+#define CUDNN_MINOR 7
+#define CUDNN_PATCHLEVEL 0
 
 #define CUDNN_VERSION (CUDNN_MAJOR * 10000 + CUDNN_MINOR * 100 + CUDNN_PATCHLEVEL)
 
 /* cannot use constexpr here since this is a C-only file */
 /* Below is the max SM version this cuDNN library is aware of and supports natively */
 
-#define CUDNN_MAX_SM_MAJOR_NUMBER 9
+#define CUDNN_MAX_SM_MAJOR_NUMBER 12
 #define CUDNN_MAX_SM_MINOR_NUMBER 0
 #define CUDNN_MAX_DEVICE_VERSION (CUDNN_MAX_SM_MAJOR_NUMBER * 100 + CUDNN_MAX_SM_MINOR_NUMBER * 10)
 

{nvidia_cudnn_cu12-9.5.1.17.dist-info → nvidia_cudnn_cu12-9.7.0.66.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: nvidia-cudnn-cu12
-Version: 9.5.1.17
+Version: 9.7.0.66
 Summary: cuDNN runtime libraries
 Home-page: https://developer.nvidia.com/cuda-zone
 Author: Nvidia CUDA Installer Team

nvidia_cudnn_cu12-9.7.0.66.dist-info/RECORD

@@ -0,0 +1,24 @@
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+nvidia/cudnn/bin/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
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+nvidia_cudnn_cu12-9.7.0.66.dist-info/RECORD,,

{nvidia_cudnn_cu12-9.5.1.17.dist-info → nvidia_cudnn_cu12-9.7.0.66.dist-info}/WHEEL

@@ -1,5 +1,5 @@
 Wheel-Version: 1.0
-Generator: setuptools (75.2.0)
+Generator: setuptools (75.6.0)
 Root-Is-Purelib: true
 Tag: py3-none-win_amd64
 

nvidia_cudnn_cu12-9.5.1.17.dist-info/RECORD

@@ -1,24 +0,0 @@
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