nortl 1.4.0__py3-none-any.whl

nortl/utils/type_aliases.py

@@ -0,0 +1,15 @@
+"""Provides type aliases for common types."""
+
+from typing import TYPE_CHECKING, Optional
+
+from typing_extensions import TypeAlias
+
+__all__ = [
+    'IntSlice',
+]
+
+# slice became generic in 2024, but is somewhat broken (still includes Any?))
+if TYPE_CHECKING:
+    IntSlice: TypeAlias = slice[Optional[int], Optional[int], Optional[int]]
+else:
+    IntSlice = slice  # type: ignore[misc]

nortl/verilog_library/__init__.py

@@ -0,0 +1,74 @@
+from pathlib import Path
+from typing import List
+
+from nortl.core.module import Module
+
+VERILOG_LIBRARY_DIR = Path(__file__).parent
+
+BUILT_IN_LIB = {
+    'nortl_sync': (VERILOG_LIBRARY_DIR / 'nortl_sync.sv').resolve(),
+    'nortl_edge_detector': (VERILOG_LIBRARY_DIR / 'nortl_edge_detector.sv').resolve(),
+    'nortl_delay': (VERILOG_LIBRARY_DIR / 'nortl_delay.sv').resolve(),
+    'nortl_count_down_timer': (VERILOG_LIBRARY_DIR / 'nortl_count_down_timer.sv').resolve(),
+    'nortl_clock_gate': (VERILOG_LIBRARY_DIR / 'nortl_clock_gate.sv').resolve(),
+}
+
+
+def get_modules() -> List[Module]:
+    module_list = []
+
+    hdl_sync = ''
+    with open(BUILT_IN_LIB['nortl_sync'], 'r') as file:
+        hdl_sync = file.read()
+
+    sync = Module('nortl_sync', hdl_sync)
+    sync.add_port('IN')
+    sync.add_port('OUT')
+    sync.add_parameter('DATA_WIDTH', 1)
+    sync.add_port('CLK_REQ')
+    sync.set_clk_request('CLK_REQ')
+    module_list.append(sync)
+
+    hdl_edge_detect = ''
+    with open(BUILT_IN_LIB['nortl_edge_detector'], 'r') as file:
+        hdl_edge_detect = file.read()
+
+    edge_detect = Module('nortl_edge_detector', hdl_edge_detect)
+    edge_detect.add_port('SIGNAL')
+    edge_detect.add_port('RISING')
+    edge_detect.add_port('FALLING')
+    edge_detect.add_port('CLK_REQ')
+    edge_detect.set_clk_request('CLK_REQ')
+    module_list.append(edge_detect)
+
+    hdl_delay = ''
+    with open(BUILT_IN_LIB['nortl_delay'], 'r') as file:
+        hdl_delay = file.read()
+
+    delay = Module('nortl_delay', hdl_delay)
+    delay.add_port('IN')
+    delay.add_port('OUT')
+    delay.add_parameter('DATA_WIDTH', 1)
+    delay.add_parameter('DELAY_STEPS', 1)
+    delay.add_port('CLK_REQ')
+    delay.set_clk_request('CLK_REQ')
+    module_list.append(delay)
+
+    hdl_timer = ''
+    with open(BUILT_IN_LIB['nortl_count_down_timer'], 'r') as file:
+        hdl_timer = file.read()
+
+    timer = Module('nortl_count_down_timer', hdl_timer)
+    timer.add_port('RELOAD')
+    timer.add_port('ZERO')
+    timer.add_port('DELAY')
+    timer.add_parameter('DATA_WIDTH', 1)
+    module_list.append(timer)
+
+    cg = ''
+    with open(BUILT_IN_LIB['nortl_clock_gate'], 'r') as file:
+        cg = file.read()
+    # Ports are not defined here -- should not be used directly!
+    module_list.append(Module('nortl_clock_gate', cg))
+
+    return module_list

nortl/verilog_library/nortl_clock_gate.sv

@@ -0,0 +1,20 @@
+module nortl_clock_gate (
+    input logic CLK_I,
+    input logic EN,
+    output logic GCLK_O
+);
+
+logic enable_latch;
+
+always_latch begin
+    if (~CLK_I)
+    begin
+        enable_latch = EN;
+    end
+end
+
+always_comb begin
+    GCLK_O = enable_latch & CLK_I;
+end
+
+endmodule

nortl/verilog_library/nortl_count_down_timer.sv

@@ -0,0 +1,50 @@
+module nortl_count_down_timer #(
+    parameter DATA_WIDTH = 16
+) (
+    input  logic CLK_I,
+    input  logic RST_ASYNC_I,
+
+    input  logic RELOAD,
+    input  logic [DATA_WIDTH-1:0] DELAY,
+    output logic ZERO
+);
+
+logic [DATA_WIDTH-1:0] counter;
+logic RELOAD_DLY;
+
+always_ff @(posedge CLK_I or posedge RST_ASYNC_I)
+begin
+    if (RST_ASYNC_I)
+    begin
+        counter <= 0;
+        RELOAD_DLY <= 0;
+    end
+    else begin
+        RELOAD_DLY <= RELOAD;
+        if (RELOAD)
+        begin
+            if (DELAY > 2)
+            begin
+                counter <= DELAY - 2;
+            end
+        end
+        else if (counter != 0) begin
+            counter <= counter - 1;
+        end
+    end
+end
+
+always_comb begin
+    ZERO = (counter == 0) & ~RELOAD;
+
+    if (DELAY == 1)
+    begin
+        ZERO = ~RELOAD;
+    end
+    if (DELAY == 0)
+    begin
+        ZERO = ~RELOAD;
+    end
+end
+
+endmodule

nortl/verilog_library/nortl_delay.sv

@@ -0,0 +1,66 @@
+module nortl_delay #(
+    parameter DATA_WIDTH = 1,
+    parameter DELAY_STEPS = 2
+) (
+    input logic CLK_I,
+    input logic RST_ASYNC_I,
+
+    input  logic [DATA_WIDTH-1:0] IN,
+    output logic [DATA_WIDTH-1:0] OUT,
+
+    output logic CLK_REQ
+);
+
+logic [DATA_WIDTH-1:0] shiftreg [DELAY_STEPS-1:0];
+
+always_ff @(posedge CLK_I or posedge RST_ASYNC_I) begin
+    if (RST_ASYNC_I)
+    begin
+        for (int i=DELAY_STEPS-1; i>=0; i=i-1)
+        begin
+            shiftreg[i] <= {DATA_WIDTH{1'b0}};
+        end
+    end
+    else begin
+        if (DELAY_STEPS == 1)
+        begin
+            shiftreg[0] <= IN;
+        end
+        else begin
+            for (int i=DELAY_STEPS-2; i>=0; i=i-1)
+            begin
+                shiftreg[i+1] <= shiftreg[i];
+            end
+            shiftreg[0] <= IN;
+        end
+    end
+end
+
+always_comb begin
+    if (DELAY_STEPS == 1)
+    begin
+        OUT = shiftreg[0];
+    end
+    else begin
+        OUT = shiftreg[DELAY_STEPS-1];
+    end
+end
+
+always_comb begin
+    CLK_REQ = 0;
+
+    if (DELAY_STEPS == 1)
+    begin
+        CLK_REQ = CLK_REQ | (shiftreg[0] != IN);
+    end
+    else begin
+        for (int i=DELAY_STEPS-2; i>=0; i=i-1)
+        begin
+            CLK_REQ = CLK_REQ | (shiftreg[i+1] != shiftreg[i]);
+        end
+        CLK_REQ = CLK_REQ | (shiftreg[0] != IN);
+    end
+end
+
+
+endmodule

nortl/verilog_library/nortl_edge_detector.sv

@@ -0,0 +1,34 @@
+module nortl_edge_detector(
+    input  logic CLK_I,
+    input  logic RST_ASYNC_I,
+
+    input  logic SIGNAL,
+    output logic RISING,
+    output logic FALLING,
+
+    output logic CLK_REQ
+);
+
+logic [1:0] sr;
+
+always_ff @(posedge CLK_I or posedge RST_ASYNC_I)
+begin
+    if (RST_ASYNC_I)
+    begin
+        sr <= 2'b00;
+    end
+    else begin
+        sr <= {sr[0], SIGNAL};
+    end
+end
+
+always_comb begin
+    RISING = (sr == 2'b01);
+    FALLING = (sr == 2'b10);
+end
+
+always_comb begin
+    CLK_REQ = sr != {sr[0], SIGNAL};
+end
+
+endmodule

nortl/verilog_library/nortl_sync.sv

@@ -0,0 +1,28 @@
+module nortl_sync #(
+    parameter DATA_WIDTH = 1
+) (
+    input  logic CLK_I,
+    input  logic RST_ASYNC_I,
+
+    input  logic [DATA_WIDTH-1:0] IN,
+    output logic [DATA_WIDTH-1:0] OUT,
+
+    output logic CLK_REQ
+);
+
+always @(posedge CLK_I or posedge RST_ASYNC_I)
+begin
+    if (RST_ASYNC_I)
+    begin
+        OUT <= {DATA_WIDTH{1'b0}};
+    end
+    else begin
+        OUT <= IN;
+    end
+end
+
+always_comb begin
+    CLK_REQ = OUT != IN;
+end
+
+endmodule

nortl-1.4.0.dist-info/METADATA

@@ -0,0 +1,105 @@
+Metadata-Version: 2.4
+Name: nortl
+Version: 1.4.0
+Summary: Not-only RTL.
+Project-URL: Homepage, https://github.com/IMMS-Ilmenau/nortl
+Project-URL: Documentation, https://IMMS-Ilmenau.github.io/nortl
+Author-email: Florian Koegler <florian.koegler@imms.de>, Georg Glaeser <georg.glaeser@imms.de>
+License-File: LICENSE
+Requires-Python: >=3.12
+Requires-Dist: more-itertools>=10.8.0
+Requires-Dist: networkx>=3.4.2
+Provides-Extra: type-stubs
+Requires-Dist: pytest-stub; extra == 'type-stubs'
+Requires-Dist: types-networkx; extra == 'type-stubs'
+Description-Content-Type: text/markdown
+
+# noRTL - Hardware design beyond register transfer level
+
+**noRTL** (Not-only RTL) is a Python-based code generation framework for designing and implementing hardware description language (HDL) modules, particularly SystemVerilog state machines. It provides a high-level, Pythonic API for describing sets of finite state machines (FSMs) and hardware components with built-in correctness guarantees.
+
+**noRTL** aims to make the design of complex digital systems easier by reducing the shortcommings of current hardware description languages that use the register transfer level (RTL) to model digital circuit's behavior. This tool goes beyond this level of abstraction: We digital designers want to describe behavior with cycle-level accuracy but do not want do deal with the complexity of state naming, state coding, starting parallel processes, etc. **noRTL** realizes this tedious part of digital design inside its core.
+
+The code that is written for **noRTL** is pure Python code. The **noRTL** package realizes state handling and data structure assembly for you while the Python code is executed. **noRTL** can be understood as a fancy generator that assembles state machines and provides the tooling to render it to SystemVerilog and tools for verifying your code.
+
+## Main ideas
+
+**noRTL** is built with the following concepts and ideas.
+
+* Each hardware description is an executable Python program. The hardware structure is assembled during execution. There is no need for static code analysis or parsing.
+* There should be no need to declare states explicitely. The number of states is determined during execution of the code.
+* The behavior description should be easily readable and feel procedural. Control structures should work similar to Python equivalents.
+* Checks and Optimizations are to be done during runtime of the Python code. Post-Optimization has not been necessary (yet).
+
+## Installation
+
+A prerequisite for noRTL is the availablility of icarus Verilog in your path. This can be installed using your system's package manager or using the *oss-cad-suite* (https://github.com/YosysHQ/oss-cad-suite-build)
+
+### Method 1: Using pip (Public Registry)
+
+```bash
+# Install nortl
+pip install nortl
+```
+
+### Method 2: Using uv (Recommended)
+
+```bash
+# Clone the repository
+git clone https://github.com/IMMS-Ilmenau/nortl
+cd nortl
+
+# Install dependencies
+uv sync
+
+# Activate the virtual environment
+source .venv/bin/activate  # On Windows: .venv\Scripts\activate
+```
+
+### Method 3: Development Installation
+
+For development work, install in editable mode:
+
+```bash
+# Clone the repository
+git clone https://github.com/IMMS-Ilmenau/nortl
+cd nortl
+
+# Install development dependencies
+uv sync --all-extras
+
+# Activate the virtual environment
+source .venv/bin/activate
+```
+
+---
+
+## Your First State Machine
+
+Let's create a simple state machine that toggles an output based on an input.
+
+```python
+from nortl import Engine, Const
+
+# Create an engine with a module name -- Clock and reset signal is automatically included
+engine = Engine("my_first_engine")
+
+# Define input and output signals
+enable = engine.define_input("enable", width=1)
+output = engine.define_output("output", width=1, reset_value=0)
+
+# Don't define states -- define behavior!
+with engine.while_loop(Const(1)):
+    engine.wait_for(enable == 1)
+    engine.set(output, 1)
+    engine.sync() # Wait one clock cycle
+    engine.set(output, 0)
+    engine.wait_for(enable == 0)
+
+# Generate SystemVerilog code
+from nortl.renderer import VerilogRenderer
+renderer = VerilogRenderer()
+verilog_code = renderer.render(engine)
+
+print(verilog_code)
+```

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nortl-1.4.0.dist-info/WHEEL

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+Wheel-Version: 1.0
+Generator: hatchling 1.28.0
+Root-Is-Purelib: true
+Tag: py3-none-any

nortl-1.4.0.dist-info/licenses/LICENSE

@@ -0,0 +1,11 @@
+Copyright 2026 Institut für Mikroelektronik- und Mechatronik-Systeme gemeinnützige GmbH (IMMS GmbH)
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
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