netgen-mesher 6.2.2504.post11.dev0__cp313-cp313-win_amd64.whl → 6.2.2506.post48.dev0__cp313-cp313-win_amd64.whl

netgen/include/core/simd_arm64.hpp

@@ -30,6 +30,152 @@ namespace ngcore
     auto Hi() const { return mask[1]; }
   };
 
+
+  // *************************** int32 ***************************
+
+
+  
+  template<>
+  class SIMD<int32_t,2>
+  {
+    int32x2_t data;
+  public:
+    static constexpr int Size() { return 2; }
+    SIMD() {}
+    SIMD (int32_t val) : data{val,val} {}
+    SIMD (int32_t v0, int32_t v1) : data{v0,v1} { }
+    SIMD (SIMD<int32_t,1> lo, SIMD<int32_t,1> hi) : data{lo[0], hi[0] } { }     
+    SIMD (std::array<int32_t, 2> arr) : data{arr[0], arr[1]} { } 
+    
+    SIMD (int32x2_t _data) { data = _data; }
+
+    NETGEN_INLINE auto Data() const { return data; }
+    NETGEN_INLINE auto & Data() { return data; }
+
+    SIMD<int32_t,1> Lo() const { return Get<0>(); }
+    SIMD<int32_t,1> Hi() const { return Get<1>(); } 
+    
+    int32_t operator[] (int i) const { return data[i]; }
+    int32_t & operator[] (int i)  { return ((int32_t*)&data)[i]; }
+
+    template <int I>
+    int32_t Get() const { return data[I]; }
+    static SIMD FirstInt(int n0=0) { return { n0+0, n0+1 }; }
+  };
+
+
+  template<>
+  class SIMD<int32_t,4>
+  {
+    int32x4_t data;
+  public:
+    static constexpr int Size() { return 4; }
+    SIMD() {}
+    SIMD (int32_t val) : data{val,val,val,val} {}
+    SIMD (int32_t v0, int32_t v1, int32_t v2, int32_t v3) : data{v0,v1,v2,v3} { }
+    SIMD (std::array<int32_t, 4> arr) : data{arr[0], arr[1], arr[2], arr[3]} { } 
+    
+    SIMD (int32x4_t _data) { data = _data; }
+    SIMD (SIMD<int32_t,2> lo, SIMD<int32_t,2> hi) : data{vcombine_s32(lo.Data(), hi.Data())} {}
+    SIMD (int32_t * p) : data{vld1q_s32(p)} { }
+
+    NETGEN_INLINE auto Data() const { return data; }
+    NETGEN_INLINE auto & Data() { return data; }
+
+    SIMD<int32_t,2> Lo() const { return vget_low_s32(data); }
+    SIMD<int32_t,2> Hi() const { return vget_high_s32(data); }
+    
+    int32_t operator[] (int i) const { return data[i]; }
+    int32_t & operator[] (int i)  { return ((int32_t*)&data)[i]; }
+
+    void Store (int32_t * p) { vst1q_s32(p, data); }
+          
+    template <int I>
+    int32_t Get() const { return data[I]; }
+    static SIMD FirstInt(int n0=0) { return { n0+0, n0+1, n0+2, n0+3 }; }
+  };
+  
+
+  
+  NETGEN_INLINE auto Min (SIMD<int32_t,2> a, SIMD<int32_t,2> b) {
+    return SIMD<int32_t,2>(vmin_s32(a.Data(), b.Data()));
+  }
+  
+  NETGEN_INLINE auto Max (SIMD<int32_t,2> a, SIMD<int32_t,2> b) {
+    return SIMD<int32_t,2>(vmax_s32(a.Data(), b.Data()));
+  }
+
+  
+  NETGEN_INLINE auto Min (SIMD<int32_t,4> a, SIMD<int32_t,4> b) {
+    return SIMD<int32_t,4>(vminq_s32(a.Data(), b.Data()));
+  }
+  
+  NETGEN_INLINE auto Max (SIMD<int32_t,4> a, SIMD<int32_t,4> b) {
+    return SIMD<int32_t,4>(vmaxq_s32(a.Data(), b.Data()));
+  }
+
+
+  
+
+  // *************************** int64 ***************************  
+ 
+  template<>
+  class SIMD<int64_t,2>
+  {
+    int64x2_t data;
+  public:
+    static constexpr int Size() { return 2; }
+    SIMD() {}
+    SIMD (int64_t val) : data{val,val} {}
+    SIMD (int64_t v0, int64_t v1) : data{vcombine_s64(int64x1_t{v0}, int64x1_t{v1})} { }
+    SIMD (std::array<int64_t, 2> arr) : data{arr[0], arr[1]} { } 
+    
+    SIMD (int64x2_t _data) { data = _data; }
+
+    NETGEN_INLINE auto Data() const { return data; }
+    NETGEN_INLINE auto & Data() { return data; }
+
+    int64_t Lo() const { return Get<0>(); } 
+    int64_t Hi() const { return Get<1>(); } 
+    
+    int64_t operator[] (int i) const { return data[i]; }
+    int64_t & operator[] (int i)  { return ((int64_t*)&data)[i]; }
+
+    template <int I>
+    int64_t Get() const { return data[I]; }
+    static SIMD FirstInt(int n0=0) { return { n0+0, n0+1 }; }
+  };
+
+  NETGEN_INLINE SIMD<int64_t,2> operator& (SIMD<int64_t,2> a, SIMD<int64_t,2> b)
+  {
+    return vandq_s64(a.Data(), b.Data());
+  }
+
+  NETGEN_INLINE SIMD<int64_t,2> operator+ (SIMD<int64_t,2> a, SIMD<int64_t,2> b)
+  {
+    return vaddq_s64(a.Data(), b.Data());
+  }
+
+  NETGEN_INLINE SIMD<mask64,2> operator== (SIMD<int64_t> a, SIMD<int64_t> b)
+  {
+    return vceqq_u64(a.Data(), b.Data());
+  }
+  
+  NETGEN_INLINE SIMD<mask64,2> operator> (SIMD<int64_t> a, SIMD<int64_t> b)
+  {
+    return vcgtq_s64(a.Data(), b.Data());
+  }
+
+  
+  template <int N>
+  SIMD<int64_t,2> operator<< (SIMD<int64_t,2> a, IC<N> n)
+  {
+    return vshlq_n_s64(a.Data(), N);
+  }
+  
+  
+  
+  // *************************** double ***************************
   
   template<>
   class SIMD<double,2>
@@ -162,6 +308,16 @@ namespace ngcore
     auto tmp = vcmlaq_f64(c.Data(), a.Data(), b.Data());   // are * b
     c = vcmlaq_rot90_f64(tmp, a.Data(), b.Data());    // += i*aim * b
   }
+
+  NETGEN_INLINE void FMAComplex (SIMD<double,4> a, SIMD<double,4> b, SIMD<double,4> & c)
+  {
+    SIMD<double,2> clo = c.Lo();
+    SIMD<double,2> chi = c.Hi();
+    FMAComplex (a.Lo(), b.Lo(), clo);
+    FMAComplex (a.Hi(), b.Hi(), chi);
+    c = SIMD<double,4> (clo, chi);
+  }
+
   
 
   NETGEN_INLINE SIMD<double,2> operator+ (SIMD<double,2> a, SIMD<double,2> b)
@@ -178,6 +334,52 @@ namespace ngcore
   NETGEN_INLINE SIMD<double,2> operator/ (SIMD<double,2> a, SIMD<double,2> b)
   { return a.Data()/b.Data(); }
 
+  NETGEN_INLINE SIMD<double,2> sqrt (SIMD<double,2> x)
+  { return vsqrtq_f64(x.Data()); }
+
+  
+  NETGEN_INLINE SIMD<double,2> round (SIMD<double,2> x)
+  {
+    return vrndnq_f64(x.Data());
+  }
+  
+  NETGEN_INLINE SIMD<int64_t,2> lround (SIMD<double,2> x)
+  {
+    return vcvtq_s64_f64(x.Data());
+  }
+
+
+
+  NETGEN_INLINE SIMD<double,2> rsqrt (SIMD<double,2> x)
+  {
+    return 1.0 / sqrt(x);
+  
+    // SIMD<double,2> y = vrsqrteq_f64(x.Data());
+
+    /*
+    y = y * vrsqrtsq_f64( (x*y).Data(), y.Data());
+    y = y * vrsqrtsq_f64( (x*y).Data(), y.Data());
+    y = y * vrsqrtsq_f64( (x*y).Data(), y.Data());
+    */
+
+    /*
+    auto x_half = 0.5*x;
+    y = y * (1.5 - (x_half * y * y));
+    y = y * (1.5 - (x_half * y * y));
+    y = y * (1.5 - (x_half * y * y));
+    
+    return y;
+    */
+  }
+  
+  
+  
+
+  template <>
+  NETGEN_INLINE SIMD<double,2> Reinterpret (SIMD<int64_t,2> a)
+  {
+    return vreinterpretq_f64_s64(a.Data());
+  }
 
   
   NETGEN_INLINE SIMD<double,2> If (SIMD<mask64,2> a, SIMD<double,2> b, SIMD<double,2> c)
@@ -188,7 +390,9 @@ namespace ngcore
   }
   NETGEN_INLINE SIMD<int64_t,2> If (SIMD<mask64,2> a, SIMD<int64_t,2> b, SIMD<int64_t,2> c)
   {
-    return SIMD<int64_t,2> (a[0] ? b[0] : c[0], a[1] ? b[1] : c[1]);
+    // return SIMD<int64_t,2> (a[0] ? b[0] : c[0], a[1] ? b[1] : c[1]);
+    uint64x2_t mask = vreinterpretq_u64_s64(a.Data());
+    return vbslq_s64(mask, b.Data(), c.Data());
   }
 
   NETGEN_INLINE SIMD<mask64,2> operator&& (SIMD<mask64,2> a, SIMD<mask64,2> b)

netgen/include/core/simd_avx.hpp

@@ -21,11 +21,31 @@ namespace ngcore
 #endif // defined(__GNUC__) && (__GNUC__ == 7)
 
 #if defined(__AVX2__)
+  NETGEN_INLINE __m256i my_mm256_cmpeq_epi64 (__m256i a, __m256i b)
+  {
+    return _mm256_cmpeq_epi64 (a,b);
+  }
+
   NETGEN_INLINE __m256i my_mm256_cmpgt_epi64 (__m256i a, __m256i b)
   {
     return _mm256_cmpgt_epi64 (a,b);
   }
+
+  NETGEN_INLINE __m256i my_mm256_cvtepi32_epi64 (__m128i a)
+  {
+    return _mm256_cvtepi32_epi64 (a);
+  }
+  
 #else
+  NETGEN_INLINE __m256i my_mm256_cmpeq_epi64 (__m256i a, __m256i b)
+  {
+    __m128i rlo = _mm_cmpeq_epi64(_mm256_extractf128_si256(a, 0),
+                                  _mm256_extractf128_si256(b, 0));
+    __m128i rhi = _mm_cmpeq_epi64(_mm256_extractf128_si256(a, 1),
+                                  _mm256_extractf128_si256(b, 1));
+    return _mm256_insertf128_si256 (_mm256_castsi128_si256(rlo), rhi, 1);
+  }
+
   NETGEN_INLINE __m256i my_mm256_cmpgt_epi64 (__m256i a, __m256i b)
   {
     __m128i rlo = _mm_cmpgt_epi64(_mm256_extractf128_si256(a, 0),
@@ -34,6 +54,13 @@ namespace ngcore
                                   _mm256_extractf128_si256(b, 1));
     return _mm256_insertf128_si256 (_mm256_castsi128_si256(rlo), rhi, 1);
   }
+
+  NETGEN_INLINE __m256i my_mm256_cvtepi32_epi64 (__m128i a)
+  {
+    __m128i rlo = _mm_cvtepi32_epi64(a);   // First two 32-bit integers
+    __m128i rhi = _mm_cvtepi32_epi64(_mm_shuffle_epi32(a, _MM_SHUFFLE(3, 2, 3, 2))); // Next two 32-bit integers
+    return _mm256_insertf128_si256 (_mm256_castsi128_si256(rlo), rhi, 1);
+  }
 #endif
 
 
@@ -86,7 +113,7 @@ namespace ngcore
       : data{_mm256_set_epi64x(a[3],a[2],a[1],a[0])}
     {}
     SIMD (SIMD<int64_t,2> v0, SIMD<int64_t,2> v1)
-        : data(_mm256_set_m128i(v0.Data(),v1.Data()))
+        : data(_mm256_set_m128i(v1.Data(),v0.Data()))
       {}
     SIMD (__m256i _data) { data = _data; }
 
@@ -97,6 +124,13 @@ namespace ngcore
     SIMD<int64_t,2> Lo() const { return _mm256_extractf128_si256(data, 0); }
     SIMD<int64_t,2> Hi() const { return _mm256_extractf128_si256(data, 1); }
     static SIMD FirstInt(int n0=0) { return { n0+0, n0+1, n0+2, n0+3 }; }
+
+    template <int I>
+    double Get() const
+    {
+      static_assert(I>=0 && I<4, "Index out of range");
+      return (*this)[I];
+    }
   };
 
 
@@ -105,6 +139,11 @@ namespace ngcore
 #ifdef __AVX2__
   NETGEN_INLINE SIMD<int64_t,4> operator+ (SIMD<int64_t,4> a, SIMD<int64_t,4> b) { return _mm256_add_epi64(a.Data(),b.Data()); }
   NETGEN_INLINE SIMD<int64_t,4> operator- (SIMD<int64_t,4> a, SIMD<int64_t,4> b) { return _mm256_sub_epi64(a.Data(),b.Data()); }
+  NETGEN_INLINE SIMD<int64_t,4> operator& (SIMD<int64_t,4> a, SIMD<int64_t,4> b)
+  { return _mm256_castpd_si256(_mm256_and_pd (_mm256_castsi256_pd(a.Data()),_mm256_castsi256_pd( b.Data()))); }
+
+  template <int N>
+  SIMD<int64_t,4> operator<< (SIMD<int64_t,4> a, IC<N> n) { return _mm256_sll_epi64(a.Data(),_mm_set_epi32(0,0,0,N)); }
 #endif // __AVX2__
 
   template<>
@@ -178,7 +217,11 @@ namespace ngcore
   NETGEN_INLINE SIMD<double,4> floor (SIMD<double,4> a) { return _mm256_floor_pd(a.Data()); }
   NETGEN_INLINE SIMD<double,4> ceil (SIMD<double,4> a) { return _mm256_ceil_pd(a.Data()); }
   NETGEN_INLINE SIMD<double,4> fabs (SIMD<double,4> a) { return _mm256_max_pd(a.Data(), (-a).Data()); }
-
+  NETGEN_INLINE SIMD<double,4> round(SIMD<double,4> a) { return _mm256_round_pd(a.Data(), _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); }
+  NETGEN_INLINE SIMD<int64_t,4> lround (SIMD<double,4> a)
+  {
+    return my_mm256_cvtepi32_epi64(_mm256_cvtpd_epi32(_mm256_round_pd(a.Data(), _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC)));
+  }
 
 #ifdef __FMA__
   NETGEN_INLINE SIMD<double,4> FMA (SIMD<double,4> a, SIMD<double,4> b, SIMD<double,4> c)
@@ -255,9 +298,9 @@ namespace ngcore
   NETGEN_INLINE SIMD<mask64,4> operator> (SIMD<int64_t,4> a , SIMD<int64_t,4> b)
   { return  my_mm256_cmpgt_epi64(a.Data(),b.Data()); }
   NETGEN_INLINE SIMD<mask64,4> operator== (SIMD<int64_t,4> a , SIMD<int64_t,4> b)
-  { return  _mm256_cmpeq_epi64(a.Data(),b.Data()); }
+  { return  my_mm256_cmpeq_epi64(a.Data(),b.Data()); }
   NETGEN_INLINE SIMD<mask64,4> operator!= (SIMD<int64_t,4> a , SIMD<int64_t,4> b)
-  { return  _mm256_xor_si256(_mm256_cmpeq_epi64(a.Data(),b.Data()),_mm256_set1_epi32(-1)); }
+  { return  _mm256_xor_si256(my_mm256_cmpeq_epi64(a.Data(),b.Data()),_mm256_set1_epi32(-1)); }
 
 #ifdef __AVX2__
   NETGEN_INLINE SIMD<mask64,4> operator&& (SIMD<mask64,4> a, SIMD<mask64,4> b)
@@ -274,6 +317,15 @@ namespace ngcore
   NETGEN_INLINE SIMD<mask64,4> operator! (SIMD<mask64,4> a)
   { return _mm256_castpd_si256(_mm256_xor_pd (_mm256_castsi256_pd(a.Data()),_mm256_castsi256_pd( _mm256_cmpeq_epi64(a.Data(),a.Data())))); }
 #endif
+
+  template <>
+  NETGEN_INLINE SIMD<double,4> Reinterpret (SIMD<int64_t,4> a)
+  {
+    return _mm256_castsi256_pd (a.Data());
+  }
+
+
+  
   NETGEN_INLINE SIMD<double,4> If (SIMD<mask64,4> a, SIMD<double,4> b, SIMD<double,4> c)
   { return _mm256_blendv_pd(c.Data(), b.Data(), _mm256_castsi256_pd(a.Data())); }
 
@@ -314,6 +366,22 @@ namespace ngcore
   }
 
 
+  /*
+    // untested ...
+    NETGEN_INLINE SIMD<double,4> rsqrt (SIMD<double,4> x)
+  {
+    // return 1.0 / sqrt(x);
+    // SIMD<double,4> y = _mm256_rsqrt14_pd(x.Data());  // only avx512
+    SIMD<double,4> y = _mm256_cvtps_pd ( _mm_rsqrt_ps ( _mm256_cvtpd_ps (x.Data())));
+    auto x_half = 0.5*x;
+    y = y * (1.5 - (x_half * y * y));
+    y = y * (1.5 - (x_half * y * y));
+    return y;
+  }
+  */
+  
+    
+
   NETGEN_INLINE SIMD<int64_t,4> If (SIMD<mask64,4> a, SIMD<int64_t,4> b, SIMD<int64_t,4> c)
   { return _mm256_castpd_si256(_mm256_blendv_pd(_mm256_castsi256_pd(c.Data()), _mm256_castsi256_pd(b.Data()),
                                                 _mm256_castsi256_pd(a.Data()))); }

netgen/include/core/simd_avx512.hpp

@@ -59,6 +59,15 @@ namespace ngcore
       data = _mm512_set_epi64(func(7), func(6), func(5), func(4), func(3), func(2), func(1), func(0));
     }
 
+    SIMD (SIMD<int64_t,4> v0, SIMD<int64_t,4> v1)
+        : data(_mm512_castsi256_si512(v0.Data()))
+      {
+        data = _mm512_inserti64x4(data, v1.Data(), 1);
+      }
+
+    SIMD<int64_t,4> Lo() const { return _mm512_castsi512_si256(data); }
+    SIMD<int64_t,4> Hi() const { return _mm512_extracti64x4_epi64(data, 1); }
+
 
     NETGEN_INLINE auto operator[] (int i) const { return ((int64_t*)(&data))[i]; }
     NETGEN_INLINE auto & operator[] (int i) { return ((int64_t*)(&data))[i]; }