nbxtensor 0.0.1__py3-none-any.whl

nbxtensor/backend/devices/amd/cdna.yml

@@ -0,0 +1,228 @@
+# The library's half of amd/cdna.yml: the keys nbxtensor reads (docs/nbxtensor/device_keys.txt),
+# moved with their sources by tools/split_vendor_files.py. NeuroBrix's half stays in
+# src/neurobrix/config/vendors/amd/cdna.yml; the engine reads the two merged.
+
+architecture: cdna
+compute_capability: "gfx908"  # MI100
+
+block_sizes:
+  # Default block size for simple kernels
+  default: 1024
+
+  # Batched Matrix Multiply configuration
+  bmm:
+    block_m: 64
+    block_n: 64
+    block_k: 16
+    num_warps: 4
+
+  # Convolution configuration
+  conv2d:
+    block_h: 16
+    block_w: 16
+    num_warps: 4
+
+  # Generic reduction block size
+  reduction: 1024
+  # M=1 dequant-GEMV occupancy rule — see nvidia/volta.yml for the
+  # full rationale (pinned parity BLOCK_N under-fills small-N grids;
+  # the wrapper halves BLOCK_N until the grid reaches min_programs).
+  # 240 = 2 waves x 120 CUs (MI100); validation_status: analytical.
+  # Key absent or 0 -> no adaptation.
+  dequant_gemv:
+    min_programs: 240
+
+# Scaled Dot-Product Attention block size thresholds.
+# Schema documented in volta.yml. Decode entries first.
+# CDNA1/2 values conservative for the 64 KB SMEM budget. CDNA3
+# (MI300) has 160 KB and could use larger tiles — when needed,
+# split into cdna3.yml or extend with conditional blocks.
+sdpa_thresholds:
+  # Decode path (seqlen_q ≤ 16)
+  - seqlen_q_le: 16
+    head_dim_ge: 256
+    block_m: 16
+    block_n: 16
+    num_warps: 4
+  - seqlen_q_le: 16
+    block_m: 16
+    block_n: 32
+    num_warps: 4
+  # Prefill path (seqlen_q > 16)
+  - head_dim_ge: 256
+    block_m: 16
+    block_n: 16
+    num_warps: 4
+  - head_dim_ge: 128
+    block_m: 32
+    block_n: 32
+    num_warps: 4
+  - head_dim_lt: 128
+    block_m: 64
+    block_n: 64
+    num_warps: 4
+
+memory:
+  max_shared_memory_per_block: 65536    # 64 KB (CDNA1/2)
+  max_registers_per_block: 65536
+  # AMD schedules in 64-wide WAVEFRONTS where NVIDIA uses 32-wide warps.
+  # Named `warp_size` for schema uniformity, the same convention
+  # apple_silicon.yml follows for its SIMD groups: one hardware concept has
+  # ONE key across every profile, so a consumer never branches on vendor to
+  # find it. Declaring it as `wavefront_size` meant a reader asking for
+  # `memory.warp_size` got nothing on AMD and would fall back to 32 — wrong
+  # by 2x, silently, on every CDNA card.
+  warp_size: 64
+  # The registers ONE lane may address for ordinary (non-matrix) code: the 256 architectural VGPRs V0-V255; the
+  # 256 AccVGPRs beside them in the same file serve the matrix (MFMA) instructions and spills, not a tile's elements
+  # (AMD Instinct MI300 / CDNA3 ISA reference guide, "VGPRs": up to 512 per wave, 256 of each type; CDNA2 the same,
+  # ORNL CDNA2 memory-hierarchy slides). Read by ops/_configs.fits_thread_registers (elements a thread holds).
+  max_registers_per_thread: 256
+  # SDPA deterministic-routing budget (R10 schema parity with
+  # volta.yml). 0 = NOT APPLICABLE: the flash-attention
+  # non-determinism diagnosed in P-TRITON-MOE-DETERMINISM-RESIDUAL
+  # is an NVIDIA Volta-SIMT MMA issue. ROCm/HIP uses a different
+  # Triton backend and matrix-core path; the Volta race does not
+  # transfer. Left 0 (no routing) until/unless empirically shown
+  # otherwise on CDNA hardware. hand_curated_from_docs.
+  sdpa_math_max_scores_bytes: 0
+  # Row block (alignment and floor) of the chunked deterministic
+  # math prefill; the chunk-halving retry on a refused allocation
+  # never goes below it.
+  sdpa_math_min_chunk_rows: 128
+  # Allocator pool: bytes the free-list may keep PARKED per device as a
+  # fraction of that device's memory (2026-09-02, pool default-on gate).
+  # Beyond it the largest parked blocks go back to the driver, bounding
+  # the pool's contribution to the driver watermark (measured +3.4 GB on
+  # the xlong int4 row unbounded). 0 = unbounded.
+  alloc_pool_parked_cap_fraction: 0.50
+precision:
+  # Attention operands that disagree in dtype (an fp16 GEMM stored fp32 feeding V) all take the
+  # narrowest of the three, the compiled engine's alignment: the half attention stays on the matrix
+  # unit (V100, 2026-10-08: 1.16 s/op aligned narrowest vs 22.0 s/op on the scalar flash aligned widest).
+  attention_operands: narrowest
+  # Whether each engine branch's OWN kernels compute float64 / complex128 elements, read with
+  # supports_fp64 (both must hold) -- a CAPABILITY: `compiled` is ATen's, which carries both wherever
+  # the device does; `triton` is the NeuroBrix Triton kernels' (cuda/hip lower double; Metal's
+  # lowering narrows it in silence, measured 2026-09-28 on the Sana 4K positional embedding). Read
+  # by the DtypeEngine (`config.device_supports_fp64`) and by the Triton wrappers' binding
+  # (`triton.dtype.triton_has_fp64` -> `nbx_tensor.set_backend_has_fp64`).
+  kernels_carry_fp64:
+    compiled: true
+    triton: true
+# Software-pipelining budget — see nvidia/volta.yml for the schema.
+#
+# validation_status: conservative_pending_first_light. cp.async is a
+# PTX instruction and does not exist on CDNA; Triton's AMD backend
+# pipelines through LDS by a different mechanism, so Volta's measured
+# fault does not transfer and neither does Ampere's clearance. Until an
+# MI-series card measures it, the cap is 2: clamping can only cost
+# throughput, while allowing unvalidated pipelining could cost
+# correctness. Raising this is a first-light task
+# (docs/internal/amd_first_light.md), not a guess to make from here.
+pipelining:
+  max_num_stages: 2
+
+# Autotune correctness screen. The engine runs every candidate config once and
+# compares its result against a reference config's before timing any of them,
+# because an autotuner that ranks on speed alone selects whichever WRONG
+# kernel is fastest — a kernel that writes half its output does half the
+# stores and wins. Measured on Apple 2026-09-07: fp16 mm [64,32]@[32,64] chose
+# a config that left half the columns zero.
+#
+# These are the tolerances that separate "a different but valid summation
+# order" from "a different answer". Two configs with different block sizes
+# reduce in a different order, so their results differ in the last bits; a
+# config that drops output differs by the scale of the output itself. The
+# gap between those two is several orders of magnitude, and these sit in it.
+#
+# Relative to the reference's own magnitude: max|a - b| / max|b|. Integer
+# and boolean results are compared BIT-IDENTICALLY and ignore this table —
+# there is no valid reordering that changes an integer.
+autotune_screen_rtol:
+  float16: 2.0e-2
+  bfloat16: 4.0e-2
+  float32: 1.0e-4
+  float64: 1.0e-8
+  int64: 0.0               # an integer result (the MoE alignment's routing tables) is met exactly
+
+# Above this many bytes of buffer, the autotune correctness screen does not
+# run. Screening copies every argument out and back once per candidate, so a
+# very large tensor turns a tuning step into hundreds of megabytes of traffic
+# — and on unified memory that pressure is the machine's, not a card's.
+# MEASURED 2026-09-07: unbounded screening of a 151936-wide softmax perturbed
+# six unrelated tests in the same process. A skipped screen is announced, not
+# silent.
+autotune_screen_max_bytes: 33554432
+
+autotune:
+  buckets:
+    # elements — an element-wise launch's element count (`kernels/ops/elementwise_launch.py`), NEVER the `default`
+    # dimension ladder (`autotune_bucket.ladder_for` refuses it). NOT measured on this architecture (no such device on
+    # either machine): the four classes measured on V100-SXM2 2026-10-23 (nvidia/volta.yml, launch-bound under 65 536
+    # elements, bandwidth classes above) and confirmed on apple_m4_pro 2026-10-24 — the measurement on this
+    # architecture is owed (docs/reference/owed-proofs.md, "element-wise ladder per architecture").
+    elements:
+      - {up_to: 65536, step: 65536}
+      - {up_to: 1048576, step: 1048576}
+      - {up_to: 16777216, step: 16777216}
+      - {up_to: null, step: 68719476736}
+    default:
+      - {up_to: 64, step: 1}
+      - {up_to: 256, step: 16}
+      - {up_to: 1024, step: 32}
+      - {up_to: 8192, step: 128}
+      # Above 8 192 a QUARTER-OCTAVE, not a 512-step. The 512 tail was decided by a sweep
+      # that ran to about 4 096 and never met a request-scale dimension: a vocoder's batched
+      # GEMM keys on the WAVEFORM and reaches 1 963 520, which a 512-step cuts into some four
+      # thousand buckets — 1 400 of one model's 1 522 distinct M values sat above 8 192.
+      # Measured 2026-09-22 on both classes, two shapes (the vocoder's B=1,N=1,K=9 and a
+      # GEMM at N=K=512), each octave bucket carrying three or four measured values with its
+      # TOP as representative: 0.0 % median loss, 0.2 % max at ONE octave bucket. The rows
+      # below are finer than the octave that was measured, so they cost no more than it did.
+      # The first three octaves above the knee keep a NARROW step. Measured directly on the
+      # rows as shipped (the upscalers' N=360, K=180; three sizes inside each bucket with
+      # its TOP among them, 2026-09-22): a quarter-octave there cost 0.0 % median but
+      # **5.2 %** at the 10 240 bucket and 1.2 % at 16 384 — the loss lives just above the
+      # knee, where a quarter of an OCTAVE is still a quarter of the VALUE. Beyond 65 536
+      # the same sweep measured 0.0 % median and at most 0.6 %, so the quarter-octave stands.
+      # The convolution-width ladder below keeps its quarter-octave: its own sweep measured
+      # 0.0 % median AND max there, on both classes and two channel counts.
+      - {up_to: 16384, step: 512}
+      - {up_to: 32768, step: 1024}
+      - {up_to: 65536, step: 2048}
+      - {up_to: 131072, step: 16384}
+      - {up_to: 262144, step: 32768}
+      - {up_to: 524288, step: 65536}
+      - {up_to: 1048576, step: 131072}
+      - {up_to: 2097152, step: 262144}
+      - {up_to: null, step: 524288}
+    # The width of a ONE-ROW convolution (a 1-D convolution over a sequence: a vocoder's
+    # samples, a mel spectrogram's frames) is the request's length, unbounded by any
+    # resolution — chatterbox's vocoder reaches 444 721 samples for 18 s of speech. Above the
+    # GEMM ladder it steps by a quarter-octave (≤ 25 % of the value), so a census meets every
+    # class of a speech length in ~100 runs instead of ~1 000; the loss of that step is owed a
+    # measurement on both classes (bucket_loss.py) before the ladder is called final.
+    W:
+      - {up_to: 64, step: 1}
+      - {up_to: 256, step: 16}
+      - {up_to: 1024, step: 32}
+      - {up_to: 8192, step: 128}
+      - {up_to: 16384, step: 2048}
+      - {up_to: 32768, step: 4096}
+      - {up_to: 65536, step: 8192}
+      - {up_to: 131072, step: 16384}
+      - {up_to: 262144, step: 32768}
+      - {up_to: 524288, step: 65536}
+      - {up_to: null, step: 131072}
+
+# The flash kernel at a power-of-two head dim >= 128 is NOT measured on this architecture: the zero-pad
+# detour stays (launch_keys.flash_headdim_detour). Declared, never left absent: true only where the
+# correctness oracle was run with the detour off on this arch and stack (Volta, Triton 3.8, 2026-10-03).
+flash:
+  pow2_head_dim_correct: false
+
+# Convolution weight storage order (launch_keys.conv_weight_layout): KCRS, the container's own,
+# until this arch measures KRSC (the M4 Pro measured +46-63 % on its 3x3 keys, 2026-10-07).
+conv:
+  weight_layout: KCRS

nbxtensor/backend/devices/amd/cdna2.yml

@@ -0,0 +1,228 @@
+# The library's half of amd/cdna2.yml: the keys nbxtensor reads (docs/nbxtensor/device_keys.txt),
+# moved with their sources by tools/split_vendor_files.py. NeuroBrix's half stays in
+# src/neurobrix/config/vendors/amd/cdna2.yml; the engine reads the two merged.
+
+architecture: cdna2
+compute_capability: "gfx90a"  # MI210 / MI250 / MI250X
+
+block_sizes:
+  # Default block size for simple kernels
+  default: 1024
+
+  # Batched Matrix Multiply configuration
+  bmm:
+    block_m: 64
+    block_n: 64
+    block_k: 16
+    num_warps: 4
+
+  # Convolution configuration
+  conv2d:
+    block_h: 16
+    block_w: 16
+    num_warps: 4
+
+  # Generic reduction block size
+  reduction: 1024
+  # M=1 dequant-GEMV occupancy rule — see nvidia/volta.yml for the
+  # full rationale (pinned parity BLOCK_N under-fills small-N grids;
+  # the wrapper halves BLOCK_N until the grid reaches min_programs).
+  # 220 = 2 waves x 110 CUs (one MI250X GCD); validation_status: analytical.
+  # Key absent or 0 -> no adaptation.
+  dequant_gemv:
+    min_programs: 220
+
+# Scaled Dot-Product Attention block size thresholds.
+# Schema documented in volta.yml. Decode entries first.
+# CDNA1/2 values conservative for the 64 KB SMEM budget. CDNA3
+# (MI300) has 160 KB and could use larger tiles — when needed,
+# split into cdna3.yml or extend with conditional blocks.
+sdpa_thresholds:
+  # Decode path (seqlen_q ≤ 16)
+  - seqlen_q_le: 16
+    head_dim_ge: 256
+    block_m: 16
+    block_n: 16
+    num_warps: 4
+  - seqlen_q_le: 16
+    block_m: 16
+    block_n: 32
+    num_warps: 4
+  # Prefill path (seqlen_q > 16)
+  - head_dim_ge: 256
+    block_m: 16
+    block_n: 16
+    num_warps: 4
+  - head_dim_ge: 128
+    block_m: 32
+    block_n: 32
+    num_warps: 4
+  - head_dim_lt: 128
+    block_m: 64
+    block_n: 64
+    num_warps: 4
+
+memory:
+  max_shared_memory_per_block: 65536    # 64 KB (CDNA1/2)
+  max_registers_per_block: 65536
+  # AMD schedules in 64-wide WAVEFRONTS where NVIDIA uses 32-wide warps.
+  # Named `warp_size` for schema uniformity, the same convention
+  # apple_silicon.yml follows for its SIMD groups: one hardware concept has
+  # ONE key across every profile, so a consumer never branches on vendor to
+  # find it. Declaring it as `wavefront_size` meant a reader asking for
+  # `memory.warp_size` got nothing on AMD and would fall back to 32 — wrong
+  # by 2x, silently, on every CDNA card.
+  warp_size: 64
+  # The registers ONE lane may address for ordinary (non-matrix) code: the 256 architectural VGPRs V0-V255; the
+  # 256 AccVGPRs beside them in the same file serve the matrix (MFMA) instructions and spills, not a tile's elements
+  # (AMD Instinct MI300 / CDNA3 ISA reference guide, "VGPRs": up to 512 per wave, 256 of each type; CDNA2 the same,
+  # ORNL CDNA2 memory-hierarchy slides). Read by ops/_configs.fits_thread_registers (elements a thread holds).
+  max_registers_per_thread: 256
+  # SDPA deterministic-routing budget (R10 schema parity with
+  # volta.yml). 0 = NOT APPLICABLE: the flash-attention
+  # non-determinism diagnosed in P-TRITON-MOE-DETERMINISM-RESIDUAL
+  # is an NVIDIA Volta-SIMT MMA issue. ROCm/HIP uses a different
+  # Triton backend and matrix-core path; the Volta race does not
+  # transfer. Left 0 (no routing) until/unless empirically shown
+  # otherwise on CDNA hardware. hand_curated_from_docs.
+  sdpa_math_max_scores_bytes: 0
+  # Row block (alignment and floor) of the chunked deterministic
+  # math prefill; the chunk-halving retry on a refused allocation
+  # never goes below it.
+  sdpa_math_min_chunk_rows: 128
+  # Allocator pool: bytes the free-list may keep PARKED per device as a
+  # fraction of that device's memory (2026-09-02, pool default-on gate).
+  # Beyond it the largest parked blocks go back to the driver, bounding
+  # the pool's contribution to the driver watermark (measured +3.4 GB on
+  # the xlong int4 row unbounded). 0 = unbounded.
+  alloc_pool_parked_cap_fraction: 0.50
+precision:
+  # Attention operands that disagree in dtype (an fp16 GEMM stored fp32 feeding V) all take the
+  # narrowest of the three, the compiled engine's alignment: the half attention stays on the matrix
+  # unit (V100, 2026-10-08: 1.16 s/op aligned narrowest vs 22.0 s/op on the scalar flash aligned widest).
+  attention_operands: narrowest
+  # Whether each engine branch's OWN kernels compute float64 / complex128 elements, read with
+  # supports_fp64 (both must hold) -- a CAPABILITY: `compiled` is ATen's, which carries both wherever
+  # the device does; `triton` is the NeuroBrix Triton kernels' (cuda/hip lower double; Metal's
+  # lowering narrows it in silence, measured 2026-09-28 on the Sana 4K positional embedding). Read
+  # by the DtypeEngine (`config.device_supports_fp64`) and by the Triton wrappers' binding
+  # (`triton.dtype.triton_has_fp64` -> `nbx_tensor.set_backend_has_fp64`).
+  kernels_carry_fp64:
+    compiled: true
+    triton: true
+# Software-pipelining budget — see nvidia/volta.yml for the schema.
+#
+# validation_status: conservative_pending_first_light. cp.async is a
+# PTX instruction and does not exist on CDNA; Triton's AMD backend
+# pipelines through LDS by a different mechanism, so Volta's measured
+# fault does not transfer and neither does Ampere's clearance. Until an
+# MI-series card measures it, the cap is 2: clamping can only cost
+# throughput, while allowing unvalidated pipelining could cost
+# correctness. Raising this is a first-light task
+# (docs/internal/amd_first_light.md), not a guess to make from here.
+pipelining:
+  max_num_stages: 2
+
+# Autotune correctness screen. The engine runs every candidate config once and
+# compares its result against a reference config's before timing any of them,
+# because an autotuner that ranks on speed alone selects whichever WRONG
+# kernel is fastest — a kernel that writes half its output does half the
+# stores and wins. Measured on Apple 2026-09-07: fp16 mm [64,32]@[32,64] chose
+# a config that left half the columns zero.
+#
+# These are the tolerances that separate "a different but valid summation
+# order" from "a different answer". Two configs with different block sizes
+# reduce in a different order, so their results differ in the last bits; a
+# config that drops output differs by the scale of the output itself. The
+# gap between those two is several orders of magnitude, and these sit in it.
+#
+# Relative to the reference's own magnitude: max|a - b| / max|b|. Integer
+# and boolean results are compared BIT-IDENTICALLY and ignore this table —
+# there is no valid reordering that changes an integer.
+autotune_screen_rtol:
+  float16: 2.0e-2
+  bfloat16: 4.0e-2
+  float32: 1.0e-4
+  float64: 1.0e-8
+  int64: 0.0               # an integer result (the MoE alignment's routing tables) is met exactly
+
+# Above this many bytes of buffer, the autotune correctness screen does not
+# run. Screening copies every argument out and back once per candidate, so a
+# very large tensor turns a tuning step into hundreds of megabytes of traffic
+# — and on unified memory that pressure is the machine's, not a card's.
+# MEASURED 2026-09-07: unbounded screening of a 151936-wide softmax perturbed
+# six unrelated tests in the same process. A skipped screen is announced, not
+# silent.
+autotune_screen_max_bytes: 33554432
+
+autotune:
+  buckets:
+    # elements — an element-wise launch's element count (`kernels/ops/elementwise_launch.py`), NEVER the `default`
+    # dimension ladder (`autotune_bucket.ladder_for` refuses it). NOT measured on this architecture (no such device on
+    # either machine): the four classes measured on V100-SXM2 2026-10-23 (nvidia/volta.yml, launch-bound under 65 536
+    # elements, bandwidth classes above) and confirmed on apple_m4_pro 2026-10-24 — the measurement on this
+    # architecture is owed (docs/reference/owed-proofs.md, "element-wise ladder per architecture").
+    elements:
+      - {up_to: 65536, step: 65536}
+      - {up_to: 1048576, step: 1048576}
+      - {up_to: 16777216, step: 16777216}
+      - {up_to: null, step: 68719476736}
+    default:
+      - {up_to: 64, step: 1}
+      - {up_to: 256, step: 16}
+      - {up_to: 1024, step: 32}
+      - {up_to: 8192, step: 128}
+      # Above 8 192 a QUARTER-OCTAVE, not a 512-step. The 512 tail was decided by a sweep
+      # that ran to about 4 096 and never met a request-scale dimension: a vocoder's batched
+      # GEMM keys on the WAVEFORM and reaches 1 963 520, which a 512-step cuts into some four
+      # thousand buckets — 1 400 of one model's 1 522 distinct M values sat above 8 192.
+      # Measured 2026-09-22 on both classes, two shapes (the vocoder's B=1,N=1,K=9 and a
+      # GEMM at N=K=512), each octave bucket carrying three or four measured values with its
+      # TOP as representative: 0.0 % median loss, 0.2 % max at ONE octave bucket. The rows
+      # below are finer than the octave that was measured, so they cost no more than it did.
+      # The first three octaves above the knee keep a NARROW step. Measured directly on the
+      # rows as shipped (the upscalers' N=360, K=180; three sizes inside each bucket with
+      # its TOP among them, 2026-09-22): a quarter-octave there cost 0.0 % median but
+      # **5.2 %** at the 10 240 bucket and 1.2 % at 16 384 — the loss lives just above the
+      # knee, where a quarter of an OCTAVE is still a quarter of the VALUE. Beyond 65 536
+      # the same sweep measured 0.0 % median and at most 0.6 %, so the quarter-octave stands.
+      # The convolution-width ladder below keeps its quarter-octave: its own sweep measured
+      # 0.0 % median AND max there, on both classes and two channel counts.
+      - {up_to: 16384, step: 512}
+      - {up_to: 32768, step: 1024}
+      - {up_to: 65536, step: 2048}
+      - {up_to: 131072, step: 16384}
+      - {up_to: 262144, step: 32768}
+      - {up_to: 524288, step: 65536}
+      - {up_to: 1048576, step: 131072}
+      - {up_to: 2097152, step: 262144}
+      - {up_to: null, step: 524288}
+    # The width of a ONE-ROW convolution (a 1-D convolution over a sequence: a vocoder's
+    # samples, a mel spectrogram's frames) is the request's length, unbounded by any
+    # resolution — chatterbox's vocoder reaches 444 721 samples for 18 s of speech. Above the
+    # GEMM ladder it steps by a quarter-octave (≤ 25 % of the value), so a census meets every
+    # class of a speech length in ~100 runs instead of ~1 000; the loss of that step is owed a
+    # measurement on both classes (bucket_loss.py) before the ladder is called final.
+    W:
+      - {up_to: 64, step: 1}
+      - {up_to: 256, step: 16}
+      - {up_to: 1024, step: 32}
+      - {up_to: 8192, step: 128}
+      - {up_to: 16384, step: 2048}
+      - {up_to: 32768, step: 4096}
+      - {up_to: 65536, step: 8192}
+      - {up_to: 131072, step: 16384}
+      - {up_to: 262144, step: 32768}
+      - {up_to: 524288, step: 65536}
+      - {up_to: null, step: 131072}
+
+# The flash kernel at a power-of-two head dim >= 128 is NOT measured on this architecture: the zero-pad
+# detour stays (launch_keys.flash_headdim_detour). Declared, never left absent: true only where the
+# correctness oracle was run with the detour off on this arch and stack (Volta, Triton 3.8, 2026-10-03).
+flash:
+  pow2_head_dim_correct: false
+
+# Convolution weight storage order (launch_keys.conv_weight_layout): KCRS, the container's own,
+# until this arch measures KRSC (the M4 Pro measured +46-63 % on its 3x3 keys, 2026-10-07).
+conv:
+  weight_layout: KCRS

nbxtensor/backend/devices/amd/cdna3.yml

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+# The library's half of amd/cdna3.yml: the keys nbxtensor reads (docs/nbxtensor/device_keys.txt),
+# moved with their sources by tools/split_vendor_files.py. NeuroBrix's half stays in
+# src/neurobrix/config/vendors/amd/cdna3.yml; the engine reads the two merged.
+
+architecture: cdna3
+compute_capability: "gfx942"  # MI300X (MI300A = gfx940/gfx941)
+
+block_sizes:
+  # Default block size for simple kernels
+  default: 1024
+
+  # Batched Matrix Multiply configuration
+  bmm:
+    block_m: 64
+    block_n: 64
+    block_k: 16
+    num_warps: 4
+
+  # Convolution configuration
+  conv2d:
+    block_h: 16
+    block_w: 16
+    num_warps: 4
+
+  # Generic reduction block size
+  reduction: 1024
+  # M=1 dequant-GEMV occupancy rule — see nvidia/volta.yml for the
+  # full rationale (pinned parity BLOCK_N under-fills small-N grids;
+  # the wrapper halves BLOCK_N until the grid reaches min_programs).
+  # 608 = 2 waves x 304 CUs (MI300X); validation_status: analytical.
+  # Key absent or 0 -> no adaptation.
+  dequant_gemv:
+    min_programs: 608
+
+# Scaled Dot-Product Attention block size thresholds.
+# Schema documented in volta.yml. Decode entries first.
+# Values inherited from CDNA1/2 (conservative for 64 KB). MI300's
+# 160 KB LDS allows larger tiles — unmeasured, see the memory note.
+sdpa_thresholds:
+  # Decode path (seqlen_q ≤ 16)
+  - seqlen_q_le: 16
+    head_dim_ge: 256
+    block_m: 16
+    block_n: 16
+    num_warps: 4
+  - seqlen_q_le: 16
+    block_m: 16
+    block_n: 32
+    num_warps: 4
+  # Prefill path (seqlen_q > 16)
+  - head_dim_ge: 256
+    block_m: 16
+    block_n: 16
+    num_warps: 4
+  - head_dim_ge: 128
+    block_m: 32
+    block_n: 32
+    num_warps: 4
+  - head_dim_lt: 128
+    block_m: 64
+    block_n: 64
+    num_warps: 4
+
+memory:
+  max_shared_memory_per_block: 163840   # 160 KB LDS per CU (CDNA3)
+  max_registers_per_block: 65536
+  # AMD schedules in 64-wide WAVEFRONTS where NVIDIA uses 32-wide warps.
+  # Named `warp_size` for schema uniformity, the same convention
+  # apple_silicon.yml follows for its SIMD groups: one hardware concept has
+  # ONE key across every profile, so a consumer never branches on vendor to
+  # find it. Declaring it as `wavefront_size` meant a reader asking for
+  # `memory.warp_size` got nothing on AMD and would fall back to 32 — wrong
+  # by 2x, silently, on every CDNA card.
+  warp_size: 64
+  # The registers ONE lane may address for ordinary (non-matrix) code: the 256 architectural VGPRs V0-V255; the
+  # 256 AccVGPRs beside them in the same file serve the matrix (MFMA) instructions and spills, not a tile's elements
+  # (AMD Instinct MI300 / CDNA3 ISA reference guide, "VGPRs": up to 512 per wave, 256 of each type; CDNA2 the same,
+  # ORNL CDNA2 memory-hierarchy slides). Read by ops/_configs.fits_thread_registers (elements a thread holds).
+  max_registers_per_thread: 256
+  # SDPA deterministic-routing budget (R10 schema parity with
+  # volta.yml). 0 = NOT APPLICABLE: the flash-attention
+  # non-determinism diagnosed in P-TRITON-MOE-DETERMINISM-RESIDUAL
+  # is an NVIDIA Volta-SIMT MMA issue. ROCm/HIP uses a different
+  # Triton backend and matrix-core path; the Volta race does not
+  # transfer. Left 0 (no routing) until/unless empirically shown
+  # otherwise on CDNA hardware. hand_curated_from_docs.
+  sdpa_math_max_scores_bytes: 0
+  # Row block (alignment and floor) of the chunked deterministic
+  # math prefill; the chunk-halving retry on a refused allocation
+  # never goes below it.
+  sdpa_math_min_chunk_rows: 128
+  # Allocator pool: bytes the free-list may keep PARKED per device as a
+  # fraction of that device's memory (2026-09-02, pool default-on gate).
+  # Beyond it the largest parked blocks go back to the driver, bounding
+  # the pool's contribution to the driver watermark (measured +3.4 GB on
+  # the xlong int4 row unbounded). 0 = unbounded.
+  alloc_pool_parked_cap_fraction: 0.50
+precision:
+  # Attention operands that disagree in dtype (an fp16 GEMM stored fp32 feeding V) all take the
+  # narrowest of the three, the compiled engine's alignment: the half attention stays on the matrix
+  # unit (V100, 2026-10-08: 1.16 s/op aligned narrowest vs 22.0 s/op on the scalar flash aligned widest).
+  attention_operands: narrowest
+  # Whether each engine branch's OWN kernels compute float64 / complex128 elements, read with
+  # supports_fp64 (both must hold) -- a CAPABILITY: `compiled` is ATen's, which carries both wherever
+  # the device does; `triton` is the NeuroBrix Triton kernels' (cuda/hip lower double; Metal's
+  # lowering narrows it in silence, measured 2026-09-28 on the Sana 4K positional embedding). Read
+  # by the DtypeEngine (`config.device_supports_fp64`) and by the Triton wrappers' binding
+  # (`triton.dtype.triton_has_fp64` -> `nbx_tensor.set_backend_has_fp64`).
+  kernels_carry_fp64:
+    compiled: true
+    triton: true
+# Software-pipelining budget — see nvidia/volta.yml for the schema.
+#
+# validation_status: conservative_pending_first_light. cp.async is a
+# PTX instruction and does not exist on CDNA; Triton's AMD backend
+# pipelines through LDS by a different mechanism, so Volta's measured
+# fault does not transfer and neither does Ampere's clearance. Until an
+# MI-series card measures it, the cap is 2: clamping can only cost
+# throughput, while allowing unvalidated pipelining could cost
+# correctness. Raising this is a first-light task
+# (docs/internal/amd_first_light.md), not a guess to make from here.
+pipelining:
+  max_num_stages: 2
+
+# Autotune correctness screen. The engine runs every candidate config once and
+# compares its result against a reference config's before timing any of them,
+# because an autotuner that ranks on speed alone selects whichever WRONG
+# kernel is fastest — a kernel that writes half its output does half the
+# stores and wins. Measured on Apple 2026-09-07: fp16 mm [64,32]@[32,64] chose
+# a config that left half the columns zero.
+#
+# These are the tolerances that separate "a different but valid summation
+# order" from "a different answer". Two configs with different block sizes
+# reduce in a different order, so their results differ in the last bits; a
+# config that drops output differs by the scale of the output itself. The
+# gap between those two is several orders of magnitude, and these sit in it.
+#
+# Relative to the reference's own magnitude: max|a - b| / max|b|. Integer
+# and boolean results are compared BIT-IDENTICALLY and ignore this table —
+# there is no valid reordering that changes an integer.
+autotune_screen_rtol:
+  float16: 2.0e-2
+  bfloat16: 4.0e-2
+  float32: 1.0e-4
+  float64: 1.0e-8
+  int64: 0.0               # an integer result (the MoE alignment's routing tables) is met exactly
+
+# Above this many bytes of buffer, the autotune correctness screen does not
+# run. Screening copies every argument out and back once per candidate, so a
+# very large tensor turns a tuning step into hundreds of megabytes of traffic
+# — and on unified memory that pressure is the machine's, not a card's.
+# MEASURED 2026-09-07: unbounded screening of a 151936-wide softmax perturbed
+# six unrelated tests in the same process. A skipped screen is announced, not
+# silent.
+autotune_screen_max_bytes: 33554432
+
+autotune:
+  buckets:
+    # elements — an element-wise launch's element count (`kernels/ops/elementwise_launch.py`), NEVER the `default`
+    # dimension ladder (`autotune_bucket.ladder_for` refuses it). NOT measured on this architecture (no such device on
+    # either machine): the four classes measured on V100-SXM2 2026-10-23 (nvidia/volta.yml, launch-bound under 65 536
+    # elements, bandwidth classes above) and confirmed on apple_m4_pro 2026-10-24 — the measurement on this
+    # architecture is owed (docs/reference/owed-proofs.md, "element-wise ladder per architecture").
+    elements:
+      - {up_to: 65536, step: 65536}
+      - {up_to: 1048576, step: 1048576}
+      - {up_to: 16777216, step: 16777216}
+      - {up_to: null, step: 68719476736}
+    default:
+      - {up_to: 64, step: 1}
+      - {up_to: 256, step: 16}
+      - {up_to: 1024, step: 32}
+      - {up_to: 8192, step: 128}
+      # Above 8 192 a QUARTER-OCTAVE, not a 512-step. The 512 tail was decided by a sweep
+      # that ran to about 4 096 and never met a request-scale dimension: a vocoder's batched
+      # GEMM keys on the WAVEFORM and reaches 1 963 520, which a 512-step cuts into some four
+      # thousand buckets — 1 400 of one model's 1 522 distinct M values sat above 8 192.
+      # Measured 2026-09-22 on both classes, two shapes (the vocoder's B=1,N=1,K=9 and a
+      # GEMM at N=K=512), each octave bucket carrying three or four measured values with its
+      # TOP as representative: 0.0 % median loss, 0.2 % max at ONE octave bucket. The rows
+      # below are finer than the octave that was measured, so they cost no more than it did.
+      # The first three octaves above the knee keep a NARROW step. Measured directly on the
+      # rows as shipped (the upscalers' N=360, K=180; three sizes inside each bucket with
+      # its TOP among them, 2026-09-22): a quarter-octave there cost 0.0 % median but
+      # **5.2 %** at the 10 240 bucket and 1.2 % at 16 384 — the loss lives just above the
+      # knee, where a quarter of an OCTAVE is still a quarter of the VALUE. Beyond 65 536
+      # the same sweep measured 0.0 % median and at most 0.6 %, so the quarter-octave stands.
+      # The convolution-width ladder below keeps its quarter-octave: its own sweep measured
+      # 0.0 % median AND max there, on both classes and two channel counts.
+      - {up_to: 16384, step: 512}
+      - {up_to: 32768, step: 1024}
+      - {up_to: 65536, step: 2048}
+      - {up_to: 131072, step: 16384}
+      - {up_to: 262144, step: 32768}
+      - {up_to: 524288, step: 65536}
+      - {up_to: 1048576, step: 131072}
+      - {up_to: 2097152, step: 262144}
+      - {up_to: null, step: 524288}
+    # The width of a ONE-ROW convolution (a 1-D convolution over a sequence: a vocoder's
+    # samples, a mel spectrogram's frames) is the request's length, unbounded by any
+    # resolution — chatterbox's vocoder reaches 444 721 samples for 18 s of speech. Above the
+    # GEMM ladder it steps by a quarter-octave (≤ 25 % of the value), so a census meets every
+    # class of a speech length in ~100 runs instead of ~1 000; the loss of that step is owed a
+    # measurement on both classes (bucket_loss.py) before the ladder is called final.
+    W:
+      - {up_to: 64, step: 1}
+      - {up_to: 256, step: 16}
+      - {up_to: 1024, step: 32}
+      - {up_to: 8192, step: 128}
+      - {up_to: 16384, step: 2048}
+      - {up_to: 32768, step: 4096}
+      - {up_to: 65536, step: 8192}
+      - {up_to: 131072, step: 16384}
+      - {up_to: 262144, step: 32768}
+      - {up_to: 524288, step: 65536}
+      - {up_to: null, step: 131072}
+
+# The flash kernel at a power-of-two head dim >= 128 is NOT measured on this architecture: the zero-pad
+# detour stays (launch_keys.flash_headdim_detour). Declared, never left absent: true only where the
+# correctness oracle was run with the detour off on this arch and stack (Volta, Triton 3.8, 2026-10-03).
+flash:
+  pow2_head_dim_correct: false
+
+# Convolution weight storage order (launch_keys.conv_weight_layout): KCRS, the container's own,
+# until this arch measures KRSC (the M4 Pro measured +46-63 % on its 3x3 keys, 2026-10-07).
+conv:
+  weight_layout: KCRS