mlsys-lab 0.1.0__py3-none-any.whl

mlsys/sim/abi.py

@@ -0,0 +1,48 @@
+"""Deterministic C++ ABI model — the MLSYS VIRTUAL ABI (pinned LP64, Itanium).
+Pure Python, identical on every machine (unlike ctypes.sizeof, which differs by
+OS/compiler). Fixed type sizes + natural alignment + standard struct padding, so
+'predict the sizeof / offsets' has ONE right answer everywhere.
+"""
+# pinned sizes/alignment (LP64: long = 8, pointer = 8) — natural alignment
+SIZE = {"bool": 1, "char": 1, "signed char": 1, "unsigned char": 1,
+        "short": 2, "unsigned short": 2, "int": 4, "unsigned int": 4,
+        "long": 8, "unsigned long": 8, "long long": 8, "unsigned long long": 8,
+        "float": 4, "double": 8, "long double": 16, "pointer": 8}
+ALIGN = dict(SIZE)
+
+
+def _sz_al(t):
+    if t.endswith("*"):
+        return 8, 8  # any pointer
+    if t not in SIZE:
+        raise KeyError(f"unknown type {t!r}")
+    return SIZE[t], ALIGN[t]
+
+
+def layout(fields, packed=False):
+    """fields: list of type names (e.g. ['char','int','double']) in declaration
+    order. Returns {size, alignment, offsets} under standard C/C++ layout.
+    packed=True disables padding (alignment 1)."""
+    offset = 0
+    max_align = 1
+    offsets = []
+    for t in fields:
+        sz, al = _sz_al(t)
+        if packed:
+            al = 1
+        pad = (-offset) % al
+        offset += pad
+        offsets.append(offset)
+        offset += sz
+        max_align = max(max_align, al)
+    tail = (-offset) % max_align            # trailing padding to struct alignment
+    total = offset + tail
+    return {"size": total, "alignment": max_align, "offsets": offsets}
+
+
+def sizeof(fields, packed=False):
+    return layout(fields, packed)["size"]
+
+
+def offsetof(fields, i, packed=False):
+    return layout(fields, packed)["offsets"][i]

mlsys/sim/cache.py

@@ -0,0 +1,55 @@
+"""Deterministic set-associative cache simulator.
+Runs identically on every machine (pure Python, no hardware). Tasks feed a trace
+of byte addresses; the model returns exact hit/miss/eviction counts under LRU.
+This is the MLSYS VIRTUAL CACHE — a pinned spec, the same for everyone.
+"""
+from collections import OrderedDict
+
+
+class Cache:
+    def __init__(self, line_bytes=64, sets=64, ways=8, policy="lru"):
+        assert policy in ("lru", "fifo")
+        self.line_bytes = line_bytes
+        self.sets = sets
+        self.ways = ways
+        self.policy = policy
+        self.reset()
+
+    def reset(self):
+        self._sets = [OrderedDict() for _ in range(self.sets)]  # set -> {tag: True} MRU last
+        self.hits = 0
+        self.misses = 0
+        self.evictions = 0
+
+    def _index_tag(self, addr):
+        block = addr // self.line_bytes
+        return block % self.sets, block // self.sets
+
+    def access(self, addr):
+        """One access to a byte address. Returns True on hit, False on miss."""
+        idx, tag = self._index_tag(addr)
+        s = self._sets[idx]
+        if tag in s:
+            self.hits += 1
+            if self.policy == "lru":
+                s.move_to_end(tag)
+            return True
+        self.misses += 1
+        if len(s) >= self.ways:
+            s.popitem(last=False)  # evict LRU/FIFO (oldest)
+            self.evictions += 1
+        s[tag] = True
+        return False
+
+    def run(self, addresses):
+        """Feed an iterable of byte addresses; return the summary dict."""
+        for a in addresses:
+            self.access(int(a))
+        total = self.hits + self.misses
+        return {"hits": self.hits, "misses": self.misses, "evictions": self.evictions,
+                "accesses": total, "miss_rate": (self.misses / total) if total else 0.0}
+
+
+def simulate(addresses, line_bytes=64, sets=64, ways=8, policy="lru"):
+    """Convenience: build a fresh cache and run the trace. Deterministic."""
+    return Cache(line_bytes, sets, ways, policy).run(addresses)