m68000-python 0.1.0__py3-none-any.whl

m68000_python/_dispatch.py

@@ -0,0 +1,243 @@
+"""The opcode map: which handler each of the 65,536 first words runs.
+
+``RULES`` below is the 68000 instruction set as PRM Section 8 prints it, one
+line per encoding: a 16-character bit pattern, the handler, and the operand
+constraint.  In a pattern ``0`` and ``1`` are fixed bits and letters are
+fields: ``ss`` a size (00 byte, 01 word, 10 long; 11 is never that
+instruction), ``eeeeee`` an effective address, anything else a field the
+handler decodes.  The constraint names the addressing category of PRM Table
+2-4 the EA field must fall in; an EA outside it makes the word something
+else or illegal (UM 6.3.6, docs/undocumented-behavior.md).
+
+:func:`build_table` walks all 65,536 words once per class, at first use, and
+checks that no word matches two rules.  A word that matches none runs the
+illegal-instruction exception, or the line 1010 / line 1111 emulator
+exception when its top four bits say so (UM 6.3.6).  Dispatch is then one
+list index and one call per instruction; handlers receive the opcode word
+and never see the table.
+"""
+
+from collections.abc import Callable
+
+from m68000_python._ea import (
+    ALL,
+    ALTERABLE,
+    AN,
+    CONTROL,
+    DATA,
+    DATA_ALTERABLE,
+    EA_KIND,
+    MEMORY_ALTERABLE,
+    POSTINC,
+    PREDEC,
+)
+
+Check = Callable[[int], bool]
+
+
+def _ea_field(opcode: int) -> int | None:
+    return EA_KIND[opcode & 0x3F]
+
+
+def ea(category: frozenset) -> Check:
+    """The EA in bits 5-0 must be in ``category``."""
+    return lambda opcode: _ea_field(opcode) in category
+
+
+def sized(category: frozenset) -> Check:
+    """Size in bits 7-6 is not 11, the EA is in ``category``, and An is never a byte."""
+
+    def check(opcode: int) -> bool:
+        size_bits = (opcode >> 6) & 3
+        kind = _ea_field(opcode)
+        if size_bits == 3 or kind not in category:
+            return False
+        return not (size_bits == 0 and kind == AN)
+
+    return check
+
+
+def any_size_register(opcode: int) -> bool:
+    """Register forms with a size field (ADDX, SUBX, CMPM, shifts): not 11."""
+    return (opcode >> 6) & 3 != 3
+
+
+def move(opcode: int) -> bool:
+    """MOVE: source any mode (no An for a byte), destination data alterable (PRM 4, MOVE)."""
+    source = _ea_field(opcode)
+    destination = EA_KIND[((opcode >> 3) & 0x38) | ((opcode >> 9) & 7)]
+    if source is None or destination not in DATA_ALTERABLE:
+        return False
+    return not ((opcode >> 12) == 1 and source == AN)
+
+
+def movea(opcode: int) -> bool:
+    """MOVEA: any source mode, word or long only (PRM 4, MOVEA)."""
+    return _ea_field(opcode) is not None
+
+
+def always(opcode: int) -> bool:
+    return True
+
+
+CONTROL_ALTERABLE = CONTROL & ALTERABLE
+
+#: (bit pattern, handler, constraint) -- PRM Section 8, in opcode-map order.
+RULES: tuple[tuple[str, str, Check], ...] = (
+    # 0000: bit manipulation, MOVEP, immediate
+    ("0000 0000 0011 1100", "ori_to_ccr", always),
+    ("0000 0000 0111 1100", "ori_to_sr", always),
+    ("0000 0000 ssee eeee", "ori", sized(DATA_ALTERABLE)),
+    ("0000 0010 0011 1100", "andi_to_ccr", always),
+    ("0000 0010 0111 1100", "andi_to_sr", always),
+    ("0000 0010 ssee eeee", "andi", sized(DATA_ALTERABLE)),
+    ("0000 0100 ssee eeee", "subi", sized(DATA_ALTERABLE)),
+    ("0000 0110 ssee eeee", "addi", sized(DATA_ALTERABLE)),
+    ("0000 1010 0011 1100", "eori_to_ccr", always),
+    ("0000 1010 0111 1100", "eori_to_sr", always),
+    ("0000 1010 ssee eeee", "eori", sized(DATA_ALTERABLE)),
+    ("0000 1100 ssee eeee", "cmpi", sized(DATA_ALTERABLE)),
+    ("0000 1000 00ee eeee", "btst", ea(DATA - {11})),
+    ("0000 1000 01ee eeee", "bchg", ea(DATA_ALTERABLE)),
+    ("0000 1000 10ee eeee", "bclr", ea(DATA_ALTERABLE)),
+    ("0000 1000 11ee eeee", "bset", ea(DATA_ALTERABLE)),
+    ("0000 rrr1 00ee eeee", "btst", ea(DATA)),
+    ("0000 rrr1 01ee eeee", "bchg", ea(DATA_ALTERABLE)),
+    ("0000 rrr1 10ee eeee", "bclr", ea(DATA_ALTERABLE)),
+    ("0000 rrr1 11ee eeee", "bset", ea(DATA_ALTERABLE)),
+    ("0000 rrr1 oo00 1aaa", "movep", always),
+    # 0001, 0010, 0011: MOVE and MOVEA
+    ("0001 RRRM MMee eeee", "move", move),
+    ("0011 RRRM MMee eeee", "move", move),
+    ("0010 RRRM MMee eeee", "move", move),
+    ("0011 aaa0 01ee eeee", "movea", movea),
+    ("0010 aaa0 01ee eeee", "movea", movea),
+    # 0100: miscellaneous
+    ("0100 0000 11ee eeee", "move_from_sr", ea(DATA_ALTERABLE)),
+    ("0100 0000 ssee eeee", "negx", sized(DATA_ALTERABLE)),
+    ("0100 0010 ssee eeee", "clr", sized(DATA_ALTERABLE)),
+    ("0100 0100 11ee eeee", "move_to_ccr", ea(DATA)),
+    ("0100 0100 ssee eeee", "neg", sized(DATA_ALTERABLE)),
+    ("0100 0110 11ee eeee", "move_to_sr", ea(DATA)),
+    ("0100 0110 ssee eeee", "not", sized(DATA_ALTERABLE)),
+    ("0100 1000 00ee eeee", "nbcd", ea(DATA_ALTERABLE)),
+    ("0100 1000 0100 0rrr", "swap", always),
+    ("0100 1000 01ee eeee", "pea", ea(CONTROL)),
+    ("0100 1000 1000 0rrr", "ext", always),
+    ("0100 1000 1100 0rrr", "ext", always),
+    ("0100 1000 1see eeee", "movem", ea(CONTROL_ALTERABLE | {PREDEC})),
+    ("0100 1010 1111 1100", "illegal", always),
+    ("0100 1010 11ee eeee", "tas", ea(DATA_ALTERABLE)),
+    ("0100 1010 ssee eeee", "tst", sized(DATA_ALTERABLE)),
+    ("0100 1100 1see eeee", "movem", ea(CONTROL | {POSTINC})),
+    ("0100 1110 0100 vvvv", "trap", always),
+    ("0100 1110 0101 0rrr", "link", always),
+    ("0100 1110 0101 1rrr", "unlk", always),
+    ("0100 1110 0110 drrr", "move_usp", always),
+    ("0100 1110 0111 0000", "reset", always),
+    ("0100 1110 0111 0001", "nop", always),
+    ("0100 1110 0111 0010", "stop", always),
+    ("0100 1110 0111 0011", "rte", always),
+    ("0100 1110 0111 0101", "rts", always),
+    ("0100 1110 0111 0110", "trapv", always),
+    ("0100 1110 0111 0111", "rtr", always),
+    ("0100 1110 10ee eeee", "jsr", ea(CONTROL)),
+    ("0100 1110 11ee eeee", "jmp", ea(CONTROL)),
+    ("0100 rrr1 10ee eeee", "chk", ea(DATA)),
+    ("0100 rrr1 11ee eeee", "lea", ea(CONTROL)),
+    # 0101: ADDQ, SUBQ, Scc, DBcc
+    ("0101 qqq0 ssee eeee", "addq", sized(ALTERABLE)),
+    ("0101 qqq1 ssee eeee", "subq", sized(ALTERABLE)),
+    ("0101 cccc 1100 1rrr", "dbcc", always),
+    ("0101 cccc 11ee eeee", "scc", ea(DATA_ALTERABLE)),
+    # 0110: Bcc, BRA, BSR; 0111: MOVEQ
+    ("0110 0000 dddd dddd", "bra", always),
+    ("0110 0001 dddd dddd", "bsr", always),
+    ("0110 cccc dddd dddd", "bcc", lambda opcode: ((opcode >> 8) & 0xF) >= 2),
+    ("0111 rrr0 dddd dddd", "moveq", always),
+    # 1000: OR, DIVU, DIVS, SBCD
+    ("1000 rrr0 11ee eeee", "divu", ea(DATA)),
+    ("1000 rrr1 11ee eeee", "divs", ea(DATA)),
+    ("1000 yyy1 0000 mxxx", "sbcd", always),
+    ("1000 rrr0 ssee eeee", "or", sized(DATA)),
+    ("1000 rrr1 ssee eeee", "or", sized(MEMORY_ALTERABLE)),
+    # 1001: SUB, SUBA, SUBX
+    ("1001 aaas 11ee eeee", "suba", ea(ALL)),
+    ("1001 yyy1 ss00 mxxx", "subx", any_size_register),
+    ("1001 rrr0 ssee eeee", "sub", sized(ALL)),
+    ("1001 rrr1 ssee eeee", "sub", sized(MEMORY_ALTERABLE)),
+    # 1011: CMP, CMPA, CMPM, EOR
+    ("1011 aaas 11ee eeee", "cmpa", ea(ALL)),
+    ("1011 yyy1 ss00 1xxx", "cmpm", any_size_register),
+    ("1011 rrr0 ssee eeee", "cmp", sized(ALL)),
+    ("1011 rrr1 ssee eeee", "eor", sized(DATA_ALTERABLE)),
+    # 1100: AND, MULU, MULS, ABCD, EXG
+    ("1100 rrr0 11ee eeee", "mulu", ea(DATA)),
+    ("1100 rrr1 11ee eeee", "muls", ea(DATA)),
+    ("1100 yyy1 0000 mxxx", "abcd", always),
+    ("1100 xxx1 0100 0yyy", "exg", always),
+    ("1100 xxx1 0100 1yyy", "exg", always),
+    ("1100 xxx1 1000 1yyy", "exg", always),
+    ("1100 rrr0 ssee eeee", "and", sized(DATA)),
+    ("1100 rrr1 ssee eeee", "and", sized(MEMORY_ALTERABLE)),
+    # 1101: ADD, ADDA, ADDX
+    ("1101 aaas 11ee eeee", "adda", ea(ALL)),
+    ("1101 yyy1 ss00 mxxx", "addx", any_size_register),
+    ("1101 rrr0 ssee eeee", "add", sized(ALL)),
+    ("1101 rrr1 ssee eeee", "add", sized(MEMORY_ALTERABLE)),
+    # 1110: shifts and rotates, memory (word, by one) then register forms
+    ("1110 000d 11ee eeee", "asd_memory", ea(MEMORY_ALTERABLE)),
+    ("1110 001d 11ee eeee", "lsd_memory", ea(MEMORY_ALTERABLE)),
+    ("1110 010d 11ee eeee", "roxd_memory", ea(MEMORY_ALTERABLE)),
+    ("1110 011d 11ee eeee", "rod_memory", ea(MEMORY_ALTERABLE)),
+    ("1110 cccd ssi0 0rrr", "asd", any_size_register),
+    ("1110 cccd ssi0 1rrr", "lsd", any_size_register),
+    ("1110 cccd ssi1 0rrr", "roxd", any_size_register),
+    ("1110 cccd ssi1 1rrr", "rod", any_size_register),
+)
+
+
+def _mask_and_value(pattern: str) -> tuple[int, int]:
+    bits = pattern.replace(" ", "")
+    assert len(bits) == 16, pattern
+    mask = value = 0
+    for bit in bits:
+        mask <<= 1
+        value <<= 1
+        if bit in "01":
+            mask |= 1
+            value |= bit == "1"
+    return mask, value
+
+
+#: RULES with each pattern turned into (mask, value), in the same order.
+COMPILED = tuple((*_mask_and_value(pattern), name, check) for pattern, name, check in RULES)
+
+
+def decode(opcode: int) -> str:
+    """The handler name for ``opcode``: a rule's, or illegal / line_a / line_f."""
+    found = [
+        name for mask, value, name, check in COMPILED if opcode & mask == value and check(opcode)
+    ]
+    if len(found) > 1:
+        raise AssertionError(f"{opcode:04X} matches {found}")
+    if found:
+        return found[0]
+    family = opcode >> 12
+    if family == 0xA:
+        return "line_a"
+    if family == 0xF:
+        return "line_f"
+    return "illegal"
+
+
+#: The handler name of every first word, computed once at import.
+NAMES: tuple[str, ...] = tuple(decode(opcode) for opcode in range(0x10000))
+
+Handler = Callable[..., None]
+
+
+def build_table(cls: type) -> list[Handler]:
+    """Return the 65,536 dispatch entries of ``cls``: ``table[opcode](cpu, opcode)``."""
+    handlers = {name: getattr(cls, "_op_" + name) for name in set(NAMES)}
+    return [handlers[name] for name in NAMES]

m68000_python/_ea.py

@@ -0,0 +1,177 @@
+"""Effective addresses: the twelve modes of the 68000 (PRM 2.2).
+
+The 6-bit EA field is ``mode:register``; mode 7 uses the register field to
+select five more forms.  :data:`EA_KIND` maps the field to one of the twelve
+kinds below once, at import, and handlers carry the kind, not the field.
+
+Timing is Table 8-1 of the UM, spent in the order the microcode spends it:
+``-(An)`` and ``(d8,An,Xn)`` start with two internal clocks, extension words
+are taken from the prefetch queue (each one refills it with a program read),
+and the operand access comes last.  The steps that bring the microcode's PC
+register up to the fetch address (what an address error stacks) are the
+corpus's, T3.
+"""
+
+from m68000_python._core import MASK
+
+# The twelve kinds, in PRM 2.2 order.
+DN = 0  # Dn                data register direct
+AN = 1  # An                address register direct
+IND = 2  # (An)              address register indirect
+POSTINC = 3  # (An)+        indirect with postincrement
+PREDEC = 4  # -(An)         indirect with predecrement
+DISP = 5  # (d16,An)        indirect with displacement
+INDEX = 6  # (d8,An,Xn)     indirect with index
+ABSW = 7  # (xxx).W        absolute short
+ABSL = 8  # (xxx).L        absolute long
+PCDISP = 9  # (d16,PC)      program counter with displacement
+PCINDEX = 10  # (d8,PC,Xn)  program counter with index
+IMM = 11  # #<data>         immediate
+
+KIND_NAMES = (
+    "Dn", "An", "(An)", "(An)+", "-(An)", "(d16,An)", "(d8,An,Xn)",
+    "(xxx).W", "(xxx).L", "(d16,PC)", "(d8,PC,Xn)", "#<data>",
+)  # fmt: skip
+
+
+def _kind(field: int) -> int | None:
+    mode, register = field >> 3, field & 7
+    if mode < 7:
+        return mode
+    return (ABSW, ABSL, PCDISP, PCINDEX, IMM, None, None, None)[register]
+
+
+#: EA field (bits 5-0) -> kind, or None for mode 7 registers 5-7 (illegal).
+EA_KIND: tuple[int | None, ...] = tuple(_kind(field) for field in range(64))
+
+# The addressing categories of PRM Table 2-4, as sets of kinds.
+ALL = frozenset(range(12))
+DATA = ALL - {AN}
+MEMORY = ALL - {DN, AN}
+CONTROL = frozenset({IND, DISP, INDEX, ABSW, ABSL, PCDISP, PCINDEX})
+ALTERABLE = frozenset({DN, AN, IND, POSTINC, PREDEC, DISP, INDEX, ABSW, ABSL})
+DATA_ALTERABLE = DATA & ALTERABLE
+MEMORY_ALTERABLE = MEMORY & ALTERABLE
+
+
+def sign_extend_8(value: int) -> int:
+    return (value & 0xFF) - 0x100 if value & 0x80 else value & 0xFF
+
+
+def sign_extend_16(value: int) -> int:
+    return (value & 0xFFFF) - 0x10000 if value & 0x8000 else value & 0xFFFF
+
+
+def word_to_long(value: int) -> int:
+    """A word sign-extended to 32 bits, as An, MOVEM.W and EXT.L take it (PRM 2.3)."""
+    return sign_extend_16(value) & 0xFFFFFFFF
+
+
+class EAMixin:
+    """Private effective-address implementation shared by every family."""
+
+    def _step_size(self, register: int, size: int) -> int:
+        # (A7)+ and -(A7) move by 2 for a byte, keeping SP even (PRM 2.2.4-2.2.5).
+        return 2 if size == 1 and register == 7 else size
+
+    def _index(self, base: int) -> int:
+        """Take the brief extension word from the queue and apply it to ``base``."""
+        return self._indexed(base, self._extension())
+
+    def _indexed(self, base: int, extension: int) -> int:
+        """Apply a brief extension word (PRM 2.4) to ``base``.
+
+        Bits 15-12 name Xn (D0-D7, A0-A7), bit 11 chooses the sign-extended
+        low word (0) or the whole register (1), bits 7-0 are the signed
+        displacement.  Bits 10-8, the 68020's scale, are ignored (PRM 2.4).
+        JMP, JSR, LEA and PEA apply the word still waiting in IRC.
+        """
+        index = self.R[extension >> 12]
+        if not extension & 0x0800:
+            index = sign_extend_16(index)
+        return (base + index + sign_extend_8(extension)) & 0xFFFFFFFF
+
+    def _ea_address(self, kind: int, register: int, size: int) -> int:
+        """Compute a memory operand's address, with its extension words and clocks.
+
+        The standard source-operand sequence: the one TST, CMP, ADD <ea>,Dn
+        and the read half of a read-modify-write use.
+        """
+        R = self.R
+        if kind == IND:
+            return R[8 + register]
+        if kind == POSTINC:
+            address = R[8 + register]
+            R[8 + register] = (address + self._step_size(register, size)) & 0xFFFFFFFF
+            return address
+        if kind == PREDEC:
+            self._cycles += 2
+            self._commit_pc()
+            address = (R[8 + register] - self._step_size(register, size)) & 0xFFFFFFFF
+            R[8 + register] = address
+            return address
+        if kind == DISP:
+            return (R[8 + register] + sign_extend_16(self._extension())) & 0xFFFFFFFF
+        if kind == INDEX:
+            self._cycles += 2
+            return self._index(R[8 + register])
+        if kind == ABSW:
+            self._commit_pc()
+            return word_to_long(self._extension())
+        if kind == ABSL:
+            high = self._extension()
+            self._commit_pc()
+            return ((high << 16) | self._extension()) & 0xFFFFFFFF
+        if kind == PCDISP:
+            base = self._pc - 2  # the address of the extension word itself
+            return (base + sign_extend_16(self._extension())) & 0xFFFFFFFF
+        if kind == PCINDEX:
+            self._cycles += 2
+            return self._index(self._pc - 2)
+        raise AssertionError(f"not a memory kind: {kind}")
+
+    def _ea_read(self, kind: int, register: int, size: int) -> int:
+        """Fetch a source operand of any kind (UM Table 8-1)."""
+        if kind == DN:
+            return self.R[register] & MASK[size]
+        if kind == AN:
+            return self.R[8 + register] & MASK[size]
+        if kind == IMM:
+            if size == 4:
+                return self._extension_long()
+            return self._extension() & MASK[size]
+        return self._ea_fetch(kind, register, size)[1]
+
+    def _ea_fetch(self, kind: int, register: int, size: int) -> tuple[int, int]:
+        """Address and value of a memory operand: the read half of every access.
+
+        PC-relative operands are read in program space (FC 2/6, UM Table 3-2).
+        """
+        if size == 4 and kind == POSTINC:
+            # A long (An)+ steps An between its two reads (SST ADD.l, MOVE.l and
+            # every long (An)+ read; T3): a fault on
+            # the first leaves An alone.
+            R = self.R
+            address = R[8 + register]
+            high = self._read_word(address)
+            R[8 + register] = (address + 4) & 0xFFFFFFFF
+            return address, (high << 16) | self._read_word(address + 2)
+        if size == 4 and kind == PREDEC:
+            # A long -(An) does not bring PC up to date, unlike a word (SST
+            # ADD.l, MOVE.l and every long -(An) read; T3).
+            self._cycles += 2
+            address = (self.R[8 + register] - 4) & 0xFFFFFFFF
+            self.R[8 + register] = address
+            return address, self._read_long(address)
+        address = self._ea_address(kind, register, size)
+        if kind >= PCDISP:
+            return address, self._read_program_operand(size, address)
+        return address, self._read(size, address)
+
+    def _write_register(self, register: int, size: int, value: int) -> None:
+        """Write the low byte, word or all of a data register (PRM 1.1)."""
+        if size == 4:
+            self.R[register] = value & 0xFFFFFFFF
+        else:
+            mask = MASK[size]
+            self.R[register] = (self.R[register] & ~mask & 0xFFFFFFFF) | (value & mask)

m68000_python/_flags.py

@@ -0,0 +1,152 @@
+"""Condition codes: the flag rules of PRM Table 3-18 and the tests of Table 3-19.
+
+Every rule is written once here and used by every family that shares it:
+``_flags_logic`` for the moves, logic and tests (N, Z from the result, V and C
+cleared, X untouched), ``_flags_add``/``_flags_sub`` for binary arithmetic,
+``_flags_cmp`` for the compares (X untouched), and the ``x`` variants for
+ADDX/SUBX/NEGX, whose Z is sticky: cleared by a nonzero result, otherwise
+unchanged (PRM Table 3-18).
+"""
+
+from m68000_python._core import MASK, MSB, C, N, V, X, Z
+
+CONDITION_NAMES = (
+    "T", "F", "HI", "LS", "CC", "CS", "NE", "EQ",
+    "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE",
+)  # fmt: skip
+
+
+def _test(cc: int, ccr: int) -> bool:
+    """PRM Table 3-19, evaluated for one condition and one N/Z/V/C value."""
+    n, z, v, c = bool(ccr & N), bool(ccr & Z), bool(ccr & V), bool(ccr & C)
+    return (
+        True,  # T
+        False,  # F
+        not c and not z,  # HI
+        c or z,  # LS
+        not c,  # CC (HS)
+        c,  # CS (LO)
+        not z,  # NE
+        z,  # EQ
+        not v,  # VC
+        v,  # VS
+        not n,  # PL
+        n,  # MI
+        n == v,  # GE
+        n != v,  # LT
+        not z and n == v,  # GT
+        z or n != v,  # LE
+    )[cc]
+
+
+#: CONDITION[cc][SR & 0xF] is the truth of condition ``cc``; built at import.
+CONDITION: tuple[tuple[bool, ...], ...] = tuple(
+    tuple(_test(cc, ccr) for ccr in range(16)) for cc in range(16)
+)
+
+
+class FlagsMixin:
+    """Private condition-code helpers."""
+
+    def _flags_logic(self, result: int, size: int) -> None:
+        """N and Z from ``result``; V and C cleared; X unchanged."""
+        ccr = self.SR & (0xFF00 | X)
+        if result & MSB[size]:
+            ccr |= N
+        if not result & MASK[size]:
+            ccr |= Z
+        self.SR = ccr
+
+    # A long result leaves the ALU as two words, and the microcode updates the
+    # flags once per word: N Z V C from the low word, then N from the high
+    # word with Z kept only if the high word is zero too.  Only an address
+    # error between the two can see the halfway state; the stacked SR does
+    # (SST MOVE.l, T3).  _flags_logic is the two applied in order.
+
+    def _flags_low_word(self, value: int) -> None:
+        """N Z from the low word; V C cleared (the first half of a long's flags)."""
+        ccr = self.SR & (0xFF00 | X)
+        if value & 0x8000:
+            ccr |= N
+        if not value & 0xFFFF:
+            ccr |= Z
+        self.SR = ccr
+
+    def _flags_high_word(self, value: int) -> None:
+        """N from bit 31; Z kept only if the high word is also zero (the second half)."""
+        ccr = self.SR & ~N
+        if value & 0x80000000:
+            ccr |= N
+        if value & 0xFFFF0000:
+            ccr &= ~Z
+        self.SR = ccr
+
+    def _flags_add(self, destination: int, source: int, result: int, size: int) -> None:
+        """X N Z V C of ``destination + source`` (``result`` unmasked)."""
+        msb = MSB[size]
+        ccr = self.SR & 0xFF00
+        if result & msb:
+            ccr |= N
+        if not result & MASK[size]:
+            ccr |= Z
+        if (source ^ result) & (destination ^ result) & msb:
+            ccr |= V
+        if result > MASK[size]:
+            ccr |= X | C
+        self.SR = ccr
+
+    def _flags_sub(self, destination: int, source: int, result: int, size: int) -> None:
+        """X N Z V C of ``destination - source`` (``result`` unmasked, may be negative)."""
+        msb = MSB[size]
+        ccr = self.SR & 0xFF00
+        if result & msb:
+            ccr |= N
+        if not result & MASK[size]:
+            ccr |= Z
+        if (source ^ destination) & (result ^ destination) & msb:
+            ccr |= V
+        if result < 0:
+            ccr |= X | C
+        self.SR = ccr
+
+    def _flags_cmp(self, destination: int, source: int, result: int, size: int) -> None:
+        """N Z V C of ``destination - source``; X unchanged (PRM Table 3-18, CMP)."""
+        msb = MSB[size]
+        ccr = self.SR & (0xFF00 | X)
+        if result & msb:
+            ccr |= N
+        if not result & MASK[size]:
+            ccr |= Z
+        if (source ^ destination) & (result ^ destination) & msb:
+            ccr |= V
+        if result < 0:
+            ccr |= C
+        self.SR = ccr
+
+    def _flags_addx(self, destination: int, source: int, result: int, size: int) -> None:
+        """ADDX: as ADD, but Z is only ever cleared (PRM Table 3-18)."""
+        msb = MSB[size]
+        ccr = self.SR & (0xFF00 | Z)
+        if result & msb:
+            ccr |= N
+        if result & MASK[size]:
+            ccr &= ~Z
+        if (source ^ result) & (destination ^ result) & msb:
+            ccr |= V
+        if result > MASK[size]:
+            ccr |= X | C
+        self.SR = ccr
+
+    def _flags_subx(self, destination: int, source: int, result: int, size: int) -> None:
+        """SUBX and NEGX: as SUB, but Z is only ever cleared (PRM Table 3-18)."""
+        msb = MSB[size]
+        ccr = self.SR & (0xFF00 | Z)
+        if result & msb:
+            ccr |= N
+        if result & MASK[size]:
+            ccr &= ~Z
+        if (source ^ destination) & (result ^ destination) & msb:
+            ccr |= V
+        if result < 0:
+            ccr |= X | C
+        self.SR = ccr