logiklib 0.1.0__py3-none-any.whl

logiklib/__init__.py

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+__version__ = "0.1.0"
+
+
+def register_part_data(fpga, part_name, package_name):
+    fpga.register_source(
+        package_name,
+        f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz",
+        f"v{__version__}")

logiklib/demo/K4_N8_6x6/K4_N8_6x6.py

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+# Copyright 2024 Zero ASIC Corporation
+
+from logiklib import register_part_data
+
+from siliconcompiler import FPGA
+
+
+####################################################
+# Setup for K4_N8_6x6 FPGA
+####################################################
+def setup():
+    part_name = 'K4_N8_6x6'
+
+    fpga = FPGA(part_name, package=f"logik-fpga-{part_name}")
+
+    register_part_data(fpga, part_name, f"logik-fpga-{part_name}")
+
+    fpga.set('fpga', part_name, 'vendor', 'zeroasic')
+
+    fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'K4_N8_6x6')
+
+    fpga.set('fpga', part_name, 'lutsize', 4)
+
+    fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'ideal')
+
+    fpga.set('fpga', part_name, 'file', 'archfile', 'cad/K4_N8_6x6.xml')
+    fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/K4_N8_6x6_rr_graph.xml')
+
+    for tool in ('vpr', 'yosys'):
+        fpga.set('fpga', part_name, 'var', f'{tool}_registers', 'dff')
+
+    fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/K4_N8_6x6_bitstream_map.json')
+
+    fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/K4_N8_6x6_constraint_map.json')
+
+    fpga.set('fpga', part_name, 'var', 'channelwidth', 50)
+
+    return fpga
+
+
+#########################
+if __name__ == "__main__":
+    fpga = setup()
+    assert fpga.check_filepaths()
+    fpga.write_manifest(f'{fpga.design}.json')

logiklib/demo/K4_N8_6x6/README.md

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+# K4_N8_6x6 FPGA Virtual Architecture
+
+The K4_N8_6x6 FPGA is a fixed-size virtual FPGA architecture consisting of configurable logic blocks (CLBs) and I/O blocks (IOBs).
+
+A summary of K4_N8_6x6 resources is shown in the table below
+
+Resource Type        | Count
+---------------------|------
+Lookup Tables (LUTs) | 288
+Registers            | 288
+GPIOs                | 192
+Max Clock Domains    | 1
+
+K4_N8_6x6 logic resources are organized into an 8x8 array of components.  A 6x6 array of CLBs is surrounded on the perimeter by four banks of IOBs, one per side of the array.  Corner array locations are unused.
+
+## Logic Resources
+
+A brief description for K4_N8_6x6 logic resources is shown below
+
+### Configurable Logic Block (CLB)
+
+Each configurable logic block (CLB) consists of 8 4-input lookup-tables (LUTs).  The LUTs in a CLB share common inputs through local routing called a crossbar.  All LUT outputs are fed back to the crossbar so that they may be used as inputs within the CLB.  Each LUT output can be paired with a flip-flop (register) to synchronize the LUT output to a common clock.  Flip-flops not paired with a LUT can accept crossbar inputs directly.  All flip-flop usage is automatically determined as part of the RTL-to-bitstream flow and is thus transparent to the user.  
+
+### I/O Block (IOB)
+
+General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the FPGA and reconfigurable logic.  Each IOB contains eight iopad primitives.  Each iopad primitive can operate either in input mode or output mode.  The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs.
+
+### Clocking
+
+This architecture uses an ideal clock model; clocks are modeled as globally distributed to all logic resources with zero delay.
+
+## K4_N8_6x6 Configuration
+
+K4_N8_6x6 bitstreams are generated using Logik.  An 8-bit wide interface is used to load a generated bitstream.
+

logiklib/demo/K6_N8_12x12_BD/K6_N8_12x12_BD.py

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+# Copyright 2025 Zero ASIC Corporation
+
+from logiklib import register_part_data
+
+from siliconcompiler import FPGA
+
+
+####################################################
+# Setup for K6_N8_12x12_BD FPGA
+####################################################
+def setup():
+    part_name = 'K6_N8_12x12_BD'
+
+    fpga = FPGA(part_name, package=f"logik-fpga-{part_name}")
+
+    register_part_data(fpga, part_name, f"logik-fpga-{part_name}")
+
+    fpga.set('fpga', part_name, 'vendor', 'zeroasic')
+
+    fpga.set('fpga', part_name, 'var', 'vpr_device_code', part_name)
+
+    fpga.set('fpga', part_name, 'lutsize', 6)
+    fpga.set('fpga', part_name, 'var', 'feature_set', [
+        'async_reset', 'async_set', 'enable'])
+
+    fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'ideal')
+
+    fpga.set('fpga', part_name, 'file', 'archfile', 'cad/K6_N8_12x12_BD.xml')
+    fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/K6_N8_12x12_BD_rr_graph.xml')
+
+    for tool in ('vpr', 'yosys'):
+        fpga.set('fpga', part_name, 'var', f'{tool}_registers', [
+            'dff', 'dffe', 'dffer', 'dffers', 'dffes', 'dffr', 'dffrs', 'dffs',
+            'dsp_mult', 'bram_sp'
+        ])
+
+    fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'techlib/tech_flops.v')
+    fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'techlib/tech_bram.v')
+    fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'techlib/bram_memory_map.txt')
+    fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'techlib/tech_dsp.v')
+
+    # Set the dsp options for the yosys built-in DSP correctly for this
+    # architecture
+    fpga.set('fpga', part_name, 'var', 'yosys_dsp_options', [
+        'DSP_A_MAXWIDTH=18', 'DSP_A_MINWIDTH=2',
+        'DSP_B_MAXWIDTH=18', 'DSP_B_MINWIDTH=2',
+        'DSP_NAME=_dsp_block_'])
+
+    fpga.set('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS')
+
+    fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/K6_N8_12x12_BD_bitstream_map.json')
+
+    fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/K6_N8_12x12_BD_constraint_map.json')
+
+    fpga.set('fpga', part_name, 'var', 'channelwidth', 80)
+
+    return fpga
+
+
+#########################
+if __name__ == "__main__":
+    fpga = setup()
+    assert fpga.check_filepaths()
+    fpga.write_manifest(f'{fpga.design}.json')

logiklib/demo/K6_N8_12x12_BD/README.md

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+# K6_N8_12x12_BD FPGA Virtual Architecture
+
+The K6_N8_12x12_BD FPGA is a fixed-size virtual FPGA architecture consisting of configurable logic blocks (CLBs), multipliers (DSP blocks), single-port SRAM blocks (BRAMs), and I/O blocks (IOBs).
+
+A summary of K6_N8_12x12_BD resources is shown in the table below
+
+Resource Type        | Count
+---------------------|------
+Lookup Tables (LUTs) | 736
+Registers            | 736
+18x18 Multipliers    | 1
+4KB SRAM Blocks      | 1
+GPIOs                | 352
+Max Clock Domains    | 1
+
+K6_N8_12x12_BD logic resources are organized into an 14x14 array of components.  A 12x12 array of logic blocks is surrounded on the perimeter by four banks of IOBs, one per side of the array.  Corner array locations are unused.
+
+## Logic Resources
+
+A brief description for K6_N8_12x12_BD logic resources is shown below
+
+### Configurable Logic Block (CLB)
+
+Each configurable logic block (CLB) consists of 8 6-input lookup-tables (LUTs).  The LUTs in a CLB share common inputs through local routing called a crossbar.  All LUT outputs are fed back to the crossbar so that they may be used as inputs within the CLB.  Each LUT output can be paired with a flip-flop (register) to synchronize the LUT output to a common clock.  Flip-flops not paired with a LUT can accept crossbar inputs directly.  All flip-flop usage is automatically determined as part of the RTL-to-bitstream flow and is thus transparent to the user.  
+
+### I/O Block (IOB)
+
+General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the FPGA and reconfigurable logic.  Each IOB contains eight iopad primitives.  Each iopad primitive can operate either in input mode or output mode.  The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs.
+
+### 18x18 Multiplier Block (DSP)
+
+To demonstrate hard arithmetic technology mapping, hard multipliers are offered.  The multipliers take two 18-bit inputs and produce a 36-bit output.  The block is fully combinational to keep the model as simple as possible.  The multipliers are modeled as occupying a 2x2 footprint within the 12x12 array of logic blocks.  This sizing is chosen for demonstration purposes and does not reflect the relative sizing of the multiplier to the CLB in any process technology.
+
+### SRAM Block (BRAM)
+
+A fixed size single port SRAM is provided to demonstrate memory technology mapping.  The memory macro is 4096x8 bits.  Each macro is modeled as occupying a 2x2 footprint within the 12x12 array of logic blocks.  This sizing is chosen for demonstration purposes and does not reflect the relative sizing of the SRAM to the CLB in any process technology.
+
+### Clocking
+
+This architecture uses an ideal clock model; clocks are modeled as globally distributed to all logic resources with zero delay.
+
+## K6_N8_12x12_BD Configuration
+
+K6_N8_12x12_BD bitstreams are generated using Logik.  An 8-bit wide interface is used to load a generated bitstream.
+

logiklib/demo/K6_N8_28x28_BD/K6_N8_28x28_BD.py

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+# Copyright 2025 Zero ASIC Corporation
+
+from logiklib import register_part_data
+
+from siliconcompiler import FPGA
+
+
+####################################################
+# Setup for K6_N8_28x28_BD FPGA
+####################################################
+def setup():
+    part_name = 'K6_N8_28x28_BD'
+
+    fpga = FPGA(part_name, package=f"logik-fpga-{part_name}")
+
+    register_part_data(fpga, part_name, f"logik-fpga-{part_name}")
+
+    fpga.set('fpga', part_name, 'vendor', 'zeroasic')
+
+    fpga.set('fpga', part_name, 'var', 'vpr_device_code', part_name)
+
+    fpga.set('fpga', part_name, 'lutsize', 6)
+    fpga.set('fpga', part_name, 'var', 'feature_set', [
+        'async_reset', 'async_set', 'enable'])
+
+    fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'ideal')
+
+    fpga.set('fpga', part_name, 'file', 'archfile', 'cad/K6_N8_28x28_BD.xml')
+    fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/K6_N8_28x28_BD_rr_graph.xml')
+
+    for tool in ('vpr', 'yosys'):
+        fpga.set('fpga', part_name, 'var', f'{tool}_registers', [
+            'dff', 'dffe', 'dffer', 'dffers', 'dffes', 'dffr', 'dffrs', 'dffs',
+            'dsp_mult', 'bram_sp'
+        ])
+
+    fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'techlib/tech_flops.v')
+    fpga.set('fpga', part_name, 'file', 'yosys_memory_techmap', 'techlib/tech_bram.v')
+    fpga.set('fpga', part_name, 'file', 'yosys_memory_libmap', 'techlib/bram_memory_map.txt')
+    fpga.set('fpga', part_name, 'file', 'yosys_dsp_techmap', 'techlib/tech_dsp.v')
+
+    # Set the dsp options for the yosys built-in DSP correctly for this
+    # architecture
+    fpga.set('fpga', part_name, 'var', 'yosys_dsp_options', [
+        'DSP_A_MAXWIDTH=18', 'DSP_A_MINWIDTH=2',
+        'DSP_B_MAXWIDTH=18', 'DSP_B_MINWIDTH=2',
+        'DSP_NAME=_dsp_block_'])
+
+    fpga.set('fpga', part_name, 'var', 'dsp_blackbox_options', 'BLACKBOX_MACROS')
+
+    fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/K6_N8_28x28_BD_bitstream_map.json')
+
+    fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/K6_N8_28x28_BD_constraint_map.json')
+
+    fpga.set('fpga', part_name, 'var', 'channelwidth', 120)
+
+    return fpga
+
+
+#########################
+if __name__ == "__main__":
+    fpga = setup()
+    assert fpga.check_filepaths()
+    fpga.write_manifest(f'{fpga.design}.json')

logiklib/demo/K6_N8_28x28_BD/README.md

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+# K6_N8_28x28_BD FPGA Virtual Architecture
+
+The K6_N8_28x28_BD FPGA is a fixed-size virtual FPGA architecture consisting of configurable logic blocks (CLBs), multipliers (DSP blocks), single-port SRAM blocks (BRAMs), and I/O blocks (IOBs).
+
+A summary of K6_N8_28x28_BD resources is shown in the table below
+
+Resource Type        | Count
+---------------------|------
+Lookup Tables (LUTs) | 4832
+Registers            | 4832
+18x18 Multipliers    | 9
+4KB SRAM Blocks      | 9
+GPIOs                | 864
+Max Clock Domains    | 1
+
+K6_N8_28x28_BD logic resources are organized into an 30x30 array of components.  A 28x28 array of logic blocks is surrounded on the perimeter by four banks of IOBs, one per side of the array.  Corner array locations are unused.
+
+## Logic Resources
+
+A brief description for K6_N8_28x28_BD logic resources is shown below
+
+### Configurable Logic Block (CLB)
+
+Each configurable logic block (CLB) consists of 8 6-input lookup-tables (LUTs).  The LUTs in a CLB share common inputs through local routing called a crossbar.  All LUT outputs are fed back to the crossbar so that they may be used as inputs within the CLB.  Each LUT output can be paired with a flip-flop (register) to synchronize the LUT output to a common clock.  Flip-flops not paired with a LUT can accept crossbar inputs directly.  All flip-flop usage is automatically determined as part of the RTL-to-bitstream flow and is thus transparent to the user.  
+
+### 18x18 Multiplier Block (DSP)
+
+To demonstrate hard arithmetic technology mapping, hard multipliers are offered.  The multipliers take two 18-bit inputs and produce a 36-bit output.  The block is fully combinational to keep the model as simple as possible.  The multipliers are modeled as occupying a 2x2 footprint within the 28x28 array of logic blocks.  This sizing is chosen for demonstration purposes and does not reflect the relative sizing of the multiplier to the CLB in any process technology.
+
+### SRAM Block (BRAM)
+
+A fixed size single port SRAM is provided to demonstrate memory technology mapping.  The memory macro is 4096x8 bits.  Each macro is modeled as occupying a 2x2 footprint within the 28x28 array of logic blocks.  This sizing is chosen for demonstration purposes and does not reflect the relative sizing of the SRAM to the CLB in any process technology.
+
+### I/O Block (IOB)
+
+General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the FPGA and reconfigurable logic.  Each IOB contains eight iopad primitives.  Each iopad primitive can operate either in input mode or output mode.  The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs.
+
+### Clocking
+
+This architecture uses an ideal clock model; clocks are modeled as globally distributed to all logic resources with zero delay.
+
+## K6_N8_28x28_BD Configuration
+
+K6_N8_28x28_BD bitstreams are generated using Logik.  An 8-bit wide interface is used to load a generated bitstream.
+

logiklib/demo/K6_N8_3x3/K6_N8_3x3.py

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+# Copyright 2024 Zero ASIC Corporation
+
+from logiklib import register_part_data
+
+from siliconcompiler import FPGA
+
+
+####################################################
+# Setup for K6_N8_3x3 FPGA
+####################################################
+def setup():
+    part_name = 'K6_N8_3x3'
+
+    fpga = FPGA(part_name, package=f"logik-fpga-{part_name}")
+
+    register_part_data(fpga, part_name, f"logik-fpga-{part_name}")
+
+    fpga.set('fpga', part_name, 'vendor', 'zeroasic')
+
+    fpga.set('fpga', part_name, 'var', 'vpr_device_code', 'K6_N8_3x3')
+
+    fpga.set('fpga', part_name, 'lutsize', 6)
+
+    fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'ideal')
+
+    fpga.set('fpga', part_name, 'file', 'archfile', 'cad/K6_N8_3x3.xml')
+    fpga.set('fpga', part_name, 'file', 'graphfile', 'cad/K6_N8_3x3_rr_graph.xml')
+
+    for tool in ('vpr', 'yosys'):
+        fpga.set('fpga', part_name, 'var', f'{tool}_registers', 'dff')
+
+    fpga.set('fpga', part_name, 'file', 'bitstream_map', 'cad/K6_N8_3x3_bitstream_map.json')
+
+    fpga.set('fpga', part_name, 'file', 'constraints_map', 'cad/K6_N8_3x3_constraint_map.json')
+
+    fpga.set('fpga', part_name, 'var', 'channelwidth', 40)
+
+    return fpga
+
+
+#########################
+if __name__ == "__main__":
+    fpga = setup()
+    assert fpga.check_filepaths()
+    fpga.write_manifest(f'{fpga.design}.json')

logiklib/demo/K6_N8_3x3/README.md

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+# K6_N8_3x3 FPGA Virtual Architecture
+
+The K6_N8_3x3 FPGA is a fixed-size virtual FPGA architecture consisting of configurable logic blocks (CLBs) and I/O blocks (IOBs).
+
+A summary of K6_N8_3x3 resources is shown in the table below
+
+Resource Type        | Count
+---------------------|------
+Lookup Tables (LUTs) | 72
+Registers            | 72
+GPIOs                | 96
+Max Clock Domains    | 1
+
+K6_N8_3x3 logic resources are organized into an 5x5 array of components.  A 3x3 array of CLBs is surrounded on the perimeter by four banks of IOBs, one per side of the array.  Corner array locations are unused.
+
+## Logic Resources
+
+A brief description for K6_N8_3x3 logic resources is shown below
+
+### Configurable Logic Block (CLB)
+
+Each configurable logic block (CLB) consists of 8 6-input lookup-tables (LUTs).  The LUTs in a CLB share common inputs through local routing called a crossbar.  All LUT outputs are fed back to the crossbar so that they may be used as inputs within the CLB.  Each LUT output can be paired with a flip-flop (register) to synchronize the LUT output to a common clock.  Flip-flops not paired with a LUT can accept crossbar inputs directly.  All flip-flop usage is automatically determined as part of the RTL-to-bitstream flow and is thus transparent to the user.  
+
+### I/O Block (IOB)
+
+General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the FPGA and reconfigurable logic.  Each IOB contains eight iopad primitives.  Each iopad primitive can operate either in input mode or output mode.  The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs.
+
+### Clocking
+
+This architecture uses an ideal clock model; clocks are modeled as globally distributed to all logic resources with zero delay.
+
+## K6_N8_3x3 Configuration
+
+K6_N8_3x3 bitstreams are generated using Logik.  An 8-bit wide interface is used to load a generated bitstream.
+

logiklib/demo/README.md

@@ -0,0 +1,2 @@
+
+# PLACE-HOLDER

logiklib/zeroasic/z1000/README.md

@@ -0,0 +1,96 @@
+# Z1000 eFPGA
+
+The Z1000 eFPGA is a fixed-size eFPGA architecture consisting of configurable logic blocks (CLBs), I/O blocks (IOBs), and a clock I/O block for clock distribution.
+
+## Z1000 Architecture
+
+A summary of Z1000 resources is shown in the table below
+
+Resource Type        | Count
+---------------------|------
+Lookup Tables (LUTs) | 2048
+Registers            | 2048
+GPIOs                | 1024
+Max Clock Domains    | 4
+
+The Z1000 architecture XML file provides a complete specification of how logic resources are arranged in this grid, the port lists of all logic resources, and how logic resources are organized and connected.  Hierarchical representations of logic blocks are provided where needed to enable correct, efficient packing and placement of a user's netlist.  The architecture XML also provides a delay model for the eFPGA and FASM feature metadata to enable logic block bitstream generation.  The Z1000 routing graph XML file encapsulates a complete model of the eFPGA interconnect architecture and contains the FASM feature metadata for interconnect bitstream generation.
+
+The following sections summarize the architecture features of Z1000.
+
+### Array and Grid Model
+
+Z1000 logic resources are organized into an 18x18 array of components, depicted in the figure below.  A 16x16 array of CLBs is surrounded on the perimeter by four banks of IOBs, one per side of the array.  Corner array locations are used for programmable interconnect only with the exception of the lower left corner, where the clock IOB is placed.
+
+![z1000_array_diagram](./docs/z1000_Block_Diagram.png )
+
+For modeling in VPR, this array of components is arranged on a 20x20 (X,Y) grid.  The lower left corner of Z1000 (the clock IOB) is located at (1,1) on this grid.  All locations at X=0, X=19, Y=0, and Y=19 are modeled as empty.  This perimeter of empty locations is required to model the architecture in VPR correctly.
+
+### Logic Resource Types
+
+Brief descriptions and block diagrams for Z1000 logic resources are shown below.
+
+#### Configurable Logic Block (CLB)
+
+Each configurable logic block (CLB) consists of 8 4-input basic logic elements (BLEs).  A block diagram of the BLE is shown below.  The BLE contains a 4-input lookup table (LUT) a configurable flip-flop, and a multiplexer that selects whether the primary output of the BLE comes from the flip-flop or directly from the LUT.  The flip-flop output is also routed out of the BLE as a secondary output; this secondary output is connected only to local interconnect in the CLB.
+
+![ble_block_diagram](./docs/BLE4_Block_Diagram.png )
+
+The BLEs in a CLB share 18 common inputs through the CLB local interconnect, an array of multiplexers referred to as the CLB crossbar.  Each BLE input is driven by a dedicated crossbar multiplexer that selects from a subset of the CLB inputs, BLE primary outputs, and BLE secondary outputs.  The CLB inputs are subdivided between north, south, east, and west sides of the CLB to improve their interface to the eFPGA global interconnect.  The BLE primary outputs are also outputs of the CLB and route directly to eFPGA global interconnect.  The overall CLB block diagram is shown below.  The BLE output feedback paths to the crossbar are not shown in the diagram to preserve diagram clarity.
+
+![clb_block_diagram](./docs/CLB4_Block_Diagram.png)
+
+#### I/O Block (IOB)
+
+General purpose I/O blocks (IOBs) are provided to provide a consistent signal interface between signals external to the eFPGA and reconfigurable logic.  Each IOB contains eight iopad primitives.  Each iopad primitive can operate either in input mode or output mode.  The IOB thus supports a maximum of eight user I/O signals in any combination of inputs and outputs.  During RTL-to-bitstream generation, each top level RTL port directly maps to an iopad primitives via pin constraints.
+
+The figure below shows a block diagram of the iopad primitive.  Each iopad enables a single signal to be connected .  The data direction is determined during bitstream generation and stored in a configuration bit that is directly wired to an output enable signal pad_oe that is accessible as a top level signal of the eFPGA.  When in input mode, the pad_in signal is received from external logic and passed to eFPGA logic via the inpad signal.  Similarly, in output mode the outpad signal is received from eFPGA logic and passed to pad_out.
+
+![iob_block_diagram](./docs/IOB_Block_Diagram.png)
+
+#### Clock I/O Block (Clock IOB)
+
+A dedicated I/O block is provided that is only used for delivering clocks to the programmable logic.  This I/O block is referred to as the clock IOB.  It is constructed from the same iopad primitive as the general purpose I/O blocks, but internally connected to the eFPGA clock network rather than to programmable interconnect.
+
+## Z1000 Pin Constraints
+
+Z1000 implements the signals in the table below as valid pin names for specifying pin constraints in a JSON pin constraints file (PCF).  Standard bus notatation using square brackets is required for all pins in the PCF.  For example, to constrain a user input signal `foo` to bit 17 of `gpio_in_east`, the following content should be included in the PCF file
+
+```
+  "foo": {
+    "direction": "input",
+    "pin": "gpio_in_east[17]"
+  },
+```
+
+> **_NOTE:_** User clock signals must be mapped to the gpio_in_clk bus
+
+Pin Name                  | Direction | MSB | LSB | Purpose
+--------------------------|-----------|-----|-----|---------
+gpio_in_clk               | input     | 3   | 0   | User clocks
+gpio_in_south             | input     | 255 | 0   | South side GPIO inputs
+gpio_in_north             | input     | 255 | 0   | North side GPIO inputs
+gpio_in_west              | input     | 255 | 0   | West side GPIO inputs
+gpio_in_east              | input     | 255 | 0   | East side GPIO inputs
+gpio_out_south            | output    | 255 | 0   | South side GPIO outputs
+gpio_oe_south             | output    | 255 | 0   | South side GPIO output enables
+gpio_out_north            | output    | 255 | 0   | North side GPIO outputs
+gpio_oe_north             | output    | 255 | 0   | North side GPIO output enables
+gpio_out_west             | output    | 255 | 0   | West side GPIO outputs
+gpio_oe_west              | output    | 255 | 0   | West side GPIO output enables
+gpio_out_east             | output    | 255 | 0   | East side GPIO outputs
+gpio_oe_east              | output    | 255 | 0   | East side GPIO output enables
+
+## Z1000 Bitstream Mapping
+
+The Z1000 bitstream format is organized into a four-dimensional array of configuration bits.  The four dimensions are the VPR grid X coordinate, VPR grid Y coordinate, word address, and bit index.
+
+The table below shows the minimum and maximum array values for this array.  Note that not all positions in the array contain valid configuration bits.
+
+Index       | Min  | Max |
+------------|------|-----|
+X           | 0    | 19  |
+Y           | 0    | 19  |
+Address     | 0    | 108 |
+Bit Index   | 0    | 7   |
+
+The Z1000 bitstream map file specifies a mapping from these array indices to each FASM feature defined in the Z1000 VPR architecture file and routing graph XML file.

logiklib/zeroasic/z1000/z1000.json

@@ -0,0 +1,15 @@
+{
+    "name": "z1000",
+    "fpga_x_size": 16,
+    "fpga_y_size": 16,
+    "num_routing_channels": 100,
+    "num_clb_inputs": 18,
+    "lut_size": 4,
+    "bles_per_clb": 8,
+    "outputs_per_ble": 1,
+    "crossbar_size": 15,
+    "sb_fraction": 0.15,
+    "logic_fraction": 0.15,
+    "ios_per_iob": 16,
+    "num_fracturable_elements": 1
+}

logiklib/zeroasic/z1000/z1000.py

@@ -0,0 +1,61 @@
+# Copyright 2025 Zero ASIC Corporation
+# Licensed under the Apache 2.0 License (see LICENSE for details)
+
+from logiklib import register_part_data
+
+from siliconcompiler import FPGA
+
+
+####################################################
+# Setup for z1000 FPGA
+####################################################
+def setup():
+    '''
+    z1000 is the first in a series of open FPGA architectures.
+    The baseline z1000 part is an architecture with 2K LUTs
+    and no hard macros.
+    '''
+
+    part_name = 'z1000'
+
+    fpga = FPGA(part_name, package=f"zeroasic-efpga-{part_name}")
+
+    register_part_data(fpga, part_name, f"zeroasic-efpga-{part_name}")
+
+    fpga.set('fpga', part_name, 'vendor', 'zeroasic')
+
+    # Set a variable for VPR to use to detect the correct <fixed_layout> section
+    # of the architecture XML file
+    fpga.set('fpga', part_name, 'var', 'vpr_device_code', part_name)
+
+    fpga.set('fpga', part_name, 'lutsize', 4)
+    fpga.set('fpga', part_name, 'var', 'feature_set', [
+        'async_reset', 'enable'])
+
+    fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'route')
+
+    fpga.set('fpga', part_name, 'file', 'archfile',  f'cad/{part_name}.xml')
+    fpga.set('fpga', part_name, 'file', 'graphfile', f'cad/{part_name}_rr_graph.xml')
+
+    for tool in ('vpr', 'yosys'):
+        fpga.set('fpga', part_name, 'var', f'{tool}_registers', [
+            'dff',
+            'dffr',
+            'dffe',
+            'dffer'])
+
+    fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'techlib/tech_flops.v')
+
+    fpga.set('fpga', part_name, 'file', 'bitstream_map', f'cad/{part_name}_bitstream_map.json')
+
+    fpga.set('fpga', part_name, 'file', 'constraints_map', f'cad/{part_name}_constraint_map.json')
+
+    fpga.set('fpga', part_name, 'var', 'channelwidth', 100)
+
+    return fpga
+
+
+#########################
+if __name__ == "__main__":
+    fpga = setup()
+    fpga.write_manifest(f'{fpga.design}.json')