lief 0.16.5__cp39-cp39-manylinux2014_aarch64.whl → 0.16.7__cp39-cp39-manylinux2014_aarch64.whl

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Files changed (30) hide show
  1. lief/ART/__init__.pyi +19 -18
  2. lief/DEX/__init__.pyi +159 -159
  3. lief/ELF/__init__.pyi +2393 -2393
  4. lief/MachO/__init__.pyi +1481 -1479
  5. lief/OAT/__init__.pyi +153 -150
  6. lief/PE/__init__.pyi +2153 -2153
  7. lief/VDEX/__init__.pyi +10 -8
  8. lief/__init__.pyi +268 -263
  9. lief/_lief.so +0 -0
  10. lief/assembly/aarch64/__init__.pyi +14 -14
  11. lief/assembly/aarch64/operands/__init__.pyi +5 -5
  12. lief/assembly/arm/__init__.pyi +5 -5
  13. lief/assembly/ebpf/__init__.pyi +5 -5
  14. lief/assembly/mips/__init__.pyi +5 -5
  15. lief/assembly/powerpc/__init__.pyi +5 -5
  16. lief/assembly/riscv/__init__.pyi +5 -5
  17. lief/assembly/x86/__init__.pyi +14 -14
  18. lief/assembly/x86/operands/__init__.pyi +5 -5
  19. lief/dsc/__init__.pyi +26 -24
  20. lief/dwarf/__init__.pyi +149 -148
  21. lief/dwarf/parameters/__init__.pyi +3 -3
  22. lief/dwarf/types/__init__.pyi +49 -49
  23. lief/logging/__init__.pyi +12 -12
  24. lief/objc/__init__.pyi +26 -26
  25. lief/pdb/__init__.pyi +44 -44
  26. lief/pdb/types/__init__.pyi +22 -22
  27. {lief-0.16.5.dist-info → lief-0.16.7.dist-info}/METADATA +1 -1
  28. lief-0.16.7.dist-info/RECORD +33 -0
  29. lief-0.16.5.dist-info/RECORD +0 -33
  30. {lief-0.16.5.dist-info → lief-0.16.7.dist-info}/WHEEL +0 -0
lief/assembly/aarch64/__init__.pyi CHANGED
@@ -2,16 +2,9 @@ import enum
2
2
  from typing import Iterator, Optional, Union
3
3
 
4
4
  from . import operands as operands
5
- import lief
5
+ import lief.assembly
6
6
 
7
7
 
8
- class Instruction(lief.assembly.Instruction):
9
- @property
10
- def opcode(self) -> OPCODE: ...
11
-
12
- @property
13
- def operands(self) -> Iterator[Optional[Operand]]: ...
14
-
15
8
  class OPCODE(enum.Enum):
16
9
  PHI = 0
17
10
 
@@ -16359,12 +16352,6 @@ class OPCODE(enum.Enum):
16359
16352
 
16360
16353
  INSTRUCTION_LIST_END = 8172
16361
16354
 
16362
- class Operand:
16363
- @property
16364
- def to_string(self) -> str: ...
16365
-
16366
- def __str__(self) -> str: ...
16367
-
16368
16355
  class REG(enum.Enum):
16369
16356
  NoRegister = 0
16370
16357
 
@@ -20198,3 +20185,16 @@ class SYSREG(enum.Enum):
20198
20185
  CPM_IOACC_CTL_EL3 = 65424
20199
20186
 
20200
20187
  NUM_TARGET_SYSREGS = 1213
20188
+
20189
+ class Instruction(lief.assembly.Instruction):
20190
+ @property
20191
+ def opcode(self) -> OPCODE: ...
20192
+
20193
+ @property
20194
+ def operands(self) -> Iterator[Optional[Operand]]: ...
20195
+
20196
+ class Operand:
20197
+ @property
20198
+ def to_string(self) -> str: ...
20199
+
20200
+ def __str__(self) -> str: ...
lief/assembly/aarch64/operands/__init__.pyi CHANGED
@@ -2,13 +2,17 @@ import enum
2
2
  import lief.assembly.aarch64
3
3
  from typing import Iterator, Optional, Union
4
4
 
5
- import lief
5
+ import lief.assembly.aarch64
6
6
 
7
7
 
8
8
  class Immediate(lief.assembly.aarch64.Operand):
9
9
  @property
10
10
  def value(self) -> int: ...
11
11
 
12
+ class Register(lief.assembly.aarch64.Operand):
13
+ @property
14
+ def value(self) -> Optional[Union[lief.assembly.aarch64.REG, lief.assembly.aarch64.SYSREG]]: ...
15
+
12
16
  class Memory(lief.assembly.aarch64.Operand):
13
17
  class SHIFT(enum.Enum):
14
18
  UNKNOWN = 0
@@ -42,7 +46,3 @@ class Memory(lief.assembly.aarch64.Operand):
42
46
  class PCRelative(lief.assembly.aarch64.Operand):
43
47
  @property
44
48
  def value(self) -> int: ...
45
-
46
- class Register(lief.assembly.aarch64.Operand):
47
- @property
48
- def value(self) -> Optional[Union[lief.assembly.aarch64.REG, lief.assembly.aarch64.SYSREG]]: ...
lief/assembly/arm/__init__.pyi CHANGED
@@ -1,13 +1,9 @@
1
1
  import enum
2
2
  from typing import Iterator, Optional, Union
3
3
 
4
- import lief
4
+ import lief.assembly
5
5
 
6
6
 
7
- class Instruction(lief.assembly.Instruction):
8
- @property
9
- def opcode(self) -> OPCODE: ...
10
-
11
7
  class OPCODE(enum.Enum):
12
8
  PHI = 0
13
9
 
@@ -9002,3 +8998,7 @@ class OPCODE(enum.Enum):
9002
8998
  t__brkdiv0 = 4495
9003
8999
 
9004
9000
  INSTRUCTION_LIST_END = 4496
9001
+
9002
+ class Instruction(lief.assembly.Instruction):
9003
+ @property
9004
+ def opcode(self) -> OPCODE: ...
lief/assembly/ebpf/__init__.pyi CHANGED
@@ -1,13 +1,9 @@
1
1
  import enum
2
2
  from typing import Iterator, Optional, Union
3
3
 
4
- import lief
4
+ import lief.assembly
5
5
 
6
6
 
7
- class Instruction(lief.assembly.Instruction):
8
- @property
9
- def opcode(self) -> OPCODE: ...
10
-
11
7
  class OPCODE(enum.Enum):
12
8
  PHI = 0
13
9
 
@@ -982,3 +978,7 @@ class OPCODE(enum.Enum):
982
978
  XXORW32 = 485
983
979
 
984
980
  INSTRUCTION_LIST_END = 486
981
+
982
+ class Instruction(lief.assembly.Instruction):
983
+ @property
984
+ def opcode(self) -> OPCODE: ...
lief/assembly/mips/__init__.pyi CHANGED
@@ -1,13 +1,9 @@
1
1
  import enum
2
2
  from typing import Iterator, Optional, Union
3
3
 
4
- import lief
4
+ import lief.assembly
5
5
 
6
6
 
7
- class Instruction(lief.assembly.Instruction):
8
- @property
9
- def opcode(self) -> OPCODE: ...
10
-
11
7
  class OPCODE(enum.Enum):
12
8
  PHI = 0
13
9
 
@@ -5796,3 +5792,7 @@ class OPCODE(enum.Enum):
5796
5792
  YIELD = 2892
5797
5793
 
5798
5794
  INSTRUCTION_LIST_END = 2893
5795
+
5796
+ class Instruction(lief.assembly.Instruction):
5797
+ @property
5798
+ def opcode(self) -> OPCODE: ...
lief/assembly/powerpc/__init__.pyi CHANGED
@@ -1,13 +1,9 @@
1
1
  import enum
2
2
  from typing import Iterator, Optional, Union
3
3
 
4
- import lief
4
+ import lief.assembly
5
5
 
6
6
 
7
- class Instruction(lief.assembly.Instruction):
8
- @property
9
- def opcode(self) -> OPCODE: ...
10
-
11
7
  class OPCODE(enum.Enum):
12
8
  PHI = 0
13
9
 
@@ -5712,3 +5708,7 @@ class OPCODE(enum.Enum):
5712
5708
  gBCat = 2866
5713
5709
 
5714
5710
  INSTRUCTION_LIST_END = 2867
5711
+
5712
+ class Instruction(lief.assembly.Instruction):
5713
+ @property
5714
+ def opcode(self) -> OPCODE: ...
lief/assembly/riscv/__init__.pyi CHANGED
@@ -1,13 +1,9 @@
1
1
  import enum
2
2
  from typing import Iterator, Optional, Union
3
3
 
4
- import lief
4
+ import lief.assembly
5
5
 
6
6
 
7
- class Instruction(lief.assembly.Instruction):
8
- @property
9
- def opcode(self) -> OPCODE: ...
10
-
11
7
  class OPCODE(enum.Enum):
12
8
  PHI = 0
13
9
 
@@ -27672,3 +27668,7 @@ class OPCODE(enum.Enum):
27672
27668
  ZIP_RV32 = 13830
27673
27669
 
27674
27670
  INSTRUCTION_LIST_END = 13831
27671
+
27672
+ class Instruction(lief.assembly.Instruction):
27673
+ @property
27674
+ def opcode(self) -> OPCODE: ...
lief/assembly/x86/__init__.pyi CHANGED
@@ -2,16 +2,9 @@ import enum
2
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  from typing import Iterator, Optional, Union
3
3
 
4
4
  from . import operands as operands
5
- import lief
5
+ import lief.assembly
6
6
 
7
7
 
8
- class Instruction(lief.assembly.Instruction):
9
- @property
10
- def operands(self) -> Iterator[Optional[Operand]]: ...
11
-
12
- @property
13
- def opcode(self) -> OPCODE: ...
14
-
15
8
  class OPCODE(enum.Enum):
16
9
  PHI = 0
17
10
 
@@ -39649,12 +39642,6 @@ class OPCODE(enum.Enum):
39649
39642
 
39650
39643
  INSTRUCTION_LIST_END = 19817
39651
39644
 
39652
- class Operand:
39653
- @property
39654
- def to_string(self) -> str: ...
39655
-
39656
- def __str__(self) -> str: ...
39657
-
39658
39645
  class REG(enum.Enum):
39659
39646
  NoRegister = 0
39660
39647
 
@@ -40431,3 +40418,16 @@ class REG(enum.Enum):
40431
40418
  R31WH = 387
40432
40419
 
40433
40420
  NUM_TARGET_REGS = 388
40421
+
40422
+ class Instruction(lief.assembly.Instruction):
40423
+ @property
40424
+ def operands(self) -> Iterator[Optional[Operand]]: ...
40425
+
40426
+ @property
40427
+ def opcode(self) -> OPCODE: ...
40428
+
40429
+ class Operand:
40430
+ @property
40431
+ def to_string(self) -> str: ...
40432
+
40433
+ def __str__(self) -> str: ...
lief/assembly/x86/operands/__init__.pyi CHANGED
@@ -1,12 +1,16 @@
1
1
  from typing import Iterator, Optional, Union
2
2
 
3
- import lief
3
+ import lief.assembly.x86
4
4
 
5
5
 
6
6
  class Immediate(lief.assembly.x86.Operand):
7
7
  @property
8
8
  def value(self) -> int: ...
9
9
 
10
+ class Register(lief.assembly.x86.Operand):
11
+ @property
12
+ def value(self) -> lief.assembly.x86.REG: ...
13
+
10
14
  class Memory(lief.assembly.x86.Operand):
11
15
  @property
12
16
  def base(self) -> lief.assembly.x86.REG: ...
@@ -26,7 +30,3 @@ class Memory(lief.assembly.x86.Operand):
26
30
  class PCRelative(lief.assembly.x86.Operand):
27
31
  @property
28
32
  def value(self) -> int: ...
29
-
30
- class Register(lief.assembly.x86.Operand):
31
- @property
32
- def value(self) -> lief.assembly.x86.REG: ...
lief/dsc/__init__.pyi CHANGED
@@ -4,8 +4,16 @@ import os
4
4
  from typing import Iterator, Optional, Union, overload
5
5
 
6
6
  import lief
7
+ import lief.MachO
8
+ import lief.assembly
7
9
 
8
10
 
11
+ @overload
12
+ def enable_cache() -> bool: ...
13
+
14
+ @overload
15
+ def enable_cache(target_cache_dir: str) -> bool: ...
16
+
9
17
  class DyldSharedCache:
10
18
  class VERSION(enum.Enum):
11
19
  UNKNOWN = 0
@@ -142,6 +150,12 @@ class DyldSharedCache:
142
150
 
143
151
  def flush_cache(self) -> None: ...
144
152
 
153
+ @overload
154
+ def load(files: Sequence[str]) -> Optional[DyldSharedCache]: ...
155
+
156
+ @overload
157
+ def load(path: os.PathLike, arch: str = '') -> Optional[DyldSharedCache]: ...
158
+
145
159
  class Dylib:
146
160
  class extract_opt_t:
147
161
  def __init__(self) -> None: ...
@@ -175,46 +189,34 @@ class Dylib:
175
189
 
176
190
  def get(self, opt: Dylib.extract_opt_t = ...) -> Optional[lief.MachO.Binary]: ...
177
191
 
178
- class MappingInfo:
192
+ class SubCache:
179
193
  @property
180
- def address(self) -> int: ...
194
+ def uuid(self) -> list[int]: ...
181
195
 
182
196
  @property
183
- def size(self) -> int: ...
197
+ def vm_offset(self) -> int: ...
184
198
 
185
199
  @property
186
- def end_address(self) -> int: ...
200
+ def suffix(self) -> str: ...
187
201
 
188
202
  @property
189
- def file_offset(self) -> int: ...
203
+ def cache(self) -> Optional[DyldSharedCache]: ...
190
204
 
205
+ class MappingInfo:
191
206
  @property
192
- def max_prot(self) -> int: ...
207
+ def address(self) -> int: ...
193
208
 
194
209
  @property
195
- def init_prot(self) -> int: ...
210
+ def size(self) -> int: ...
196
211
 
197
- class SubCache:
198
212
  @property
199
- def uuid(self) -> list[int]: ...
213
+ def end_address(self) -> int: ...
200
214
 
201
215
  @property
202
- def vm_offset(self) -> int: ...
216
+ def file_offset(self) -> int: ...
203
217
 
204
218
  @property
205
- def suffix(self) -> str: ...
219
+ def max_prot(self) -> int: ...
206
220
 
207
221
  @property
208
- def cache(self) -> Optional[DyldSharedCache]: ...
209
-
210
- @overload
211
- def enable_cache() -> bool: ...
212
-
213
- @overload
214
- def enable_cache(target_cache_dir: str) -> bool: ...
215
-
216
- @overload
217
- def load(files: Sequence[str]) -> Optional[DyldSharedCache]: ...
218
-
219
- @overload
220
- def load(path: os.PathLike, arch: str = '') -> Optional[DyldSharedCache]: ...
222
+ def init_prot(self) -> int: ...