librelane 3.1.0.dev3__py3-none-any.whl → 3.1.0.dev4__py3-none-any.whl

librelane/common/__init__.py

@@ -33,6 +33,7 @@ from .misc import (
     get_librelane_root,
     get_script_dir,
     get_pdk_hash,
+    get_ciel_pdk_hash,
     slugify,
     protected,
     final,

librelane/common/misc.py

@@ -40,6 +40,7 @@ from typing import (
 )
 
 import httpx
+from deprecated.sphinx import deprecated
 
 from ..__version__ import __version__
 from .types import AnyPath, Path
@@ -75,6 +76,11 @@ def get_script_dir() -> str:
     )
 
 
+@deprecated(
+    version="3.1.0",
+    reason="Use get_ciel_pdk_hash, this method can force an exit in some codepaths",
+    action="once",
+)
 def get_pdk_hash(pdk_variant) -> str:
     """
     Gets the PDK version hash confirmed compatible with this version of LibreLane.
@@ -92,6 +98,27 @@ def get_pdk_hash(pdk_variant) -> str:
     exit(1)
 
 
+def get_ciel_pdk_hash(pdk_variant: str) -> str:
+    """
+    Gets the PDK version hash confirmed compatible with this version of LibreLane.
+
+    Requires ciel
+    """
+    import ciel
+
+    with open(os.path.join(get_librelane_root(), "pdk_hashes.yaml"), "r") as file:
+        pdk_hashes = yaml.safe_load(file)
+
+    pdk_family = ciel.resolve_pdk_family(pdk_variant)
+
+    if pdk_family not in pdk_hashes:
+        raise ValueError(
+            f"LibreLane does not have a validated version for Ciel PDK family {pdk_family}."
+        )
+
+    return pdk_hashes[pdk_family]
+
+
 # The following code snippet has been adapted under the following license:
 #
 # Copyright (c) Django Software Foundation and individual contributors.

librelane/common/toolbox.py

@@ -367,6 +367,11 @@ class Toolbox(object):
             warn(f"Failed to generate preview: {e}.")
             return None
 
+    @deprecated(
+        version="3.1.0",
+        reason="No longer needed by internal LibreLane steps and will be removed in LibreLane 4.0.",
+        action="once",
+    )
     def remove_cells_from_lib(
         self,
         input_lib_files: FrozenSet[str],

librelane/config/__init__.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane 2
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");

librelane/config/__main__.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane 2
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");

librelane/config/config.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane 2
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -815,7 +819,7 @@ class Config(GenericImmutableDict[str, Any]):
             try:
                 import ciel
 
-                pdk_root = ciel.get_ciel_home(pdk_root)
+                pdk_root = str(ciel.get_ciel_home(pdk_root))
             except ImportError:
                 raise ValueError(
                     "The pdk_root argument is required as Ciel is not installed."

librelane/config/flow.py

@@ -1,6 +1,6 @@
 # Copyright 2025 LibreLane Contributors
 #
-# Adapted from OpenLane
+# Adapted from OpenLane 2
 #
 # Copyright 2023 Efabless Corporation
 #

librelane/config/pdk_compat.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane 2
+#
 # Copyright 2023-2025 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -350,4 +354,20 @@ def migrate_old_config(config: Mapping[str, Any]) -> Dict[str, Any]:
         if "HEURISTIC_ANTENNA_THRESHOLD" not in config:
             new["HEURISTIC_ANTENNA_THRESHOLD"] = 130
 
+    # x7. KLAYOUT_DRC_OPTIONS to defines
+    if new["PDK"].startswith("sky130") and "KLAYOUT_DRC_OPTIONS" in new:
+        tcl_dict = new["KLAYOUT_DRC_OPTIONS"]
+        ws_rx = re.compile(r"\s+")
+        del new["KLAYOUT_DRC_OPTIONS"]
+        new["KLAYOUT_DRC_DEFINES"] = {}
+        # deliberately not checking for bad dicts or dicts that require quoting
+        # it's already overkill to assume people modified the PDK files here
+        #
+        # if someone complains we can parse a Tcl dict later
+        tcl_dict_entries = ws_rx.split(tcl_dict)
+        while len(tcl_dict_entries):
+            key = tcl_dict_entries.pop(0)
+            value = tcl_dict_entries.pop(0)
+            new["KLAYOUT_DRC_DEFINES"][key] = value
+
     return new

librelane/config/preprocessor.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane 2
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");

librelane/config/removals.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane 2
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");

librelane/config/variable.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane 2
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");

librelane/flows/cli.py

@@ -43,7 +43,7 @@ from cloup.constraints import (
 from cloup.typing import Decorator
 
 from .flow import Flow
-from ..common import set_tpe, cli, get_pdk_hash, _get_process_limit
+from ..common import set_tpe, cli, get_ciel_pdk_hash, _get_process_limit
 from ..logging import set_log_level, verbose, err, options, LogLevels
 from ..state import State, InvalidState
 
@@ -517,8 +517,7 @@ def cloup_flow_opts(
                     import ciel
                     from ciel.source import StaticWebDataSource
 
-                    opdks_rev = volare_pdk_override or get_pdk_hash(pdk)
-                    ciel_home = ciel.get_ciel_home(pdk_root)
+                    ciel_home = str(ciel.get_ciel_home(pdk_root))
 
                     include_libraries = ["default"]
                     if scl is not None:
@@ -527,32 +526,35 @@ def cloup_flow_opts(
                     if pad is not None:
                         include_libraries.append(pad)
 
-                    pdk_family = None
-                    if family := ciel.Family.by_name.get(pdk):
-                        pdk = family.default_variant
-                        pdk_family = family.name
-                        verbose(f"Resolved PDK variant {family.default_variant}.")
-                    else:
-                        for family in ciel.Family.by_name.values():
-                            if pdk in family.variants:
-                                pdk_family = family.name
-                                break
-
-                    if pdk_family is None:
-                        err(f"Could not resolve the PDK '{pdk}'.")
+                    selector = pdk
+
+                    try:
+                        pdk = ciel.resolve_pdk_variant(pdk)
+                        if pdk != selector:
+                            verbose(f"Resolved PDK variant {pdk}.")
+                    except ValueError as e:
+                        err(str(e))
+                        err("If you're using a non-Ciel PDK, please pass --manual-pdk.")
+                        exit(1)
+
+                    try:
+                        opdks_rev = volare_pdk_override or get_ciel_pdk_hash(pdk)
+                    except ValueError as e:
+                        err(str(e))
+                        err("Please specify a PDK manually with '--manual-pdk'.")
                         exit(1)
 
                     try:
                         version = ciel.fetch(
                             ciel_home,
-                            pdk_family,
+                            pdk,  # only pull default libraries for resolved variant since we have a message saying "Resolved variant {pdk}..."
                             opdks_rev,
                             data_source=StaticWebDataSource(
                                 "https://fossi-foundation.github.io/ciel-releases"
                             ),
                             include_libraries=include_libraries,
                         )
-                        pdk_root = version.get_dir(ciel_home)
+                        pdk_root = str(version.get_dir(ciel_home))
                     except ValueError as e:
                         err(f"Failed to download PDK: {e}")
                         exit(1)

librelane/flows/synth_explore.py

@@ -79,6 +79,7 @@ class SynthesisExploration(Flow):
         options.set_condensed_mode(True)
 
         for strategy in [
+            "DEFAULT",
             "AREA 0",
             "AREA 1",
             "AREA 2",

librelane/pdk_hashes.yaml

@@ -1,3 +1,4 @@
-sky130: 74c0e6b118a67d94c24172143d3bd597473fa63d
-gf180mcu: f6eeac7dad085ffcc829ccfd721f7b4ce39edcf7
-ihp-sg13g2: ee974c3adc69d0f36adbf20577079f0df419d702
+sky130: 792ef67037d74c8c51811eab3ce23cf793491296
+gf180mcu: 792ef67037d74c8c51811eab3ce23cf793491296
+ihp-sg13: 89d42ee6d2fd9b50b86a1aada6fee6673c3e6008
+freepdk45: 784b1a483a5f4de362d6f3629378de1199453f3c

librelane/scripts/odbpy/check_antenna_properties.py

@@ -65,7 +65,7 @@ def check_cells(odb_cells):
         }
         report.append(entry)
 
-        return report
+    return report
 
 
 def get_top_level_cell(input_lefs, design_lef, cell_name):

librelane/scripts/odbpy/defutil.py

@@ -562,7 +562,10 @@ def remove_obstructions(reader, input_lefs, obstructions):
             if (odb_layer, odb_bbox) == (layer, bbox):
                 print(f"Removing obstruction on {layer} at {bbox} (DBU)…")
                 found = True
-                odb.dbObstruction_destroy(odb_obj)
+                if not odb_obj.isSystemReserved():
+                    odb.dbObstruction_destroy(odb_obj)
+                else:
+                    print("[WARNING] Obstruction is system-reserved.")
             if found:
                 break
         if not found:

librelane/scripts/openroad/common/io.tcl

@@ -19,11 +19,23 @@ source $::env(_TCL_ENV_IN)
 source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
 
 namespace eval lln {
+    proc scene_name {scene} {
+        # OpenSTA >= 3.1 (commit 998806cb, 2026-06-30) bridges scenes as SWIG
+        # objects instead of strings. Older OpenSTA 3 bridges them as strings,
+        # in which case the value already is the name.
+        if { [sta::is_object $scene] } {
+            return [sta::get_property $scene name]
+        }
+        return $scene
+    }
     proc get_corner_names {} {
         # returns: names as a Tcl list, compatible with both OpenSTA 2 and 3
         if {[string length [namespace which sta::scenes]] != 0} {
-            # scenes are bridged as a list of strings
-            return [sta::scenes]
+            set result [list]
+            foreach scene [sta::scenes] {
+                lappend result [scene_name $scene]
+            }
+            return $result
         } else {
             # corners are not bridged as strings
             set result [list]
@@ -36,12 +48,14 @@ namespace eval lln {
     proc get_corner_dict {} {
         # returns: Tcl dictionary from corner names to whatever object is
         # interpreted as a corner for internal commands that expect corners:
-        # - in OpenSTA 3, that's the scene's name again
+        # - in OpenSTA 3, that's whatever sta::find_scene returns (a name in
+        #   OpenSTA 3.0, a Scene object since 3.1)
         # - in OpenSTA 2, that's an opaque Tcl pointer
         set result [dict create]
         if {[string length [namespace which sta::scenes]] != 0} {
             foreach scene [sta::scenes] {
-                dict set result $scene $scene
+                set name [scene_name $scene]
+                dict set result $name [sta::find_scene $name]
             }
         } else {
             foreach corner [sta::corners] {
@@ -52,7 +66,11 @@ namespace eval lln {
     }
 
     proc set_sta_cmd_corner {corner_name} {
-        if {[string length [namespace which sta::set_cmd_scene]] != 0} {
+        # sta::set_scene takes a name in every OpenSTA 3; sta::set_cmd_scene
+        # takes a name before 998806cb and a Scene object after.
+        if {[string length [namespace which sta::set_scene]] != 0} {
+            sta::set_scene $corner_name
+        } elseif {[string length [namespace which sta::set_cmd_scene]] != 0} {
             sta::set_cmd_scene $corner_name
         } else {
             set corner_object [sta::find_corner $corner_name]

librelane/scripts/openroad/repair_design.tcl

@@ -49,11 +49,11 @@ lappend arg_list -verbose
 lappend arg_list -max_wire_length $::env(DESIGN_REPAIR_MAX_WIRE_LENGTH)
 lappend arg_list -slew_margin $::env(DESIGN_REPAIR_MAX_SLEW_PCT)
 lappend arg_list -cap_margin $::env(DESIGN_REPAIR_MAX_CAP_PCT)
-if { [info exists ::env(DESIGN_REPAIR_MAX_UTILIZATION)] } {
+if { $::env(DESIGN_REPAIR_MAX_UTILIZATION) > 0 } {
     lappend arg_list -max_utilization $::env(DESIGN_REPAIR_MAX_UTILIZATION)
 }
-if { [info exists ::env(DESIGN_REPAIR_BUFFER_GAIN)] } {
-    lappend arg_list -buffer_gain $::env(DESIGN_REPAIR_BUFFER_GAIN)
+if { $::env(DESIGN_REPAIR_PRE_PLACEMENT) } {
+    lappend arg_list -pre_placement
 }
 # Repair Design
 log_cmd repair_design {*}$arg_list

librelane/scripts/openroad/repair_design_postgrt.tcl

@@ -36,12 +36,9 @@ lappend arg_list -verbose
 lappend arg_list -max_wire_length $::env(GRT_DESIGN_REPAIR_MAX_WIRE_LENGTH)
 lappend arg_list -slew_margin $::env(GRT_DESIGN_REPAIR_MAX_SLEW_PCT)
 lappend arg_list -cap_margin $::env(GRT_DESIGN_REPAIR_MAX_CAP_PCT)
-if { [info exists ::env(GRT_DESIGN_REPAIR_MAX_UTILIZATION)] } {
+if { $::env(GRT_DESIGN_REPAIR_MAX_UTILIZATION) > 0 } {
     lappend arg_list -max_utilization $::env(GRT_DESIGN_REPAIR_MAX_UTILIZATION)
 }
-if { [info exists ::env(GRT_DESIGN_REPAIR_BUFFER_GAIN)] } {
-    lappend arg_list -buffer_gain $::env(GRT_DESIGN_REPAIR_BUFFER_GAIN)
-}
 log_cmd repair_design {*}$arg_list
 
 # Re-DPL and GRT

librelane/scripts/pyosys/synthesize.py

@@ -257,6 +257,10 @@ def synthesize(
     config = json.load(open(config_in))
     extra = json.load(open(extra_in))
 
+    lib_dont_use_args = []
+    for excluded_cell in extra["excluded_cell_patterns"]:
+        lib_dont_use_args.extend(("-dont_use", excluded_cell))
+
     includes = config.get("VERILOG_INCLUDE_DIRS") or []
     defines = (
         (config.get("VERILOG_DEFINES") or [])
@@ -288,7 +292,7 @@ def synthesize(
     # https://github.com/YosysHQ/abc/blob/28d955ca97a1c4be3aed4062aec0241a734fac5d/src/map/scl/sclUtil.c#L257
     sdc_path = os.path.join(step_dir, "synthesis.abc.sdc")
     with open(sdc_path, "w") as f:
-        print(f"set_driving_cell {config['SYNTH_DRIVING_CELL']}", file=f)
+        print(f"set_driving_cell {config['SYNTH_DRIVING_CELL'].split('/')[0]}", file=f)
         print(f"set_load {config['OUTPUT_CAP_LOAD']}", file=f)
 
     ys.log(f"[INFO] Using SDC file '{sdc_path}' for ABC…")
@@ -434,6 +438,7 @@ def synthesize(
         cg_min_width = config["SYNTH_CLOCKGATE_MIN_WIDTH"]
         posedge = ()
         negedge = ()
+        tie_lo = ()
         if posedge_raw := config["SYNTH_CLOCKGATE_POSEDGE_ICG"]:
             cell, ce, clk, gclk = posedge_raw.rsplit("/", maxsplit=4)
             posedge = ("-pos", cell, f"{ce}:{clk}:{gclk}")
@@ -444,18 +449,21 @@ def synthesize(
             ys.log(
                 "[WARNING] A minimum width for clock gating is set; but no ICGs are configured."
             )
+        if tie_lo_raw := config["SYNTH_CLOCKGATE_TIE_LO"]:
+            tie_lo = ("-tie_lo", tie_lo_raw)
         d.run_pass(
             "clockgate",
             "-min_net_size",
             str(cg_min_width),
             *posedge,
             *negedge,
+            *tie_lo,
         )
 
     dfflibmap_args = []
     for lib in libs:
         dfflibmap_args.extend(["-liberty", lib])
-    d.run_pass("dfflibmap", *dfflibmap_args)
+    d.run_pass("dfflibmap", *dfflibmap_args, *lib_dont_use_args)
 
     d.tee("stat", "-json", *lib_arguments, o=os.path.join(report_dir, "post_dff.json"))
     d.tee("stat", *lib_arguments, o=os.path.join(report_dir, "post_dff.rpt"))
@@ -465,24 +473,35 @@ def synthesize(
     def run_strategy(d):
         abc_script = config["SYNTH_ABC_STRATEGY_SCRIPT"]
         if abc_script:
-            ys.log(f"[INFO] Using custom ABC strategy script '{abc_script}'…")
-        else:
-            abc_script = script_creator.generate_abc_script(
-                step_dir,
-                config["SYNTH_STRATEGY"],
-            )
-            ys.log(f"[INFO] Using generated ABC strategy script '{abc_script}'…")
-
-        d.run_pass(
-            "abc",
-            "-script",
-            abc_script,
+            ys.log(f"[INFO] Using custom ABC strategy script '{abc_script}'…\n")
+        elif config["SYNTH_STRATEGY"] != "DEFAULT":
+            if config["SYNTH_ABC_NEW"]:
+                ys.log(
+                    "[WARN] Using Yosys-provided synthesis strategy for experimental abc_new pass: use SYNTH_ABC_STRATEGY_SCRIPT to provide your own synthesis scripts."
+                )
+            else:
+                abc_script = script_creator.generate_abc_script(
+                    step_dir,
+                    config["SYNTH_STRATEGY"],
+                )
+                ys.log(f"[INFO] Using generated ABC strategy script '{abc_script}'…\n")
+        ys.log_flush()
+
+        extra_args = ["-script", abc_script] * bool(abc_script)
+        if not config["SYNTH_ABC_NEW"]:
+            extra_args += ["-showtmp"]
+            if config["SYNTH_ABC_DFF"]:
+                extra_args += ["-dff"]
+
+        abc_pass = [
+            "abc_new" if config["SYNTH_ABC_NEW"] else "abc",
             "-constr",
             sdc_path,
-            "-showtmp",
             *lib_arguments,
-            *(["-dff"] if config["SYNTH_ABC_DFF"] else []),
-        )
+            *extra_args,
+            *lib_dont_use_args,
+        ]
+        d.run_pass(*abc_pass)
 
         if value := config.get("SYNTH_TIE_UNDEFINED"):
             flag = "-zero" if value == "low" else "-one"

librelane/scripts/pyosys/ys_common.py

@@ -18,6 +18,7 @@
 import os
 import re
 import sys
+import shlex
 from typing import Iterable, List, Optional, Tuple, Union
 
 try:
@@ -64,6 +65,9 @@ def yosys_version_at_least(*target: Tuple[int, ...]) -> Tuple[int, int]:
 
 
 def _Design_run_pass(self, *command):
+    if pass_dump := os.getenv("_LIBRELANE_YOSYS_DUMP_PASSES_TO"):
+        with open(pass_dump, "a+", encoding="utf8") as f:
+            print(shlex.join(command), file=f)
     ys.Pass.call(self, command)
 
 
@@ -151,6 +155,8 @@ def _Design_add_blackbox_models(
                 "-sv",
                 "-setattr",
                 "keep_hierarchy",
+                "-setattr",
+                "blackbox",
                 "-lib",
                 *include_args,
                 *define_args,
@@ -165,6 +171,7 @@ def _Design_add_blackbox_models(
                 "blackbox",
                 "-setattr",
                 "keep_hierarchy",
+                "-unit_delay",
                 model,
             )
         else:

librelane/steps/klayout.py

@@ -459,10 +459,13 @@ class DRC(KLayoutStep):
             deprecated_names=["KLAYOUT_DRC_TECH_SCRIPT"],
         ),
         Variable(
-            "KLAYOUT_DRC_OPTIONS",
-            Optional[Dict[str, Union[int, bool, str]]],
+            "KLAYOUT_DRC_DEFINES",
+            Optional[Dict[str, str]],
             "Options passed directly to the KLayout DRC runset. They vary from one PDK to another.",
             pdk=True,
+            deprecated_names=[
+                ("KLAYOUT_DRC_OPTIONS", lambda x: {k: str(v) for k, v in x.items()})
+            ],
         ),
         Variable(
             "KLAYOUT_DRC_THREADS",
@@ -505,8 +508,8 @@ class DRC(KLayoutStep):
         assert isinstance(input_view, Path)
 
         opts = []
-        if self.config["KLAYOUT_DRC_OPTIONS"]:
-            for k, v in self.config["KLAYOUT_DRC_OPTIONS"].items():
+        if self.config["KLAYOUT_DRC_DEFINES"]:
+            for k, v in self.config["KLAYOUT_DRC_DEFINES"].items():
                 opts.extend(
                     [
                         "-rd",
@@ -566,13 +569,13 @@ class DRC(KLayoutStep):
         drc_script_path = self.config["KLAYOUT_DRC_RUNSET"]
         lyrdb_report = os.path.join(reports_dir, "drc.klayout.lyrdb")
         json_report = os.path.join(reports_dir, "drc.klayout.json")
-        feol = str(self.config["KLAYOUT_DRC_OPTIONS"]["feol"]).lower()
-        beol = str(self.config["KLAYOUT_DRC_OPTIONS"]["beol"]).lower()
+        feol = str(self.config["KLAYOUT_DRC_DEFINES"]["feol"]).lower()
+        beol = str(self.config["KLAYOUT_DRC_DEFINES"]["beol"]).lower()
         floating_metal = str(
-            self.config["KLAYOUT_DRC_OPTIONS"]["floating_metal"]
+            self.config["KLAYOUT_DRC_DEFINES"]["floating_metal"]
         ).lower()
-        offgrid = str(self.config["KLAYOUT_DRC_OPTIONS"]["offgrid"]).lower()
-        seal = str(self.config["KLAYOUT_DRC_OPTIONS"]["seal"]).lower()
+        offgrid = str(self.config["KLAYOUT_DRC_DEFINES"]["offgrid"]).lower()
+        seal = str(self.config["KLAYOUT_DRC_DEFINES"]["seal"]).lower()
         threads = self.config["KLAYOUT_DRC_THREADS"] or _get_process_limit()
         info(f"Running KLayout DRC with {threads} threads…")
 
@@ -648,8 +651,8 @@ class DRC(KLayoutStep):
         assert isinstance(input_view, Path)
 
         opts = []
-        if self.config["KLAYOUT_DRC_OPTIONS"]:
-            for k, v in self.config["KLAYOUT_DRC_OPTIONS"].items():
+        if self.config["KLAYOUT_DRC_DEFINES"]:
+            for k, v in self.config["KLAYOUT_DRC_DEFINES"].items():
                 opts.extend(
                     [
                         "-rd",
@@ -717,8 +720,8 @@ class DRC(KLayoutStep):
         assert isinstance(input_view, Path)
 
         opts = []
-        if self.config["KLAYOUT_DRC_OPTIONS"]:
-            for k, v in self.config["KLAYOUT_DRC_OPTIONS"].items():
+        if self.config["KLAYOUT_DRC_DEFINES"]:
+            for k, v in self.config["KLAYOUT_DRC_DEFINES"].items():
                 opts.extend(
                     [
                         "-rd",
@@ -1037,10 +1040,16 @@ class Filler(KLayoutStep):
             pdk=True,
         ),
         Variable(
-            "KLAYOUT_FILLER_OPTIONS",
-            Optional[Dict[str, Union[bool, int, str]]],
-            "Options passed directly to the KLayout filler script. They vary from one PDK to another.",
+            "KLAYOUT_FILLER_DEFINES",
+            Optional[Dict[str, str]],
+            "Options passed directly to the KLayout filler runset. They vary from one PDK to another.",
             pdk=True,
+            deprecated_names=[
+                (
+                    "KLAYOUT_FILLER_OPTIONS",
+                    lambda x: {k: str(v) for k, v in (x or {}).items()},
+                )
+            ],
         ),
     ]
 
@@ -1076,8 +1085,8 @@ class Filler(KLayoutStep):
         script = self.config["KLAYOUT_FILLER_SCRIPT"]
 
         opts = []
-        if self.config["KLAYOUT_FILLER_OPTIONS"]:
-            for k, v in self.config["KLAYOUT_FILLER_OPTIONS"].items():
+        if self.config["KLAYOUT_FILLER_DEFINES"]:
+            for k, v in self.config["KLAYOUT_FILLER_DEFINES"].items():
                 opts.extend(
                     [
                         "-rd",
@@ -1119,6 +1128,16 @@ class Filler(KLayoutStep):
 
         script = self.config["KLAYOUT_FILLER_SCRIPT"]
 
+        opts = []
+        if self.config["KLAYOUT_FILLER_DEFINES"]:
+            for k, v in self.config["KLAYOUT_FILLER_DEFINES"].items():
+                opts.extend(
+                    [
+                        "-rd",
+                        f"{k}={v}",
+                    ]
+                )
+
         env["PDK_ROOT"] = self.config["PDK_ROOT"]
         env["PDK"] = self.config["PDK"]
 
@@ -1132,6 +1151,7 @@ class Filler(KLayoutStep):
                 "-rd",
                 f"output_file={abspath(output_gds)}",
                 abspath(input_gds),
+                *opts,
             ],
             env=env,
         )
@@ -1161,10 +1181,16 @@ class Density(KLayoutStep):
             pdk=True,
         ),
         Variable(
-            "KLAYOUT_DENSITY_OPTIONS",
-            Optional[Dict[str, Union[bool, int, str]]],
+            "KLAYOUT_DENSITY_DEFINES",
+            Optional[Dict[str, str]],
             "Options passed directly to the KLayout density runset. They vary from one PDK to another.",
             pdk=True,
+            deprecated_names=[
+                (
+                    "KLAYOUT_DENSITY_OPTIONS",
+                    lambda x: {k: str(v) for k, v in (x or {}).items()},
+                )
+            ],
         ),
         Variable(
             "KLAYOUT_DENSITY_THREADS",
@@ -1202,8 +1228,8 @@ class Density(KLayoutStep):
         json_report = os.path.join(reports_dir, "density.klayout.json")
 
         opts = []
-        if self.config["KLAYOUT_DENSITY_OPTIONS"]:
-            for k, v in self.config["KLAYOUT_DENSITY_OPTIONS"].items():
+        if self.config["KLAYOUT_DENSITY_DEFINES"]:
+            for k, v in self.config["KLAYOUT_DENSITY_DEFINES"].items():
                 opts.extend(
                     [
                         "-rd",
@@ -1279,10 +1305,16 @@ class Antenna(KLayoutStep):
             pdk=True,
         ),
         Variable(
-            "KLAYOUT_ANTENNA_OPTIONS",
-            Optional[Dict[str, Union[bool, int, str]]],
-            "Options passed directly to the KLayout density runset. They vary from one PDK to another.",
+            "KLAYOUT_ANTENNA_DEFINES",
+            Optional[Dict[str, str]],
+            "Options passed directly to the KLayout antenna runset. They vary from one PDK to another.",
             pdk=True,
+            deprecated_names=[
+                (
+                    "KLAYOUT_ANTENNA_OPTIONS",
+                    lambda x: {k: str(v) for k, v in (x or {}).items()},
+                )
+            ],
         ),
     ]
 
@@ -1314,8 +1346,8 @@ class Antenna(KLayoutStep):
         json_report = os.path.join(reports_dir, "antenna.klayout.json")
 
         opts = []
-        if self.config["KLAYOUT_ANTENNA_OPTIONS"]:
-            for k, v in self.config["KLAYOUT_ANTENNA_OPTIONS"].items():
+        if self.config["KLAYOUT_ANTENNA_DEFINES"]:
+            for k, v in self.config["KLAYOUT_ANTENNA_DEFINES"].items():
                 opts.extend(
                     [
                         "-rd",

librelane/steps/openroad.py

@@ -516,7 +516,7 @@ class OpenROADStep(TclStep):
 
     def get_command(self) -> List[str]:
         metrics_path = os.path.join(self.step_dir, "or_metrics_out.json")
-        threads = str(self.config["OPENROAD_THREADS"]) or str(_get_process_limit())
+        threads = str(self.config["OPENROAD_THREADS"] or _get_process_limit())
         verbose(f"OpenROAD will use {threads} threads")
         return [
             self.get_openroad_path(),
@@ -2667,6 +2667,19 @@ class RepairDesignPostGPL(ResizerStep):
             "Invokes OpenROAD's remove_buffers command to remove buffers from synthesis, which gives OpenROAD more flexibility when buffering nets.",
             default=False,
         ),
+        Variable(
+            "DESIGN_REPAIR_MAX_UTILIZATION",
+            Decimal,
+            "Defines the percentage of core area used.",
+            units="%",
+            default=0,
+        ),
+        Variable(
+            "DESIGN_REPAIR_PRE_PLACEMENT",
+            bool,
+            "Enables performing an initial pre-placement sizing and buffering round.",
+            default=False,
+        ),
     ]
 
     def get_script_path(self):
@@ -2723,6 +2736,13 @@ class RepairDesignPostGRT(ResizerStep):
             units="%",
             deprecated_names=["GLB_RESIZER_MAX_CAP_MARGIN"],
         ),
+        Variable(
+            "GRT_DESIGN_REPAIR_MAX_UTILIZATION",
+            Decimal,
+            "Defines the percentage of core area used during post-grt repair.",
+            units="%",
+            default=0,
+        ),
     ]
 
     def get_script_path(self):

librelane/steps/pyosys.py

@@ -214,6 +214,12 @@ class PyosysStep(Step):
             pdk=True,
             validator=_validate_icg,
         ),
+        Variable(
+            "SYNTH_CLOCKGATE_TIE_LO",
+            Optional[str],
+            "Port of the integrated clock gate cell to be tied to zero. Intended for DFT scan-enable pins.",
+            pdk=True,
+        ),
         Variable(
             "YOSYS_LOG_LEVEL",
             Literal["ALL", "WARNING", "ERROR"],
@@ -268,7 +274,7 @@ class PyosysStep(Step):
         env["PYTHONPATH"] = ":".join(
             (env.get("PYTHONPATH", ""), os.path.join(get_script_dir(), "pyosys"))
         )
-        subprocess_result = super().run_subprocess(cmd, env=env, **kwargs)
+        subprocess_result = self.run_subprocess(cmd, env=env, **kwargs)
         return {}, subprocess_result["generated_metrics"]
 
 
@@ -287,6 +293,11 @@ class VerilogStep(PyosysStep):
         pad_lib_list = self.toolbox.filter_views(
             self.config, self.config["PAD_LIBS"], self.config.get("SYNTH_CORNER")
         )
+        pad_lib_list = []
+        if pad_libs := self.config.get("PAD_LIBS"):
+            pad_lib_list = self.toolbox.filter_views(
+                self.config, pad_libs, self.config.get("SYNTH_CORNER")
+            )
 
         # Try your best to use powered blackbox models if power_defines is true
         if self.power_defines:
@@ -338,19 +349,27 @@ class VerilogStep(PyosysStep):
         if models := self.config.get("EXTRA_VERILOG_MODELS"):
             blackbox_models.extend(str(f) for f in models)
 
-        excluded_cells: Set[str] = set(self.config["EXTRA_EXCLUDED_CELLS"] or [])
-        excluded_cells.update(
+        excluded_cell_patterns: Set[str] = set(
+            self.config["EXTRA_EXCLUDED_CELLS"] or []
+        )
+        excluded_cell_patterns.update(
             process_list_file(self.config["SYNTH_EXCLUDED_CELL_FILE"])
         )
-        excluded_cells.update(process_list_file(self.config["PNR_EXCLUDED_CELL_FILE"]))
-
-        libs_synth = self.toolbox.remove_cells_from_lib(
-            frozenset([str(lib) for lib in scl_lib_list + pad_lib_list]),
-            excluded_cells=frozenset(excluded_cells),
+        excluded_cell_patterns.update(
+            process_list_file(self.config["PNR_EXCLUDED_CELL_FILE"])
         )
+
+        libs_synth = [str(p) for p in scl_lib_list + pad_lib_list]
         extra_path = os.path.join(self.step_dir, "extra.json")
         with open(extra_path, "w") as f:
-            json.dump({"blackbox_models": blackbox_models, "libs_synth": libs_synth}, f)
+            json.dump(
+                {
+                    "blackbox_models": blackbox_models,
+                    "libs_synth": libs_synth,
+                    "excluded_cell_patterns": list(excluded_cell_patterns),
+                },
+                f,
+            )
         cmd.extend(["--extra-in", extra_path])
         return cmd
 
@@ -411,9 +430,27 @@ class SynthesisCommon(VerilogStep):
             "Generates names for netlist instances. This results in instance names that can be extremely long, but are more human-readable.",
             default=False,
         ),
+        Variable(
+            "SYNTH_ABC_NEW",
+            bool,
+            "Experimental: Use the abc_new pass instead of abc, with the default synthesis strategy from Yosys.",
+            default=False,
+        ),
+        Variable(
+            "SYNTH_ABC_DFF",
+            bool,
+            "Passes D-flipflop cells through ABC for optimization (which can for example, eliminate identical flip-flops). Has no effect if SYNTH_ABC_NEW is true.",
+            default=False,
+        ),
+        Variable(
+            "SYNTH_ABC_STRATEGY_SCRIPT",
+            Optional[Path],
+            "Custom ABC strategy script, overriding the script generated by the SYNTH_STRATEGY.",
+        ),
         Variable(
             "SYNTH_STRATEGY",
             Literal[
+                "DEFAULT",
                 "AREA 0",
                 "AREA 1",
                 "AREA 2",
@@ -424,51 +461,40 @@ class SynthesisCommon(VerilogStep):
                 "DELAY 3",
                 "DELAY 4",
             ],
-            "Strategies for abc logic synthesis and technology mapping. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them.",
-            default="AREA 0",
+            "Strategies for abc logic synthesis and technology mapping. DEFAULT uses whichever script Yosys applies by default. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them. Has no effect if SYNTH_ABC_STRATEGY_SCRIPT is set. While marked experimental, SYNTH_ABC_NEW will always use DEFAULT.",
+            default="DELAY 4",
         ),
         Variable(
             "SYNTH_ABC_BUFFERING",
             bool,
-            "Enables `abc` cell buffering.",
+            "Enables `abc` cell buffering. Has no effect if either SYNTH_ABC_NEW is true or SYNTH_ABC_STRATEGY_SCRIPT is set.",
             default=False,
             deprecated_names=["SYNTH_BUFFERING"],
         ),
         Variable(
             "SYNTH_ABC_LEGACY_REFACTOR",
             bool,
-            "Replaces the ABC command `drf -l` with `refactor` which matches older versions of LibreLane but is more unstable.",
+            "Replaces the ABC command `drf -l` with `refactor` which matches older versions of LibreLane but is more unstable. Has no effect if either SYNTH_ABC_NEW is true or SYNTH_ABC_STRATEGY_SCRIPT is set.",
             default=False,
         ),
         Variable(
             "SYNTH_ABC_LEGACY_REWRITE",
             bool,
-            "Replaces the ABC command `drw -l` with `rewrite` which matches older versions of LibreLane but is more unstable.",
-            default=False,
-        ),
-        Variable(
-            "SYNTH_ABC_DFF",
-            bool,
-            "Passes D-flipflop cells through ABC for optimization (which can for example, eliminate identical flip-flops).",
+            "Replaces the ABC command `drw -l` with `rewrite` which matches older versions of LibreLane but is more unstable. Has no effect if either SYNTH_ABC_NEW is true or SYNTH_ABC_STRATEGY_SCRIPT is set.",
             default=False,
         ),
         Variable(
             "SYNTH_ABC_USE_MFS3",
             bool,
-            "Experimental: attempts a SAT-based remapping in all area and delay strategies before 'retime', which may improve PPA results.",
+            "Experimental: attempts a SAT-based remapping in all area and delay strategies before 'retime', which may improve PPA results. Has no effect if either SYNTH_ABC_NEW is true or SYNTH_ABC_STRATEGY_SCRIPT is set.",
             default=False,
         ),
         Variable(
             "SYNTH_ABC_AREA_USE_NF",
             bool,
-            "Experimental: uses the &nf delay-based mapper with a very high value instead of the amap area mapper, which may be better in some scenarios at recovering area.",
+            "Experimental: uses the &nf delay-based mapper with a very high value instead of the amap area mapper, which may be better in some scenarios at recovering area. Has no effect if  either SYNTH_ABC_NEW is true or SYNTH_ABC_STRATEGY_SCRIPT is set.",
             default=False,
         ),
-        Variable(
-            "SYNTH_ABC_STRATEGY_SCRIPT",
-            Optional[Path],
-            "Custom ABC strategy script. Runs instead of the default script for the selected 'SYNTH_STRATEGY'. All other 'SYNTH_ABC_*' variables except 'SYNTH_ABC_DFF' will have no effect.",
-        ),
         Variable(
             "SYNTH_DIRECT_WIRE_BUFFERING",
             bool,
@@ -610,17 +636,19 @@ class SynthesisCommon(VerilogStep):
         ]
         metric_updates["design__instance_unmapped__count"] = sum(unmapped_cells)
 
-        check_error_count_file = os.path.join(
-            self.step_dir, "reports", "pre_synth_chk.rpt"
-        )
+        check_report_files = [
+            os.path.join(self.step_dir, "reports", "pre_synth_chk.rpt"),
+            os.path.join(self.step_dir, "reports", "chk.rpt"),
+        ]
         metric_updates["synthesis__check_error__count"] = 0
-        if os.path.exists(check_error_count_file):
-            metric_updates["synthesis__check_error__count"] = _parse_yosys_check(
-                open(check_error_count_file),
-                self.config["TRISTATE_CELLS"],
-                self.config["SYNTH_CHECKS_ALLOW_TRISTATE"],
-                self.config["SYNTH_ELABORATE_ONLY"],
-            )
+        for check_error_count_file in check_report_files:
+            if os.path.exists(check_error_count_file):
+                metric_updates["synthesis__check_error__count"] += _parse_yosys_check(
+                    open(check_error_count_file),
+                    self.config["TRISTATE_CELLS"],
+                    self.config["SYNTH_CHECKS_ALLOW_TRISTATE"],
+                    self.config["SYNTH_ELABORATE_ONLY"],
+                )
 
         view_updates[DesignFormat.NETLIST] = Path(out_file)
 

librelane/steps/step.py

@@ -313,7 +313,7 @@ class ProcessStatsThread(Thread):
                     time.sleep(self.interval)
                     status = self.process.status()
         except psutil.Error as e:
-            message = e.msg
+            message = str(e)
             for normal in ["process no longer exists", "but it's a zombie"]:
                 if normal in message:
                     return

librelane/steps/verilator.py

@@ -165,7 +165,7 @@ class Lint(Step):
                     model_set.add(str_model)
                     model_list.append(str_model)
         defines = [
-            f"PDK_{self.config['PDK']}",
+            f"PDK_{self.config['PDK']}.replace('-','_')",
             f"SCL_{self.config['STD_CELL_LIBRARY']}",
             "__librelane__",
             "__pnr__",

{librelane-3.1.0.dev3.dist-info → librelane-3.1.0.dev4.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: librelane
-Version: 3.1.0.dev3
+Version: 3.1.0.dev4
 Summary: An infrastructure for implementing chip design flows
 License-Expression: Apache-2.0
 Maintainer: Mohamed Gaber
@@ -12,7 +12,8 @@ Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3.13
 Classifier: Programming Language :: Python :: 3.14
-Requires-Dist: ciel (>=2.3.1,<3)
+Classifier: Programming Language :: Python :: 3.15
+Requires-Dist: ciel (>=3.2.0,<4)
 Requires-Dist: click (>=8,<8.4)
 Requires-Dist: cloup (>=3.0.5,<4)
 Requires-Dist: deprecated (>=1.2.10,<2)

{librelane-3.1.0.dev3.dist-info → librelane-3.1.0.dev4.dist-info}/RECORD

@@ -1,7 +1,7 @@
 librelane/__init__.py,sha256=Xbz6e-J9pNxv0AIi89-mApMEQQtRgxJyzHS6yYc00Y0,1221
 librelane/__main__.py,sha256=QLV5xjX9p_xXltrb9JgXkvG9gC6G3oxMfM6vOvrY138,14904
 librelane/__version__.py,sha256=TRnK0R8jG4P_eiX1VVShHpLWZljMLwhDggTIYW1lBSk,1598
-librelane/common/__init__.py,sha256=fK52kxuueEpKI1HNNhUOJFQ4yvxJs0f0Vz1a5S-CBGY,1569
+librelane/common/__init__.py,sha256=wrVBpwXBQTVRy7COwWulyTHwnV2Rx5nh2gWNMVEf06w,1592
 librelane/common/cli.py,sha256=XeNFI1B-lM-luGJfCVa88wUl9Q5S4btEwzXTAui1xYU,2413
 librelane/common/drc.py,sha256=ujwGdwQoq8aXBwpJNn2r-o808iUfj8IJx2SglBzw5YU,12853
 librelane/common/generic_dict.py,sha256=ASa5wtVcLuGlsBqGfLxLYXrYksqQB62iHljV04plIqI,10010
@@ -11,20 +11,20 @@ librelane/common/metrics/compare.py,sha256=dPJmtcDKQpMUEqQBx4eynJddCNxAA0_zwvJ0u
 librelane/common/metrics/library.py,sha256=CG7rubLdjuCQL9-9bzAC-64hf-KlH-iu_Fg0oKuesqs,7373
 librelane/common/metrics/metric.py,sha256=h3Xd26z5M80IJgVmmrBTjKcdGLb4I0wyjM-H4jdyi_0,6990
 librelane/common/metrics/util.py,sha256=Bl_9znlot7-Os2VigYLSmMf56aAkGdv3evWz9vfK7K4,9344
-librelane/common/misc.py,sha256=Jry0rW7VzCgrmHGmX4F6hKvNefa9rmWj8_ZMxnrlpQE,14836
+librelane/common/misc.py,sha256=lMJcMt0Vp8jXrqzQxsglz5tLKjPjodMHUr7r76Amas0,15584
 librelane/common/ring_buffer.py,sha256=DGFen9y0JOmiL7E27tmzDTVSJKZtV-waF9hl5Rz9uek,1898
 librelane/common/tcl.py,sha256=kq09m9dj-RK7uvvduAgxHMCf0xjzMRS9IPcrhQFl-Xc,4350
-librelane/common/toolbox.py,sha256=VPjZ_8D2oUiubwZw112F8J-gUbsnBSGlxQeZlCf5fRM,21211
+librelane/common/toolbox.py,sha256=-fIOD9yjLEB4KFF30e7r3iPRfAmJMjL5Yx_hY5YSI7o,21383
 librelane/common/tpe.py,sha256=Txj0fVscXSDJTYmEKZ2ESFHOeqrhHnaPPiwWBgyx4g8,1285
 librelane/common/types.py,sha256=yFzUWnfnwrzhOz06uh45oHY8un0kDk4CJR5B32TbQDw,3950
-librelane/config/__init__.py,sha256=lbJmD5CbrrrnaNdIUWqFIK488ea0uyej3iExh-9mkgE,1107
-librelane/config/__main__.py,sha256=NsJGoIOb950mdXql1zmzSq10wuFovK9NGWm011NNJ3A,4474
-librelane/config/config.py,sha256=pAT6LqTiCVQykUQiJXYSmBimHDWcbha9IF-XTJ48f58,36928
-librelane/config/flow.py,sha256=mBZkBuQOvke9Xf8OQuTvGmJSX72UfQ5xI0ycTbNm-dc,18618
-librelane/config/pdk_compat.py,sha256=35tgW_vrn5kxPVUaA8vlnJ77mkHKvJlvYiYUrjV4k9s,13992
-librelane/config/preprocessor.py,sha256=0SNRaPTAwABi3vkvCzcchqTqkuTGjFOIVZRiQHdAFkU,14521
-librelane/config/removals.py,sha256=57jRLJ8505IsNbyr68iAyHBFEyIloq7DQUPw4L3iisc,3173
-librelane/config/variable.py,sha256=yfnco9zux0dZ74wp0-ObZyUEnwIdEHIOVCuJHj-9noc,35322
+librelane/config/__init__.py,sha256=xDSlMiZsjAwdfsGErJPjsY2pfa5vbazRiNcKNJ2udf8,1177
+librelane/config/__main__.py,sha256=iGva_Hv3zQ4OnV-Y9POgcDl1Fkz4RYZcfa2G9zroLuk,4544
+librelane/config/config.py,sha256=v_NWe6BVKvMAEiSaWklILsiL1QOyz60R8du-4X9Kj2A,37003
+librelane/config/flow.py,sha256=9uV_KWu8jigcmN8YHEJokJIHxAvbz-y0uFlR6ACo_Fw,18620
+librelane/config/pdk_compat.py,sha256=qCj6TXiTssHRbzjKB6faqnpUytctSDrqBpdGc2Ue8qg,14789
+librelane/config/preprocessor.py,sha256=n3IrZUWxgodkl54B43XggT_lChItRPEmTKkNZeOGSfs,14591
+librelane/config/removals.py,sha256=Fjf0GHxJGVMUKyKg-oH083OEqKjl3A3O06nMi8n9nt8,3243
+librelane/config/variable.py,sha256=hN-cBCArBkIRYAvp-AawO7HlsddU4hQX9gSLkoPfKfk,35392
 librelane/container.py,sha256=GN1lqVguuqPAuTxINii-bWKBKmIQ-VJc0WHPDEp73sU,8829
 librelane/env_info.py,sha256=xF9iqwwJv5yZz7n7BTrrT_yP3Dp1HjAOUObNE9k_1g4,11074
 librelane/examples/hold_eco_demo/config.yaml,sha256=InDj4pS6o6TpyvQZyR3qCrYcIHdmCd6l04wqanKnK_A,490
@@ -46,16 +46,16 @@ librelane/flows/__init__.py,sha256=ghtmUG-taVpHJ3CKJRYZGn3dU0r93araT1EIGlBEsxg,8
 librelane/flows/builtins.py,sha256=4UbeOySaHSO8KTaTV0d__bl4ugjPtOe0NpSosdLYj_E,796
 librelane/flows/chip.py,sha256=fxmScni4ErJRSlhRy4Wyr-HaOdyjEfOn2BxBVQmkhmk,1795
 librelane/flows/classic.py,sha256=24hwOEk7CzPe-PYxdUjHpH7ykspvzc-0P19FmKmiyu0,10995
-librelane/flows/cli.py,sha256=k1EchdOx8G4UW0bscb8dSeQDnAfNvV4yGV66cdlOOJQ,20559
+librelane/flows/cli.py,sha256=osgT-XD02HxNoO_LjorA0sIyZPY2W-aFdVAMyMKkc18,20668
 librelane/flows/flow.py,sha256=_zZfS3LvYG0GdzBJftWY-7-EPIHxeh_UnEaNAaC3ucQ,36911
 librelane/flows/misc.py,sha256=32Om3isexesfKKiJZCajNmINc-xdv7eVx_tgoh9SR6U,2015
 librelane/flows/optimizing.py,sha256=OwZz6WGmXpliwO8vtmhjKHD-kzDyNv-zoCECZIigXsI,6076
 librelane/flows/sequential.py,sha256=C5TIlWxlJh0oZ-6iCbA7Uq7-iqJkvNy6-LBPQb0TigY,15361
-librelane/flows/synth_explore.py,sha256=brLxVFg1VOczN_U8DqYtYkRZWFdUHqZKYjX3mf_t_es,8629
+librelane/flows/synth_explore.py,sha256=MIIIX-bFpCoe1p9pi9aB4kz8Gxpmh81qMKGRDeSp6M8,8652
 librelane/help/__main__.py,sha256=gnm0yi-Ih8YoyY2cMiHONV2ZzR-tvHfdEHCb28YQJZ0,1243
 librelane/logging/__init__.py,sha256=mrTnzjpH6AOu2CiDZYfOMCVByAS2Xeg9HS4FJyXsJOE,1043
 librelane/logging/logger.py,sha256=kA61TGsR00Fi6kQSxgTC1pHpS_-zqC1PdQnYqnk2TWY,8632
-librelane/pdk_hashes.yaml,sha256=Q1IGbbc3VvPLwZ5IKBDtaqsC3hRLC_-gKudB0f59ii4,153
+librelane/pdk_hashes.yaml,sha256=iS3gQ7RxEHTmT7mf9bteHkBXGqI5Kh7qyE_PaQnN8ZE,203
 librelane/plugins.py,sha256=G5o2h1LT4a1LO1Q0gKXXuhqcEdjdTFkYU8QUSg2D2eM,820
 librelane/py.typed,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 librelane/scripts/base.sdc,sha256=NMjzMcNm21Gnjtig0qe7rDtsHP4Cd6BMasqbpJSOf3g,3149
@@ -87,9 +87,9 @@ librelane/scripts/magic/wrapper.tcl,sha256=qO33N2AiEYBTABMB5vWMWWEd2FpyOhg8JlcGs
 librelane/scripts/netgen/setup.tcl,sha256=_NfZUGFeSxFzanm32r0ytipSYg6JXVjC3oPdIgYj7NY,1281
 librelane/scripts/odbpy/apply_def_template.py,sha256=Tn6y65biu0bAQ6XilYxq5jn3a_KqjTl423-aXWI864k,1534
 librelane/scripts/odbpy/cell_frequency.py,sha256=NfGgM8wxIvjM1C_GHUghZPOh8gpdasLOWR4qBdHHLFE,3105
-librelane/scripts/odbpy/check_antenna_properties.py,sha256=D8Hb1nzNurOzNekCZ2n2x1D-ycGTjSe9leI7qcZZHXY,3942
+librelane/scripts/odbpy/check_antenna_properties.py,sha256=qDoR-f_9SNwwhZgAFVYcm45zf_UALxUocdkT3Dv2n6o,3938
 librelane/scripts/odbpy/contextualize.py,sha256=G8EEgmK6ISikXD2-Pw-RTs1JxLWPnuppwL7oPfAsb84,4020
-librelane/scripts/odbpy/defutil.py,sha256=gBANy_XTeLeXRBMGdCy2vI5y44qMB6E_Fy0VeyW6rUg,18104
+librelane/scripts/odbpy/defutil.py,sha256=YzxP_0ePGLAVGxUvszTmfP1tArRuMx8K447emOU1lrQ,18252
 librelane/scripts/odbpy/diodes.py,sha256=qpsTW2RQlqNm4pzrUFm7d0Jj4x4zSQqladcv5SJF7XI,11752
 librelane/scripts/odbpy/disconnected_pins.py,sha256=hS_Iletg7N6K6yN_ccvWxZ3nWNZp4ecUJM-oY0kkEfA,11139
 librelane/scripts/odbpy/eco_buffer.py,sha256=lb7KtVZUzXSkPq9mRTXPVnSo_isy4845wohLFPhDN30,6292
@@ -113,7 +113,7 @@ librelane/scripts/openroad/buffer_list.tcl,sha256=sXygy1KRSUS4dZi1UOpBkGGOuXRVLM
 librelane/scripts/openroad/common/dpl.tcl,sha256=T_rzoZy8i7S9C92TOmiN79w0MCfudafEhkXcHmB1BAM,920
 librelane/scripts/openroad/common/dpl_cell_pad.tcl,sha256=KWVuj8u1-y3ZUiQr48TAsFv1GSzOCVnAjdqfBjtoQxQ,1066
 librelane/scripts/openroad/common/grt.tcl,sha256=VbZORyX7DljoylaUXyhY5vDIjAoYMlLGgrY_ZnXiJoE,1111
-librelane/scripts/openroad/common/io.tcl,sha256=x7KDIvCFPHxuvmB2pFTAuvPZfMYZTAkx6ue_F6RCuA8,25369
+librelane/scripts/openroad/common/io.tcl,sha256=twqHM6KiagkJviINgyDXjiKhPLQYqGLB7winDaKYX-Q,26208
 librelane/scripts/openroad/common/pad_cfg.tcl,sha256=2WMNEwWJUZq3UQsTVJBDJfZE5dDdVKkYQ6b-_3iDO5g,10643
 librelane/scripts/openroad/common/pdn_cfg.tcl,sha256=ovCfiwTD-ft6OXksI9hwgZZ6ynwQohC79HIU88fHvf4,6354
 librelane/scripts/openroad/common/resizer.tcl,sha256=OhjpVxw_8IOx5Bmh2_gh_EIHxKaX84NS37Of9Rlchpw,2255
@@ -138,8 +138,8 @@ librelane/scripts/openroad/irdrop.tcl,sha256=bXhNY_87xPV-ocF9v8wOWqjlnFPaVO_6K_D
 librelane/scripts/openroad/pad.tcl,sha256=ZEFhUfGDfWm-eNp-HkB_Q82jkdPNsK8vTN4QKzlxIaI,801
 librelane/scripts/openroad/pdn.tcl,sha256=WiKVmLw3g_ZN1Hs4iiAzc6Qah7ZwCn6o-OA5iNmlTtY,1566
 librelane/scripts/openroad/rcx.tcl,sha256=kyEhli4sGFMEj-He9UXZDGb0Tmxlw7d6iZD7t6adUx8,1057
-librelane/scripts/openroad/repair_design.tcl,sha256=ojwbIgUHShUFEzQtTfv6gq365ExPgpXbRSuMOK9xKm0,2575
-librelane/scripts/openroad/repair_design_postgrt.tcl,sha256=sEXdFfH2le-q0ggcsWGgCR-GCFyzPdxk4P3RZyWCnpI,1902
+librelane/scripts/openroad/repair_design.tcl,sha256=wG1owFuh5iriSUR7hd8ehCHOoq4i5DeFpOfQlsjhco8,2523
+librelane/scripts/openroad/repair_design_postgrt.tcl,sha256=utJS58-WRWZN5j4mNXjzJJv5UzqFpSAwT7wdbBulN5k,1759
 librelane/scripts/openroad/rsz_timing_postcts.tcl,sha256=ztDJ__R7f3eK7-xAg9SklGXqL5F1jydGPQDH7X5twNE,2553
 librelane/scripts/openroad/rsz_timing_postgrt.tcl,sha256=F6ex9Ke85YzS4z9rf8SpqCKjMyzuiQEhYYSJfkN93sM,2699
 librelane/scripts/openroad/sta/check_macro_instances.tcl,sha256=YpHleMNIWHqQLLEl1HZlimphxyMRqUT4l09XBIeH14M,1783
@@ -150,8 +150,8 @@ librelane/scripts/openroad/write_cdl.tcl,sha256=pp-l-7JkuwpdtR1bypIVI_PKCOGCoUOD
 librelane/scripts/openroad/write_views.tcl,sha256=-MxTJsB4EF7l5trDaZe-VBFjhfzqRt8F5_DZrADTs0U,892
 librelane/scripts/pyosys/construct_abc_script.py,sha256=x_of9UOxxme-lFWlnZ75-W6I-UAWm-wJy8odnQ1alPE,6830
 librelane/scripts/pyosys/json_header.py,sha256=LSoDHLMKch3tUwsjrps2HdF6PJZ3ydxM8NZHf3z0Bz4,2525
-librelane/scripts/pyosys/synthesize.py,sha256=DvlKpYu1_xvv6Q1AVhyCEL82CzxZI65eGERxwjqFEow,19226
-librelane/scripts/pyosys/ys_common.py,sha256=My9m1mtHfgbEjeMqvOARplgYsTJQBoQMEf7gLAD0Nf8,5221
+librelane/scripts/pyosys/synthesize.py,sha256=86n8dWQiAs9gIH-jGb0ow38skmZ-FSe0-dnU-S1vCkU,20130
+librelane/scripts/pyosys/ys_common.py,sha256=lhyA8k1DCM59RTvRkyFxxt1oBP19sp2vl_WCL8GpCSs,5492
 librelane/scripts/tclsh/hello.tcl,sha256=kkR3akY7QnGHYXsQODYwLkMkUEOgWcNFtzaMTTEV2bY,34
 librelane/state/__init__.py,sha256=DZ_RyKMr2oj4p5d32u8MmDKfCxR7OEdDw-1HWKTpatA,949
 librelane/state/__main__.py,sha256=Ici4Ejg1ICUZNSYZRguC3BfEk_wFxsmE0ag0Vv8iY1I,1679
@@ -161,19 +161,19 @@ librelane/steps/__init__.py,sha256=j3JYrdnWM74dYuEvE931oSrQI7FUz-hKWr8Mts8C0wg,1
 librelane/steps/__main__.py,sha256=7TaEmJGiphnIqEbAALyThNQPNlelXeJRHg114P6DZ4M,13463
 librelane/steps/checker.py,sha256=CxGshm_2K1-zFTso-aPZNFuu-Y9hdSv5KkjumN6pbLY,22655
 librelane/steps/common_variables.py,sha256=tTEVB9bnZ8AnufEVZUGS6fnpQWfpyyBVK_Eax5DVD64,14990
-librelane/steps/klayout.py,sha256=aHfKqd66pLPCUV5WXbsDtBYXQz_kGFuBW2oH7VMgwrc,45863
+librelane/steps/klayout.py,sha256=lVZwzGYWDpzoJMOAlKy8yHGV5BltXW1jz9FhfK5rrpo,46848
 librelane/steps/magic.py,sha256=GS2TzOzf3XZuYIzz5P3CQ3T_QHb47YTMaTbA9-ggb0M,28044
 librelane/steps/misc.py,sha256=3O-6V3QPnqsYACoogg9I7SrJ7C0VMQbtA0anF13wa7w,5806
 librelane/steps/netgen.py,sha256=tfHaY2ItpmmbKhSuduPvGmMw8Rqb7O1sLpXEDKSVEXg,9454
 librelane/steps/odb.py,sha256=Nrk37F33-qKz-pcCYAWvWkOlSHiLMwSqpeYldx33v1Q,40772
-librelane/steps/openroad.py,sha256=50p9YWgOTscAoa5rnKLGFIuX0_jG1nDbSxLFfsZbBNs,111028
+librelane/steps/openroad.py,sha256=EIhmk6y_OwLwq2piJW09ZOLnsNSXeavMRaUrVxjICu8,111650
 librelane/steps/openroad_alerts.py,sha256=IJyB4piBDCKXhkJswHGMYCRDwbdQsR0GZlrGGDhmW6Q,3364
-librelane/steps/pyosys.py,sha256=ktRxe8PgenS-kmxsgxaCZr9tCIxL3CB5m412K0cJGkw,26328
-librelane/steps/step.py,sha256=gtr8xlNv4J4m4maqO6V1R0YPK_IpX6g_6X6Mk-_Oklc,55539
+librelane/steps/pyosys.py,sha256=Omx4XBPol-MrINw2u4Qwl14t1uV5rXQOoHOpgAMuOcY,27819
+librelane/steps/step.py,sha256=FCVcFiFQyHqjoQC3QA3Yc_x4MeDfj2k--caAxQJi4OI,55540
 librelane/steps/tclstep.py,sha256=nBCzsu9NWQ4kjOfrX5E5va1vOo8UI8nimxSY6F_Rvq4,10188
-librelane/steps/verilator.py,sha256=6W7ljzi8OD7NuX_v12aI9EIwQd_YJ2BXcjWu0aDO-uI,9896
+librelane/steps/verilator.py,sha256=h5v5l7etVitFLReI3QSgD_Z57ZmB5Mv6Sszv5Lzz7IE,9913
 librelane/steps/yosys.py,sha256=BM1R_-omt1bSZa7J_REsbDPyW4MKv5A-ZfFzCzWu4QI,12762
-librelane-3.1.0.dev3.dist-info/METADATA,sha256=EWufq71fAjmL3kDEY9nIeYDsDE8eMYaMnSyolgUyKb8,8766
-librelane-3.1.0.dev3.dist-info/WHEEL,sha256=EGEvSphFYqXKs23-kQBeyNoJP1nrT8ZJKQoi5p5DYL8,88
-librelane-3.1.0.dev3.dist-info/entry_points.txt,sha256=Ub2wE2U4uZPjJgBVTPYFeXtwhNyqAqaKT8q4jGoKIUk,274
-librelane-3.1.0.dev3.dist-info/RECORD,,
+librelane-3.1.0.dev4.dist-info/METADATA,sha256=FoDlgmk5xX6eI0YQuykcfYhi5PkiIM8SPLo9_tZsZg0,8817
+librelane-3.1.0.dev4.dist-info/WHEEL,sha256=L-WvLdSBvJWHXv5zrQxDvNRnIgoBzLUpcbuiw19KCuQ,88
+librelane-3.1.0.dev4.dist-info/entry_points.txt,sha256=Ub2wE2U4uZPjJgBVTPYFeXtwhNyqAqaKT8q4jGoKIUk,274
+librelane-3.1.0.dev4.dist-info/RECORD,,

{librelane-3.1.0.dev3.dist-info → librelane-3.1.0.dev4.dist-info}/WHEEL

@@ -1,4 +1,4 @@
 Wheel-Version: 1.0
-Generator: poetry-core 2.4.0
+Generator: poetry-core 2.5.0
 Root-Is-Purelib: true
 Tag: py3-none-any