librelane 3.0.0.dev39__py3-none-any.whl → 3.0.0.dev41__py3-none-any.whl
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- librelane/common/metrics/__main__.py +4 -3
- librelane/config/variable.py +20 -10
- librelane/flows/flow.py +4 -3
- librelane/scripts/magic/drc.tcl +7 -0
- librelane/scripts/openroad/ioplacer.tcl +6 -0
- librelane/scripts/openroad/sta/check_macro_instances.tcl +1 -1
- librelane/scripts/pyosys/synthesize.py +33 -7
- librelane/scripts/pyosys/ys_common.py +10 -1
- librelane/steps/magic.py +14 -1
- librelane/steps/openroad.py +6 -0
- librelane/steps/pyosys.py +22 -1
- librelane/steps/step.py +1 -0
- librelane/steps/verilator.py +37 -8
- {librelane-3.0.0.dev39.dist-info → librelane-3.0.0.dev41.dist-info}/METADATA +15 -15
- {librelane-3.0.0.dev39.dist-info → librelane-3.0.0.dev41.dist-info}/RECORD +17 -17
- {librelane-3.0.0.dev39.dist-info → librelane-3.0.0.dev41.dist-info}/WHEEL +1 -1
- {librelane-3.0.0.dev39.dist-info → librelane-3.0.0.dev41.dist-info}/entry_points.txt +0 -1
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@@ -358,9 +358,10 @@ def compare_remote(
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for chunk in r.iter_bytes(chunk_size=8192):
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bio_gz.write(chunk)
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bio_gz.seek(0)
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with
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fileobj=bio,
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with (
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gzip.GzipFile(fileobj=bio_gz) as bio,
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tarfile.TarFile(fileobj=bio, mode="r") as tf,
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):
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for file in tf:
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if file.isdir():
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continue
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librelane/config/variable.py
CHANGED
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@@ -16,7 +16,6 @@ import inspect
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from enum import Enum
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from decimal import Decimal, InvalidOperation
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from dataclasses import (
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_MISSING_TYPE,
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MISSING,
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asdict,
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dataclass,
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@@ -24,6 +23,7 @@ from dataclasses import (
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fields,
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is_dataclass,
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)
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import types
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from typing import (
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ClassVar,
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Dict,
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@@ -219,7 +219,8 @@ class Macro:
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def is_optional(t: Type[Any]) -> bool:
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type_args = get_args(t)
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-
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origin = get_origin(t)
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return (origin is Union or origin is types.UnionType) and type(None) in type_args
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def some_of(t: Type[Any]) -> Type[Any]:
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@@ -229,11 +230,20 @@ def some_of(t: Type[Any]) -> Type[Any]:
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# t must be a Union with None if we're here
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type_args = get_args(t)
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origin = get_origin(t)
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args_without_none = [arg for arg in type_args if arg
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args_without_none = [arg for arg in type_args if arg is not type(None)]
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if len(args_without_none) == 1:
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return args_without_none[0]
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if origin is types.UnionType:
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# Use the | operator to create a UnionType
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result = args_without_none[0]
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for arg in args_without_none[1:]:
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result = result | arg
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return result
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# Otherwise, return a typing.Union
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new_union = Union[tuple(args_without_none)] # type: ignore
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return new_union # type: ignore
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@@ -440,7 +450,7 @@ class Variable:
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return_value = list()
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raw = value
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if isinstance(raw, list) or isinstance(raw, tuple):
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if
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if type_origin is list and type_args == (str,):
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if any(isinstance(item, List) for item in raw):
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Variable.__flatten_list(value)
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pass
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f"List provided for variable '{key_path}' is invalid: {value}"
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)
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if type_origin
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if type_origin is tuple:
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if len(raw) != len(type_args):
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raise ValueError(
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f"Value provided for variable '{key_path}' of type {validating_type} is invalid: ({len(raw)}/{len(type_args)}) tuple entries provided"
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)
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)
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if type_origin
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if type_origin is tuple:
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return tuple(return_value)
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return return_value
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elif type_origin
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elif type_origin is dict:
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raw = value
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key_type, value_type = type_args
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if isinstance(raw, dict):
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field_default = None
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if (
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current_field.default is not None
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and
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and current_field.default != MISSING
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):
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field_default = current_field.default
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if current_field.default_factory != MISSING:
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result = Path(value)
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result.validate(f"Path provided for variable '{key_path}' is invalid")
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return result
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elif validating_type
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elif validating_type is bool:
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if not permissive_typing and not isinstance(value, bool):
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raise ValueError(
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f"Refusing to automatically convert '{value}' at '{key_path}' to a Boolean"
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f"Value provided for variable '{key_path}' of type {validating_type.__name__} is invalid: '{value}'"
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)
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elif issubclass(validating_type, Enum):
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if type(value)
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if type(value) is validating_type:
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return value
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try:
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return validating_type[value]
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librelane/flows/flow.py
CHANGED
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@@ -916,9 +916,10 @@ class Flow(ABC):
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# Despite the name, this is the Magic DRC report simply
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# converted into a KLayout-compatible format. Confusing!
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drc_xml_out = os.path.join(openlane_signoff_dir, "drc.klayout.xml")
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with (
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open(drc_xml, encoding="utf8") as i,
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open(drc_xml_out, "w", encoding="utf8") as o,
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):
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o.write(
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"<!-- Despite the name, this is the Magic DRC report in KLayout format. -->\n"
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)
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librelane/scripts/magic/drc.tcl
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# Flatten cells
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if { [info exists ::env(MAGIC_GDS_FLATGLOB)] } {
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foreach {gds_flatglob} $::env(MAGIC_GDS_FLATGLOB) {
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gds flatglob $gds_flatglob
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}
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}
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if { $::env(MAGIC_DRC_USE_GDS) } {
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gds read $::env(CURRENT_GDS)
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} else {
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lappend arg_list -annealing
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}
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if { [info exists ::env(IO_EXCLUDE_PIN_REGION)] } {
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foreach exclude $::env(IO_EXCLUDE_PIN_REGION) {
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lappend arg_list -exclude $exclude
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}
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}
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set HMETAL $::env(FP_IO_HLAYER)
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set VMETAL $::env(FP_IO_VLAYER)
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set error_count 0
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foreach {instance_name macro_name} $::env(_check_macro_instances) {
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set instances [get_cells
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set instances [get_cells $instance_name]
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set instance_count [llength $instances]
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import os
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import json
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import shutil
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from typing import List, Optional
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import click
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def librelane_synth(
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d,
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flatten,
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report_dir,
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*,
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booth=False,
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abc_dff=False,
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undriven=True,
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keep_hierarchy_min_cost: Optional[int],
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keep_hierarchy_instances: List[str],
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keep_hierarchy_modules: List[str],
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):
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d.run_pass("hierarchy", "-check", "-top", top, "-nokeep_prints", "-nokeep_asserts")
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for keep_hierarchy_instance in keep_hierarchy_instances:
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)
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)
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if flatten:
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d.run_pass("flatten") # Flatten the design hierarchy
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d.run_pass("rename", "-top", config["DESIGN_NAME"])
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d.run_pass("select", "-module", config["DESIGN_NAME"])
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if config["SYNTH_SHOW"]:
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d.run_pass(
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except Exception:
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if config["SYNTH_NORMALIZE_SINGLE_BIT_VECTORS"]:
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abc_dff=config["SYNTH_ABC_DFF"],
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keep_hierarchy_min_cost=config["SYNTH_KEEP_HIERARCHY_MIN_COST"],
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keep_hierarchy_instances=config["SYNTH_KEEP_HIERARCHY_INSTANCES"],
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keep_hierarchy_modules=config["SYNTH_KEEP_HIERARCHY_MODULES"],
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d.run_pass("delete", "t:$print")
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"-prefix",
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os.path.join(step_dir, "primitive_techmap"),
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except Exception:
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if ext in [".v", ".sv", ".vh"]:
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"-lib",
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*include_args,
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model,
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)
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else:
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librelane/steps/magic.py
CHANGED
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# Copyright 2025 LibreLane Contributors
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#
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# Adapted from OpenLane
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#
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# Copyright 2023 Efabless Corporation
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# Licensed under the Apache License, Version 2.0 (the "License");
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name = "DRC"
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long_name = "Design Rule Checks"
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inputs = [DesignFormat.DEF, DesignFormat.GDS]
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inputs = [DesignFormat.DEF.mkOptional(), DesignFormat.GDS]
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outputs = []
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config_vars = MagicStep.config_vars + [
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@@ -399,6 +403,11 @@ class DRC(MagicStep):
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"A flag to choose whether to run the Magic DRC checks on GDS or not. If not, then the checks will be done on the DEF view of the design, which is a bit faster, but may be less accurate as some DEF/LEF elements are abstract.",
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default=True,
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),
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Variable(
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"MAGIC_GDS_FLATGLOB",
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Optional[List[str]],
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|
409
|
+
"Flatten cells by name pattern on input. May be used to avoid false positive DRC errors. The strings may use standard shell-type glob patterns, with * for any length string match, ? for any single character match, \\ for special characters, and [] for matching character sets or ranges.",
|
|
410
|
+
),
|
|
402
411
|
]
|
|
403
412
|
|
|
404
413
|
def get_script_path(self):
|
|
@@ -408,6 +417,10 @@ class DRC(MagicStep):
|
|
|
408
417
|
reports_dir = os.path.join(self.step_dir, "reports")
|
|
409
418
|
mkdirp(reports_dir)
|
|
410
419
|
|
|
420
|
+
# Check that the DEF exists if needed
|
|
421
|
+
if not self.config["MAGIC_DRC_USE_GDS"]:
|
|
422
|
+
assert state_in.get(DesignFormat.DEF)
|
|
423
|
+
|
|
411
424
|
views_updates, metrics_updates = super().run(state_in, **kwargs)
|
|
412
425
|
|
|
413
426
|
report_path = os.path.join(reports_dir, "drc_violations.magic.rpt")
|
librelane/steps/openroad.py
CHANGED
|
@@ -1213,6 +1213,12 @@ class IOPlacement(OpenROADStep):
|
|
|
1213
1213
|
Optional[Path],
|
|
1214
1214
|
"Points to the DEF file to be used as a template.",
|
|
1215
1215
|
),
|
|
1216
|
+
Variable(
|
|
1217
|
+
"IO_EXCLUDE_PIN_REGION",
|
|
1218
|
+
Optional[List[str]],
|
|
1219
|
+
"List of regions where pins cannot be placed. The regions are strings in the format `{edge}:{interval}` where edge is `top|bottom|left|right` and the interval is either `*` to exclude the entire edge or `{begin}-{end}` to exclude a part of the edge, where `begin` and `end` are either absolute distance values or themselves `*` to denote the very start or end of an edge.",
|
|
1220
|
+
units="µm",
|
|
1221
|
+
),
|
|
1216
1222
|
]
|
|
1217
1223
|
)
|
|
1218
1224
|
|
librelane/steps/pyosys.py
CHANGED
|
@@ -214,6 +214,12 @@ class PyosysStep(Step):
|
|
|
214
214
|
"A fully qualified IPVT corner to use during synthesis. If unspecified, the value for `DEFAULT_CORNER` from the PDK will be used.",
|
|
215
215
|
pdk=True,
|
|
216
216
|
),
|
|
217
|
+
Variable(
|
|
218
|
+
"SYNTH_SHOW",
|
|
219
|
+
bool,
|
|
220
|
+
"Generate a graphviz DOT file for the design. This will fail on a completely empty design.",
|
|
221
|
+
default=False,
|
|
222
|
+
),
|
|
217
223
|
]
|
|
218
224
|
|
|
219
225
|
@classmethod
|
|
@@ -444,7 +450,7 @@ class SynthesisCommon(VerilogStep):
|
|
|
444
450
|
Variable(
|
|
445
451
|
"SYNTH_HIERARCHY_MODE",
|
|
446
452
|
Literal["flatten", "deferred_flatten", "keep"],
|
|
447
|
-
"Affects how hierarchy is maintained throughout and after synthesis. 'flatten' flattens it during and after synthesis. 'deferred_flatten' flattens it after synthesis. 'keep' never flattens it. Please note that when using the Slang plugin, you need to pass '--keep-hierarchy' to `SLANG_ARGUMENTS` separately.",
|
|
453
|
+
"Affects how hierarchy is maintained throughout and after synthesis. 'flatten' flattens it during and after synthesis. 'deferred_flatten' flattens it after synthesis. 'keep' never flattens it. Please note that when using the Slang plugin, you need to pass '--keep-hierarchy' to `SLANG_ARGUMENTS` separately. To keep the hierarchy partially, use one of the flattening options and set the 'keep_hierarchy' attribute on instances or modules via: `SYNTH_KEEP_HIERARCHY_INSTANCES`, `SYNTH_KEEP_HIERARCHY_MODULES` or `SYNTH_KEEP_HIERARCHY_MIN_COST`.",
|
|
448
454
|
default="flatten",
|
|
449
455
|
deprecated_names=[
|
|
450
456
|
(
|
|
@@ -453,6 +459,21 @@ class SynthesisCommon(VerilogStep):
|
|
|
453
459
|
)
|
|
454
460
|
],
|
|
455
461
|
),
|
|
462
|
+
Variable(
|
|
463
|
+
"SYNTH_KEEP_HIERARCHY_MIN_COST",
|
|
464
|
+
Optional[int],
|
|
465
|
+
"Sets the 'keep_hierarchy' attribute on modules where the gate count is estimated to exceed the specified threshold. This prevents larger modules from being flattened. This variable only affects the design when 'flatten' is called through `SYNTH_HIERARCHY_MODE`.",
|
|
466
|
+
),
|
|
467
|
+
Variable(
|
|
468
|
+
"SYNTH_KEEP_HIERARCHY_INSTANCES",
|
|
469
|
+
Optional[List[str]],
|
|
470
|
+
"A list of instances for which to set the 'keep_hierarchy' attribute. This variable only affects the design when 'flatten' is called through `SYNTH_HIERARCHY_MODE`.",
|
|
471
|
+
),
|
|
472
|
+
Variable(
|
|
473
|
+
"SYNTH_KEEP_HIERARCHY_MODULES",
|
|
474
|
+
Optional[List[str]],
|
|
475
|
+
"A list of modules for which to set the 'keep_hierarchy' attribute. This variable only affects the design when 'flatten' is called through `SYNTH_HIERARCHY_MODE`.",
|
|
476
|
+
),
|
|
456
477
|
Variable(
|
|
457
478
|
"SYNTH_SHARE_RESOURCES",
|
|
458
479
|
bool,
|
librelane/steps/step.py
CHANGED
|
@@ -1016,6 +1016,7 @@ class Step(ABC):
|
|
|
1016
1016
|
state_in: GenericDict[str, Any] = self.state_in.result().copy_mut()
|
|
1017
1017
|
for format_id in state_in:
|
|
1018
1018
|
format = DesignFormat.factory.get(format_id)
|
|
1019
|
+
assert format is not None
|
|
1019
1020
|
if format not in self.__class__.inputs and not (
|
|
1020
1021
|
format == DesignFormat.DEF
|
|
1021
1022
|
and DesignFormat.ODB
|
librelane/steps/verilator.py
CHANGED
|
@@ -1,3 +1,7 @@
|
|
|
1
|
+
# Copyright 2025 LibreLane Contributors
|
|
2
|
+
#
|
|
3
|
+
# Adapted from OpenLane
|
|
4
|
+
#
|
|
1
5
|
# Copyright 2023 Efabless Corporation
|
|
2
6
|
#
|
|
3
7
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
@@ -84,6 +88,23 @@ class Lint(Step):
|
|
|
84
88
|
Optional[List[str]],
|
|
85
89
|
"Linter-specific preprocessor definitions; overrides VERILOG_DEFINES for the lint step if exists",
|
|
86
90
|
),
|
|
91
|
+
Variable(
|
|
92
|
+
"LINTER_DISABLE_WARNINGS",
|
|
93
|
+
Optional[List[str]],
|
|
94
|
+
"Warning codes that are passed to the linter to be disabled.",
|
|
95
|
+
default=["DECLFILENAME", "EOFNEWLINE"],
|
|
96
|
+
),
|
|
97
|
+
Variable(
|
|
98
|
+
"LINTER_DISABLE_WARNINGS_BLACKBOX",
|
|
99
|
+
Optional[List[str]],
|
|
100
|
+
"Warning codes that are passed to the linter to be disabled for all blackbox modules.",
|
|
101
|
+
default=["UNDRIVEN", "UNUSEDSIGNAL"],
|
|
102
|
+
),
|
|
103
|
+
Variable(
|
|
104
|
+
"LINTER_VLT",
|
|
105
|
+
Optional[Path],
|
|
106
|
+
"Path to a Verilator Configuration format file (`.vlt`) that is passed to the linter.",
|
|
107
|
+
),
|
|
87
108
|
]
|
|
88
109
|
|
|
89
110
|
def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
|
|
@@ -149,11 +170,16 @@ class Lint(Step):
|
|
|
149
170
|
vlt_file = os.path.join(self.step_dir, "_deps.vlt")
|
|
150
171
|
with open(vlt_file, "w") as f:
|
|
151
172
|
f.write("`verilator_config\n")
|
|
152
|
-
|
|
153
|
-
|
|
173
|
+
if disable_warnings := self.config["LINTER_DISABLE_WARNINGS"]:
|
|
174
|
+
for warn in disable_warnings:
|
|
175
|
+
f.write(f"lint_off -rule {warn}\n")
|
|
176
|
+
|
|
154
177
|
for blackbox in blackboxes:
|
|
155
|
-
|
|
156
|
-
|
|
178
|
+
if disable_warnings_bb := self.config[
|
|
179
|
+
"LINTER_DISABLE_WARNINGS_BLACKBOX"
|
|
180
|
+
]:
|
|
181
|
+
for warn in disable_warnings_bb:
|
|
182
|
+
f.write(f'lint_off -rule {warn} -file "{blackbox}"\n')
|
|
157
183
|
|
|
158
184
|
extra_args.append("--Wno-fatal")
|
|
159
185
|
|
|
@@ -169,20 +195,23 @@ class Lint(Step):
|
|
|
169
195
|
for define in defines:
|
|
170
196
|
extra_args.append(f"+define+{define}")
|
|
171
197
|
|
|
198
|
+
if linter_vlt := self.config["LINTER_VLT"]:
|
|
199
|
+
extra_args.append(linter_vlt)
|
|
200
|
+
|
|
172
201
|
result = self.run_subprocess(
|
|
173
202
|
[
|
|
174
203
|
"verilator",
|
|
175
204
|
"--lint-only",
|
|
205
|
+
"--waiver-output",
|
|
206
|
+
os.path.join(self.step_dir, "_waivers_output.vlt"),
|
|
176
207
|
"--Wall",
|
|
177
|
-
"--Wno-DECLFILENAME",
|
|
178
|
-
"--Wno-EOFNEWLINE",
|
|
179
208
|
"--top-module",
|
|
180
209
|
self.config["DESIGN_NAME"],
|
|
181
210
|
vlt_file,
|
|
182
211
|
]
|
|
212
|
+
+ extra_args
|
|
183
213
|
+ blackboxes
|
|
184
|
-
+ self.config["VERILOG_FILES"]
|
|
185
|
-
+ extra_args,
|
|
214
|
+
+ self.config["VERILOG_FILES"],
|
|
186
215
|
env=env,
|
|
187
216
|
check=False,
|
|
188
217
|
)
|
|
@@ -1,41 +1,41 @@
|
|
|
1
|
-
Metadata-Version: 2.
|
|
1
|
+
Metadata-Version: 2.4
|
|
2
2
|
Name: librelane
|
|
3
|
-
Version: 3.0.0.
|
|
3
|
+
Version: 3.0.0.dev41
|
|
4
4
|
Summary: An infrastructure for implementing chip design flows
|
|
5
|
-
|
|
6
|
-
|
|
7
|
-
|
|
8
|
-
|
|
9
|
-
Requires-Python: >=3.8.1,<4
|
|
10
|
-
Classifier: License :: OSI Approved :: Apache Software License
|
|
5
|
+
License-Expression: Apache-2.0
|
|
6
|
+
Maintainer: Mohamed Gaber
|
|
7
|
+
Maintainer-email: me@donn.website
|
|
8
|
+
Requires-Python: >=3.10
|
|
11
9
|
Classifier: Programming Language :: Python :: 3
|
|
12
|
-
Classifier: Programming Language :: Python :: 3.9
|
|
13
10
|
Classifier: Programming Language :: Python :: 3.10
|
|
14
11
|
Classifier: Programming Language :: Python :: 3.11
|
|
15
12
|
Classifier: Programming Language :: Python :: 3.12
|
|
16
13
|
Classifier: Programming Language :: Python :: 3.13
|
|
17
|
-
|
|
14
|
+
Classifier: Programming Language :: Python :: 3.14
|
|
15
|
+
Requires-Dist: ciel (>=2.3.1,<3)
|
|
18
16
|
Requires-Dist: click (>=8,<8.2)
|
|
19
17
|
Requires-Dist: cloup (>=3.0.5,<4)
|
|
20
18
|
Requires-Dist: deprecated (>=1.2.10,<2)
|
|
21
19
|
Requires-Dist: httpx (>=0.22.0,<0.29)
|
|
22
|
-
Requires-Dist: klayout (>=0.29.0,<0.
|
|
20
|
+
Requires-Dist: klayout (>=0.29.0,<0.32.0)
|
|
23
21
|
Requires-Dist: lln-libparse (==0.56.*)
|
|
24
22
|
Requires-Dist: lxml (>=4.9.0)
|
|
25
23
|
Requires-Dist: psutil (>=5.9.0)
|
|
26
24
|
Requires-Dist: pyyaml (>=5,<7)
|
|
27
25
|
Requires-Dist: rapidfuzz (>=3.9.0,<4)
|
|
28
26
|
Requires-Dist: rich (>=12,<15)
|
|
29
|
-
Requires-Dist: semver (>=3.0.2,<4
|
|
30
|
-
Requires-Dist: yamlcore (>=0.0.2,<0.0
|
|
27
|
+
Requires-Dist: semver (>=3.0.2,<4)
|
|
28
|
+
Requires-Dist: yamlcore (>=0.0.2,<0.1.0)
|
|
29
|
+
Project-URL: Bug Tracker, https://github.com/librelane/librelane/issues
|
|
31
30
|
Project-URL: Documentation, https://librelane.readthedocs.io
|
|
31
|
+
Project-URL: Homepage, https://librelane.org/
|
|
32
32
|
Project-URL: Repository, https://github.com/librelane/librelane
|
|
33
33
|
Description-Content-Type: text/markdown
|
|
34
34
|
|
|
35
35
|
<h1 align="center">LibreLane</h1>
|
|
36
36
|
<p align="center">
|
|
37
37
|
<a href="https://opensource.org/licenses/Apache-2.0"><img src="https://img.shields.io/badge/License-Apache%202.0-blue.svg" alt="License: Apache 2.0"/></a>
|
|
38
|
-
<a href="https://www.python.org"><img src="https://img.shields.io/badge/Python-3.
|
|
38
|
+
<a href="https://www.python.org"><img src="https://img.shields.io/badge/Python-3.10-3776AB.svg?style=flat&logo=python&logoColor=white" alt="Python ≥3.10" /></a>
|
|
39
39
|
<a href="https://github.com/psf/black"><img src="https://img.shields.io/badge/code%20style-black-000000.svg" alt="Code Style: black"/></a>
|
|
40
40
|
<a href="https://mypy-lang.org/"><img src="https://www.mypy-lang.org/static/mypy_badge.svg" alt="Checked with mypy"/></a>
|
|
41
41
|
<a href="https://nixos.org/"><img src="https://img.shields.io/static/v1?logo=nixos&logoColor=white&label=&message=Built%20with%20Nix&color=41439a" alt="Built with Nix"/></a>
|
|
@@ -72,7 +72,7 @@ Colaboratory by following
|
|
|
72
72
|
|
|
73
73
|
You'll need the following:
|
|
74
74
|
|
|
75
|
-
* Python **3.
|
|
75
|
+
* Python **3.10** or higher with PIP, Venv and Tkinter
|
|
76
76
|
|
|
77
77
|
### Nix (Recommended)
|
|
78
78
|
|
|
@@ -6,7 +6,7 @@ librelane/common/cli.py,sha256=xi48GBGHRsYrLGwx40ARwpykHx7GnuHbJjHxjOwtZ5Y,2349
|
|
|
6
6
|
librelane/common/drc.py,sha256=l1quZbHXGb7yjKCO5IFn-Xxf_zIx4f6kxqpNm3YmpOs,12809
|
|
7
7
|
librelane/common/generic_dict.py,sha256=ASa5wtVcLuGlsBqGfLxLYXrYksqQB62iHljV04plIqI,10010
|
|
8
8
|
librelane/common/metrics/__init__.py,sha256=nzdmeia1fN4CDPT604v-OHaBVydz-M4hz232g-jxJ6M,1521
|
|
9
|
-
librelane/common/metrics/__main__.py,sha256=
|
|
9
|
+
librelane/common/metrics/__main__.py,sha256=tU-HzmvisMlAt6mlg5IhR4WOFUr8PZZFdb_cfwP5FnY,12558
|
|
10
10
|
librelane/common/metrics/library.py,sha256=CG7rubLdjuCQL9-9bzAC-64hf-KlH-iu_Fg0oKuesqs,7373
|
|
11
11
|
librelane/common/metrics/metric.py,sha256=h3Xd26z5M80IJgVmmrBTjKcdGLb4I0wyjM-H4jdyi_0,6990
|
|
12
12
|
librelane/common/metrics/util.py,sha256=Bl_9znlot7-Os2VigYLSmMf56aAkGdv3evWz9vfK7K4,9344
|
|
@@ -23,7 +23,7 @@ librelane/config/flow.py,sha256=Dr2i9MlCcGFg_ilCpeys3vPo_DLDb1yF6yGrMCZZabE,1700
|
|
|
23
23
|
librelane/config/pdk_compat.py,sha256=ofqYuD-MgTcfvPVXpGJo8H1GKzCvN6sxHsK_OqCVXa8,12870
|
|
24
24
|
librelane/config/preprocessor.py,sha256=ATi29SHz0_OBq1IqUkGxvhHUDKB5z5jO0KqvoQXg8R8,14913
|
|
25
25
|
librelane/config/removals.py,sha256=vxqTuRTJ0jt2TX4KmFZCZPTwghDFkCVjIhF2iReHwJA,2958
|
|
26
|
-
librelane/config/variable.py,sha256=
|
|
26
|
+
librelane/config/variable.py,sha256=SKhMJT3jnJt7w3vZacD8_4n5YUH3hecG0iAnHjZrkPk,27162
|
|
27
27
|
librelane/container.py,sha256=7w_V2Fpb3dbnZ8FqBce1vK31jH30UrxByppfEJRyG9M,8672
|
|
28
28
|
librelane/env_info.py,sha256=xF9iqwwJv5yZz7n7BTrrT_yP3Dp1HjAOUObNE9k_1g4,11074
|
|
29
29
|
librelane/examples/spm/config.yaml,sha256=H2ERY4xoIeXN7kM3N9yGWiFBbtByyaN2Ni1kFqYPtO4,612
|
|
@@ -43,7 +43,7 @@ librelane/flows/__init__.py,sha256=ghtmUG-taVpHJ3CKJRYZGn3dU0r93araT1EIGlBEsxg,8
|
|
|
43
43
|
librelane/flows/builtins.py,sha256=tR14Qc1ZUey2w-Ar4DWOvxuP7LGPtMecCJq8WgcYJpk,773
|
|
44
44
|
librelane/flows/classic.py,sha256=JB9gVgP2hHPhMuCJg7hvoj2BvJcvRec7suEXPgHmz14,10971
|
|
45
45
|
librelane/flows/cli.py,sha256=ClFU3f81I5PDUMg249UzSdlYU_iZoX_CaEQtYpwvkA8,19346
|
|
46
|
-
librelane/flows/flow.py,sha256=
|
|
46
|
+
librelane/flows/flow.py,sha256=kV6874HFxceFCrGpv4V7hjplajUpd7OvEyU5-2OhGQg,37128
|
|
47
47
|
librelane/flows/misc.py,sha256=32Om3isexesfKKiJZCajNmINc-xdv7eVx_tgoh9SR6U,2015
|
|
48
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