librelane 3.0.0.dev32__py3-none-any.whl → 3.0.0.dev34__py3-none-any.whl

librelane/scripts/magic/extract_spice.tcl

@@ -79,9 +79,11 @@ extract no capacitance
 extract no coupling
 extract no resistance
 extract no adjust
-if { ! $::env(MAGIC_NO_EXT_UNIQUE) } {
-    extract unique
+
+if { $::env(MAGIC_EXT_UNIQUE) != "none" } {
+    extract unique $::env(MAGIC_EXT_UNIQUE)
 }
+
 # extract warn all
 extract
 

librelane/scripts/pyosys/json_header.py

@@ -63,6 +63,7 @@ def json_header(
         includes=includes,
         defines=defines,
         use_slang=config["USE_SLANG"],
+        slang_arguments=config["SLANG_ARGUMENTS"] or [],
     )
     d.run_pass(
         "hierarchy",

librelane/scripts/pyosys/synthesize.py

@@ -263,6 +263,7 @@ def synthesize(
             includes=includes,
             defines=defines,
             use_slang=False,
+            slang_arguments=[],
         )
     elif verilog_files := config.get("VERILOG_FILES"):
         d.read_verilog_files(
@@ -272,6 +273,7 @@ def synthesize(
             includes=includes,
             defines=defines,
             use_slang=config["USE_SLANG"],
+            slang_arguments=config["SLANG_ARGUMENTS"] or [],
         )
     elif vhdl_files := config.get("VHDL_FILES"):
         d.run_pass("plugin", "-i", "ghdl")

librelane/scripts/pyosys/ys_common.py

@@ -51,6 +51,7 @@ def _Design_read_verilog_files(
     includes: Iterable[str],
     defines: Iterable[str],
     use_slang: bool = False,
+    slang_arguments: Iterable[str],
 ):
     files = list(files)  # for easier concatenation
     include_args = [f"-I{dir}" for dir in includes]
@@ -72,6 +73,7 @@ def _Design_read_verilog_files(
             *define_args,
             *include_args,
             *slang_chparam_args,
+            *slang_arguments,
             *files,
         )
     else:

librelane/steps/magic.py

@@ -458,15 +458,18 @@ class SpiceExtraction(MagicStep):
         Variable(
             "MAGIC_EXT_ABSTRACT_CELLS",
             Optional[List[str]],
-            "A list of regular experssions which are matched against the cells of a "
+            "A list of regular expressions which are matched against the cells of a "
             + "the design. Matches are abstracted (black-boxed) during SPICE extraction.",
         ),
         Variable(
-            "MAGIC_NO_EXT_UNIQUE",
-            bool,
-            "Enables connections by label in LVS by skipping `extract unique` in Magic extractions.",
-            default=False,
-            deprecated_names=["LVS_CONNECT_BY_LABEL"],
+            "MAGIC_EXT_UNIQUE",
+            Literal["all", "notopports", "noports", "none"],
+            'Runs `extract unique` with the specified option. The default is "all", and "none" disables `extract unique`, allowing connections between separate nets by label in LVS.',
+            default="all",
+            deprecated_names=[
+                ("MAGIC_NO_EXT_UNIQUE", lambda o: "none" if o else "all"),
+                ("LVS_CONNECT_BY_LABEL", lambda o: "none" if o else "all"),
+            ],
         ),
         Variable(
             "MAGIC_EXT_SHORT_RESISTOR",

librelane/steps/pyosys.py

@@ -128,6 +128,11 @@ verilog_rtl_cfg_vars = [
         default=False,
         deprecated_names=["USE_SYNLIG"],
     ),
+    Variable(
+        "SLANG_ARGUMENTS",
+        Optional[List[str]],
+        "Pass arguments to the Slang frontend.",
+    ),
 ]
 
 DesignFormat(
@@ -439,7 +444,7 @@ class SynthesisCommon(VerilogStep):
         Variable(
             "SYNTH_HIERARCHY_MODE",
             Literal["flatten", "deferred_flatten", "keep"],
-            "Affects how hierarchy is maintained throughout and after synthesis. 'flatten' flattens it during and after synthesis. 'deferred_flatten' flattens it after synthesis. 'keep' never flattens it.",
+            "Affects how hierarchy is maintained throughout and after synthesis. 'flatten' flattens it during and after synthesis. 'deferred_flatten' flattens it after synthesis. 'keep' never flattens it. Please note that when using the Slang plugin, you need to pass '--keep-hierarchy' to `SLANG_ARGUMENTS` separately.",
             default="flatten",
             deprecated_names=[
                 (

{librelane-3.0.0.dev32.dist-info → librelane-3.0.0.dev34.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: librelane
-Version: 3.0.0.dev32
+Version: 3.0.0.dev34
 Summary: An infrastructure for implementing chip design flows
 Home-page: https://github.com/librelane/librelane
 License: Apache-2.0

{librelane-3.0.0.dev32.dist-info → librelane-3.0.0.dev34.dist-info}/RECORD

@@ -67,7 +67,7 @@ librelane/scripts/magic/def/antenna_check.tcl,sha256=T_r1CWgySFVlLMcoTrNXQ_aMRs_
 librelane/scripts/magic/def/mag.tcl,sha256=PuL3MH6pmZP5Qh2cJ0GygWNzaYjdCSCoAbOli-JB4fs,707
 librelane/scripts/magic/def/mag_gds.tcl,sha256=fwtQR9zPZpWqVmmLb-1hzY4WMCr4gbA3S0pTZsS9sss,2144
 librelane/scripts/magic/drc.tcl,sha256=gPGyI96lR10dJXcJACajzHaHiT6ayAYPJqrmmuQkABc,2395
-librelane/scripts/magic/extract_spice.tcl,sha256=-jDxVEGddch1YZLZXW1vFXhdLkeTjxk0d8eU1tBMBWc,2788
+librelane/scripts/magic/extract_spice.tcl,sha256=2NjDFbqRfTsWhD1s-NGcDr8e4o3Ejg-4vCEoLt22RCc,2820
 librelane/scripts/magic/gds/drc_batch.tcl,sha256=O76rwxSrQgoCuoxk36tRBZkQaeMfJknlHrQA3mtU2JU,2198
 librelane/scripts/magic/gds/erase_box.tcl,sha256=wsVSwMlkZFJa_MEGNsdXLnXFvjZlrl_lzIWkJjcDBgg,929
 librelane/scripts/magic/gds/extras_mag.tcl,sha256=1raG0URUezUDEKkdDeJqdlS0Y5gb4IzQFnjFysHHlmU,1304
@@ -142,9 +142,9 @@ librelane/scripts/openroad/ungpl.tcl,sha256=vhHxou1W3VROwJePoQzmWn0h0d5lQrrt1vof
 librelane/scripts/openroad/write_cdl.tcl,sha256=uPO1IROPTr5NrW0-VZA8tXQD8aseGeXDXDsU8TX-9nQ,460
 librelane/scripts/openroad/write_views.tcl,sha256=-MxTJsB4EF7l5trDaZe-VBFjhfzqRt8F5_DZrADTs0U,892
 librelane/scripts/pyosys/construct_abc_script.py,sha256=3CCDz5ZTEPpWLco-OvikTmn361-BNitqjQE_-5zHm14,6733
-librelane/scripts/pyosys/json_header.py,sha256=gKla0V4tFhF5fR-zzudrTr6TjpqkV3c69PWk1fVfMgg,2332
-librelane/scripts/pyosys/synthesize.py,sha256=soDbOObGdCix3zDUQFIF6FvZn6_mT_GonkvH5exGQiA,16927
-librelane/scripts/pyosys/ys_common.py,sha256=t5LLEYoy4cfCIeEaAo8Nr51rXtlI8ZPe1h_kSbrky5M,3891
+librelane/scripts/pyosys/json_header.py,sha256=fbHPjUkTQHKbdGPh7P1jZjip3nat4k8oSD1N7rpXxFk,2389
+librelane/scripts/pyosys/synthesize.py,sha256=5BlgXK5gfJWv9E8ki9UXUDLxlfKoGwXgqjdDMiPrms8,17020
+librelane/scripts/pyosys/ys_common.py,sha256=r9BQ7j8gN6sgJM9nC3QPNZcZX10m_PF8We4S93qZ5w0,3957
 librelane/scripts/tclsh/hello.tcl,sha256=kkR3akY7QnGHYXsQODYwLkMkUEOgWcNFtzaMTTEV2bY,34
 librelane/state/__init__.py,sha256=DZ_RyKMr2oj4p5d32u8MmDKfCxR7OEdDw-1HWKTpatA,949
 librelane/state/__main__.py,sha256=Ici4Ejg1ICUZNSYZRguC3BfEk_wFxsmE0ag0Vv8iY1I,1679
@@ -156,18 +156,18 @@ librelane/steps/checker.py,sha256=HD5YFPAbHQKsFmBDrIAbo_0clZcCszNhIXb4lHaNIeQ,21
 librelane/steps/common_variables.py,sha256=eih2eA1m0FpL8ydF5WWattwh_SxtzI55eb8gggJtBuY,12494
 librelane/steps/cvc_rv.py,sha256=qeroQPjidSAMYSp3nJNiQBYt8V73kkz3JK97uioo7J8,5294
 librelane/steps/klayout.py,sha256=18B7trKjyD8HnGUVwrjQV8XRzGu298CuosM1WOzg9oM,23255
-librelane/steps/magic.py,sha256=m4cZH2VomJs0RudtV8avSaZVqRj1NP7Pm2P6qo2z2X0,20919
+librelane/steps/magic.py,sha256=Cc_qApOgeltIn7lKA7dBQ4Ud9EQtbMatsuGPEvqvpcQ,21183
 librelane/steps/misc.py,sha256=8ubCvFeFEspXrgnzNWINY5-TXTyalNtlvcX8TSw0qdg,5685
 librelane/steps/netgen.py,sha256=R9sDWv-9wKMdi2rkuLQdOc4uLlbYhXcKKd6WsZsnLt0,8953
 librelane/steps/odb.py,sha256=-zsXi0jVdtfBfAJI0OC4x1jI_B2OX5YVn4uAn6NyFdk,38424
 librelane/steps/openroad.py,sha256=hgpqsVQi7tFRlj75zefQkD3Vdmq21ubZAFWyU12WxUg,99586
 librelane/steps/openroad_alerts.py,sha256=IJyB4piBDCKXhkJswHGMYCRDwbdQsR0GZlrGGDhmW6Q,3364
-librelane/steps/pyosys.py,sha256=LY7qqxkhjfoyBBR7vdkm7ylabbxMJDwIoYm7mAUbLVY,23348
+librelane/steps/pyosys.py,sha256=BzTUYCFxXJWtHqPtEPAztoWNLbDWvECWnsWVdK_lljU,23589
 librelane/steps/step.py,sha256=THIxZkhtkNYt1iRgMduD0ywrOTCaV7cCfUB2EqXN6-k,55751
 librelane/steps/tclstep.py,sha256=68AjCmbLhBscbzQDxRcPQVU-6UvZQNOalO7qNwUXCa4,10138
 librelane/steps/verilator.py,sha256=MWx2TpLqYyea9_jSeLG9c2S5ujvYERQZRFNaMhfHxZE,7916
 librelane/steps/yosys.py,sha256=lYdZPFvjcmdu_NE6rtB94_dysIK2qwGdGb480W6pg2w,12711
-librelane-3.0.0.dev32.dist-info/METADATA,sha256=djo0K7TzkitmcNUdzjBIlZyhud9u389_OeTWGcmdyjk,6561
-librelane-3.0.0.dev32.dist-info/WHEEL,sha256=Nq82e9rUAnEjt98J6MlVmMCZb-t9cYE2Ir1kpBmnWfs,88
-librelane-3.0.0.dev32.dist-info/entry_points.txt,sha256=0eZs2NOH-w-W_GVRCs-ualst26XplkPpJkOnGWMaFw0,306
-librelane-3.0.0.dev32.dist-info/RECORD,,
+librelane-3.0.0.dev34.dist-info/METADATA,sha256=qoArrX0bEBJJAvuN8-edEBPE33CRzB_XIie0ZtGxTJo,6561
+librelane-3.0.0.dev34.dist-info/WHEEL,sha256=Nq82e9rUAnEjt98J6MlVmMCZb-t9cYE2Ir1kpBmnWfs,88
+librelane-3.0.0.dev34.dist-info/entry_points.txt,sha256=0eZs2NOH-w-W_GVRCs-ualst26XplkPpJkOnGWMaFw0,306
+librelane-3.0.0.dev34.dist-info/RECORD,,