librelane 3.0.0.dev32__py3-none-any.whl → 3.0.0.dev33__py3-none-any.whl

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@@ -63,6 +63,7 @@ def json_header(
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  includes=includes,
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  defines=defines,
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  use_slang=config["USE_SLANG"],
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+ slang_arguments=config["SLANG_ARGUMENTS"] or [],
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  )
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  d.run_pass(
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  "hierarchy",
@@ -263,6 +263,7 @@ def synthesize(
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  includes=includes,
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  defines=defines,
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  use_slang=False,
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+ slang_arguments=[],
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  )
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  elif verilog_files := config.get("VERILOG_FILES"):
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  d.read_verilog_files(
@@ -272,6 +273,7 @@ def synthesize(
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  includes=includes,
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  defines=defines,
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  use_slang=config["USE_SLANG"],
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+ slang_arguments=config["SLANG_ARGUMENTS"] or [],
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  )
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  elif vhdl_files := config.get("VHDL_FILES"):
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  d.run_pass("plugin", "-i", "ghdl")
@@ -51,6 +51,7 @@ def _Design_read_verilog_files(
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  includes: Iterable[str],
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  defines: Iterable[str],
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  use_slang: bool = False,
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+ slang_arguments: Iterable[str],
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  ):
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  files = list(files) # for easier concatenation
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  include_args = [f"-I{dir}" for dir in includes]
@@ -72,6 +73,7 @@ def _Design_read_verilog_files(
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  *define_args,
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  *include_args,
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  *slang_chparam_args,
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+ *slang_arguments,
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  *files,
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  )
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  else:
librelane/steps/pyosys.py CHANGED
@@ -128,6 +128,11 @@ verilog_rtl_cfg_vars = [
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  default=False,
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  deprecated_names=["USE_SYNLIG"],
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  ),
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+ Variable(
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+ "SLANG_ARGUMENTS",
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+ Optional[List[str]],
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+ "Pass arguments to the Slang frontend.",
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+ ),
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  ]
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  DesignFormat(
@@ -439,7 +444,7 @@ class SynthesisCommon(VerilogStep):
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  Variable(
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  "SYNTH_HIERARCHY_MODE",
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  Literal["flatten", "deferred_flatten", "keep"],
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- "Affects how hierarchy is maintained throughout and after synthesis. 'flatten' flattens it during and after synthesis. 'deferred_flatten' flattens it after synthesis. 'keep' never flattens it.",
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+ "Affects how hierarchy is maintained throughout and after synthesis. 'flatten' flattens it during and after synthesis. 'deferred_flatten' flattens it after synthesis. 'keep' never flattens it. Please note that when using the Slang plugin, you need to pass '--keep-hierarchy' to `SLANG_ARGUMENTS` separately.",
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  default="flatten",
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  deprecated_names=[
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  (
@@ -1,6 +1,6 @@
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  Metadata-Version: 2.1
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  Name: librelane
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- Version: 3.0.0.dev32
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+ Version: 3.0.0.dev33
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  Summary: An infrastructure for implementing chip design flows
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  Home-page: https://github.com/librelane/librelane
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  License: Apache-2.0
@@ -142,9 +142,9 @@ librelane/scripts/openroad/ungpl.tcl,sha256=vhHxou1W3VROwJePoQzmWn0h0d5lQrrt1vof
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  librelane/scripts/openroad/write_cdl.tcl,sha256=uPO1IROPTr5NrW0-VZA8tXQD8aseGeXDXDsU8TX-9nQ,460
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  librelane/scripts/openroad/write_views.tcl,sha256=-MxTJsB4EF7l5trDaZe-VBFjhfzqRt8F5_DZrADTs0U,892
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  librelane/scripts/pyosys/construct_abc_script.py,sha256=3CCDz5ZTEPpWLco-OvikTmn361-BNitqjQE_-5zHm14,6733
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- librelane/scripts/pyosys/json_header.py,sha256=gKla0V4tFhF5fR-zzudrTr6TjpqkV3c69PWk1fVfMgg,2332
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- librelane/scripts/pyosys/synthesize.py,sha256=soDbOObGdCix3zDUQFIF6FvZn6_mT_GonkvH5exGQiA,16927
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- librelane/scripts/pyosys/ys_common.py,sha256=t5LLEYoy4cfCIeEaAo8Nr51rXtlI8ZPe1h_kSbrky5M,3891
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+ librelane/scripts/pyosys/json_header.py,sha256=fbHPjUkTQHKbdGPh7P1jZjip3nat4k8oSD1N7rpXxFk,2389
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+ librelane/scripts/pyosys/synthesize.py,sha256=5BlgXK5gfJWv9E8ki9UXUDLxlfKoGwXgqjdDMiPrms8,17020
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+ librelane/scripts/pyosys/ys_common.py,sha256=r9BQ7j8gN6sgJM9nC3QPNZcZX10m_PF8We4S93qZ5w0,3957
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  librelane/scripts/tclsh/hello.tcl,sha256=kkR3akY7QnGHYXsQODYwLkMkUEOgWcNFtzaMTTEV2bY,34
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  librelane/state/__init__.py,sha256=DZ_RyKMr2oj4p5d32u8MmDKfCxR7OEdDw-1HWKTpatA,949
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  librelane/state/__main__.py,sha256=Ici4Ejg1ICUZNSYZRguC3BfEk_wFxsmE0ag0Vv8iY1I,1679
@@ -162,12 +162,12 @@ librelane/steps/netgen.py,sha256=R9sDWv-9wKMdi2rkuLQdOc4uLlbYhXcKKd6WsZsnLt0,895
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  librelane/steps/odb.py,sha256=-zsXi0jVdtfBfAJI0OC4x1jI_B2OX5YVn4uAn6NyFdk,38424
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  librelane/steps/openroad.py,sha256=hgpqsVQi7tFRlj75zefQkD3Vdmq21ubZAFWyU12WxUg,99586
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  librelane/steps/openroad_alerts.py,sha256=IJyB4piBDCKXhkJswHGMYCRDwbdQsR0GZlrGGDhmW6Q,3364
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- librelane/steps/pyosys.py,sha256=LY7qqxkhjfoyBBR7vdkm7ylabbxMJDwIoYm7mAUbLVY,23348
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+ librelane/steps/pyosys.py,sha256=BzTUYCFxXJWtHqPtEPAztoWNLbDWvECWnsWVdK_lljU,23589
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  librelane/steps/step.py,sha256=THIxZkhtkNYt1iRgMduD0ywrOTCaV7cCfUB2EqXN6-k,55751
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  librelane/steps/tclstep.py,sha256=68AjCmbLhBscbzQDxRcPQVU-6UvZQNOalO7qNwUXCa4,10138
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  librelane/steps/verilator.py,sha256=MWx2TpLqYyea9_jSeLG9c2S5ujvYERQZRFNaMhfHxZE,7916
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  librelane/steps/yosys.py,sha256=lYdZPFvjcmdu_NE6rtB94_dysIK2qwGdGb480W6pg2w,12711
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- librelane-3.0.0.dev32.dist-info/METADATA,sha256=djo0K7TzkitmcNUdzjBIlZyhud9u389_OeTWGcmdyjk,6561
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- librelane-3.0.0.dev32.dist-info/WHEEL,sha256=Nq82e9rUAnEjt98J6MlVmMCZb-t9cYE2Ir1kpBmnWfs,88
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- librelane-3.0.0.dev32.dist-info/entry_points.txt,sha256=0eZs2NOH-w-W_GVRCs-ualst26XplkPpJkOnGWMaFw0,306
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- librelane-3.0.0.dev32.dist-info/RECORD,,
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+ librelane-3.0.0.dev33.dist-info/METADATA,sha256=u7-qZzdB2GVYUEeR1RAAyHvIC8GU4Y3cprFnjR_uJyU,6561
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+ librelane-3.0.0.dev33.dist-info/WHEEL,sha256=Nq82e9rUAnEjt98J6MlVmMCZb-t9cYE2Ir1kpBmnWfs,88
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+ librelane-3.0.0.dev33.dist-info/entry_points.txt,sha256=0eZs2NOH-w-W_GVRCs-ualst26XplkPpJkOnGWMaFw0,306
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+ librelane-3.0.0.dev33.dist-info/RECORD,,