librelane 3.0.0.dev26__py3-none-any.whl → 3.0.0.dev28__py3-none-any.whl

librelane/common/__init__.py

@@ -32,7 +32,7 @@ from .misc import (
     idem,
     get_librelane_root,
     get_script_dir,
-    get_opdks_rev,
+    get_pdk_hash,
     slugify,
     protected,
     final,

librelane/common/metrics/__main__.py

@@ -158,7 +158,8 @@ def _compare_metric_folders(
                 continue
             basename = basename[: -len(".metrics.json")]
 
-            parts = basename.split("-", maxsplit=2)
+            # We have to rsplit, since ihp-sg13g2 contains a "-"
+            parts = basename.rsplit("-", maxsplit=2)
             if len(parts) != 3:
                 raise ValueError(
                     f"Invalid filename {basename}: not in the format {{pdk}}-{{scl}}-{{design_name}}"

librelane/common/misc.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -16,6 +20,7 @@ import os
 import re
 import glob
 import gzip
+import yaml
 import typing
 import pathlib
 import fnmatch
@@ -37,6 +42,7 @@ import httpx
 
 from ..__version__ import __version__
 from .types import AnyPath, Path
+from ..logging import err
 
 T = TypeVar("T")
 
@@ -68,15 +74,21 @@ def get_script_dir() -> str:
     )
 
 
-def get_opdks_rev() -> str:
+def get_pdk_hash(pdk_variant) -> str:
     """
-    Gets the Open_PDKs revision confirmed compatible with this version of LibreLane.
+    Gets the PDK version hash confirmed compatible with this version of LibreLane.
     """
-    return (
-        open(os.path.join(get_librelane_root(), "open_pdks_rev"), encoding="utf8")
-        .read()
-        .strip()
+
+    with open(os.path.join(get_librelane_root(), "pdk_hashes.yaml"), "r") as file:
+        pdk_hashes = yaml.safe_load(file)
+        for pdk_family in pdk_hashes:
+            if pdk_family in pdk_variant:
+                return pdk_hashes[pdk_family]
+
+    err(
+        f"Could not find a PDK family for '{pdk_variant}'. Please specify a PDK manually with '--manual-pdk'."
     )
+    exit(1)
 
 
 # The following code snippet has been adapted under the following license:

librelane/common/tcl.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -68,12 +72,50 @@ class TclUtils(object):
                 if value is not None:
                     env_out[match.group(1)] = value
 
+        def py_dict(command, target=None, *args):
+            if command == "set":
+                if match := _env_rx.fullmatch(target):
+
+                    if len(args) > 1:
+                        value = args[-1]
+                        keys = args[:-1]
+
+                        # Create new dict if it does not exist
+                        if not match.group(1) in env_out:
+                            env_out[match.group(1)] = {}
+
+                        # set ::env(...) [dict create]
+                        # will create an empty string ""
+                        # convert into an empty dictionary
+                        if env_out[match.group(1)] == "":
+                            env_out[match.group(1)] = {}
+
+                        # Set key value pair
+                        cur_dict = env_out[match.group(1)]
+
+                        # Create all nested dicts
+                        for key in keys[:-1]:
+                            if key in cur_dict:
+                                cur_dict = cur_dict[key]
+                            else:
+                                cur_dict[key] = {}
+                                cur_dict = cur_dict[key]
+
+                        # Finally set the value
+                        cur_dict[keys[-1]] = value
+
         py_set_name = interpreter.register(py_set)
+        py_dict_name = interpreter.register(py_dict)
         interpreter.call("rename", py_set_name, "_py_set")
         interpreter.call("rename", "set", "_orig_set")
+        interpreter.call("rename", py_dict_name, "_py_dict")
+        interpreter.call("rename", "dict", "_orig_dict")
         interpreter.eval(
             "proc set args { _py_set {*}$args; tailcall _orig_set {*}$args; }"
         )
+        interpreter.eval(
+            "proc dict args { _py_dict {*}$args; tailcall _orig_dict {*}$args; }"
+        )
 
         interpreter.eval(tcl_in)
 

librelane/config/flow.py

@@ -195,6 +195,13 @@ scl_variables = [
         "Path(s) to cells' SPICE model(s)",
         pdk=True,
     ),
+    Variable(
+        "CELL_CDLS",
+        Optional[List[Path]],
+        description="A circuit-design language view of the standard cell library.",
+        pdk=True,
+        deprecated_names=["STD_CELL_LIBRARY_CDL"],
+    ),
     Variable(
         "SYNTH_EXCLUDED_CELL_FILE",
         Path,
@@ -424,6 +431,11 @@ option_variables = [
         Optional[List[Path]],
         "Specifies miscellaneous SPICE models to be loaded indiscriminately whenever SPICE models are loaded.",
     ),
+    Variable(
+        "EXTRA_CDLS",
+        Optional[List[Path]],
+        "Specifies miscellaneous CDL netlists to be loaded indiscriminately whenever CDL netlists are loaded.",
+    ),
     Variable(
         "EXTRA_LIBS",
         Optional[List[Path]],

librelane/flows/cli.py

@@ -34,7 +34,7 @@ from cloup.constraints import (
 from cloup.typing import Decorator
 
 from .flow import Flow
-from ..common import set_tpe, cli, get_opdks_rev, _get_process_limit
+from ..common import set_tpe, cli, get_pdk_hash, _get_process_limit
 from ..logging import set_log_level, verbose, err, options, LogLevels
 from ..state import State, InvalidState
 
@@ -421,7 +421,7 @@ def cloup_flow_opts(
                     import ciel
                     from ciel.source import StaticWebDataSource
 
-                    opdks_rev = volare_pdk_override or get_opdks_rev()
+                    opdks_rev = volare_pdk_override or get_pdk_hash(pdk)
                     ciel_home = ciel.get_ciel_home(pdk_root)
 
                     include_libraries = ["default"]

librelane/pdk_hashes.yaml

@@ -0,0 +1,3 @@
+sky130: 8afc8346a57fe1ab7934ba5a6056ea8b43078e71
+gf180mcu: 8afc8346a57fe1ab7934ba5a6056ea8b43078e71
+ihp-sg13g2: cb7daaa8901016cf7c5d272dfa322c41f024931f

librelane/scripts/klayout/stream_out.py

@@ -90,6 +90,13 @@ import click
     "input",
     type=click.Path(exists=True, file_okay=True, dir_okay=False),
 )
+@click.option(
+    "--conflict-resolution",
+    "conflict_resolution",
+    type=str,
+    default="RenameCell",
+    help="Cell conflict resolution handling.",
+)
 def stream_out(
     output: str,
     input_lefs: Tuple[str, ...],
@@ -100,6 +107,7 @@ def stream_out(
     seal_gds: Optional[str],
     design_name: str,
     input: str,
+    conflict_resolution: str,
 ):  # Load technology file
     try:
         tech = pya.Technology()
@@ -109,6 +117,22 @@ def stream_out(
         layout_options.lefdef_config.lef_files = list(input_lefs)
         layout_options.lefdef_config.map_file = lym
 
+        cell_conflict_resolution = {
+            "AddToCell": pya.LoadLayoutOptions.CellConflictResolution.AddToCell,
+            "OverwriteCell": pya.LoadLayoutOptions.CellConflictResolution.OverwriteCell,
+            "RenameCell": pya.LoadLayoutOptions.CellConflictResolution.RenameCell,
+            "SkipNewCell": pya.LoadLayoutOptions.CellConflictResolution.SkipNewCell,
+        }.get(conflict_resolution)
+
+        if cell_conflict_resolution is None:
+            print(
+                f"[ERROR] Unknown conflict resolution: '{conflict_resolution}'.",
+                file=sys.stderr,
+            )
+            exit(1)
+        else:
+            layout_options.cell_conflict_resolution = cell_conflict_resolution
+
         # Load def file
         main_layout = pya.Layout()
         # main_layout.load_layer_props(props_file)
@@ -126,7 +150,7 @@ def stream_out(
         # Load in the gds to merge
         print("[INFO] Merging GDS files…")
         for gds in input_gds_files:
-            main_layout.read(gds)
+            main_layout.read(gds, layout_options)
 
         # Copy the top level only to a new layout
         print(f"[INFO] Copying top level cell '{design_name}'…")
@@ -138,7 +162,7 @@ def stream_out(
         print("[INFO] Checking for missing GDS…")
         missing_gds = False
         for i in top_only_layout.each_cell():
-            if i.is_empty():
+            if i.is_ghost_cell():
                 missing_gds = True
                 print(
                     f"[ERROR] LEF Cell '{i.name}' has no matching GDS cell.",

librelane/scripts/magic/extract_spice.tcl

@@ -12,7 +12,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 set f [open $::env(STEP_DIR)/cif_scale.txt "w"]
-puts $f "[magic::i2u 1]"
+puts $f [expr {((round([magic::cif scale output] * 10000)) / 10000.0) * 1}]
 close $f
 
 if { $::env(MAGIC_EXT_USE_GDS) } {

librelane/scripts/openroad/write_cdl.tcl

@@ -0,0 +1,23 @@
+#
+# Write CDL netlist of the current design
+#
+
+# Load design database
+source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
+read_current_odb
+
+# Collect masters CDL
+set masters {}
+
+foreach cdl $::env(CELL_CDLS) {
+    lappend masters $cdl
+}
+
+if { [info exist ::env(EXTRA_CDLS)] } {
+    foreach cdl $::env(EXTRA_CDLS) {
+        lappend masters $cdl
+    }
+}
+
+# Write only the CDL
+write_cdl -include_fillers -masters "$masters" $::env(STEP_DIR)/$::env(DESIGN_NAME).cdl

librelane/scripts/pyosys/json_header.py

@@ -38,7 +38,7 @@ def json_header(
     defines = (
         (config["VERILOG_DEFINES"] or [])
         + [
-            f"PDK_{config['PDK']}",
+            f"PDK_{config['PDK'].replace('-','_')}",
             f"SCL_{config['STD_CELL_LIBRARY']}",
             "__librelane__",
             "__pnr__",

librelane/scripts/pyosys/synthesize.py

@@ -227,7 +227,7 @@ def synthesize(
 
     includes = config.get("VERILOG_INCLUDE_DIRS") or []
     defines = (config.get("VERILOG_DEFINES") or []) + [
-        f"PDK_{config['PDK']}",
+        f"PDK_{config['PDK'].replace('-','_')}",
         f"SCL_{config['STD_CELL_LIBRARY']}",
         "__librelane__",
         "__pnr__",

librelane/state/design_format.py

@@ -239,6 +239,13 @@ DesignFormat(
     alts=["SPICE"],
 ).register()
 
+DesignFormat(
+    "cdl",
+    "cdl",
+    "Circuit Design Language",
+    alts=["CDL"],
+).register()
+
 DesignFormat(
     "gds",
     "gds",

librelane/steps/cvc_rv.py

@@ -16,7 +16,7 @@ import re
 import json
 from enum import Enum
 from io import StringIO, TextIOWrapper
-from typing import List, Optional, Tuple
+from typing import Optional, Tuple
 
 from .step import StepException, ViewsUpdate, MetricsUpdate, Step
 from ..common import Path
@@ -124,13 +124,6 @@ class ERC(Step):
             description="",
             pdk=True,
         ),
-        Variable(
-            "CELL_CDLS",
-            List[Path],
-            description="A circuit-design language view of the standard cell library.",
-            pdk=True,
-            deprecated_names=["STD_CELL_LIBRARY_CDL"],
-        ),
     ]
 
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:

librelane/steps/klayout.py

@@ -1,3 +1,7 @@
+# Copyright 2025 LibreLane Contributors
+#
+# Adapted from OpenLane
+#
 # Copyright 2023 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -19,7 +23,8 @@ import shutil
 import subprocess
 from os.path import abspath
 from base64 import b64encode
-from typing import Any, Dict, Optional, List, Sequence, Tuple, Union
+from tempfile import NamedTemporaryFile
+from typing import Any, Dict, Optional, List, Literal, Sequence, Tuple, Union
 
 from .step import ViewsUpdate, MetricsUpdate, Step, StepError, StepException
 
@@ -196,6 +201,17 @@ class StreamOut(KLayoutStep):
     inputs = [DesignFormat.DEF]
     outputs = [DesignFormat.GDS, DesignFormat.KLAYOUT_GDS]
 
+    config_vars = KLayoutStep.config_vars + [
+        Variable(
+            "KLAYOUT_CONFLICT_RESOLUTION",
+            Optional[
+                Literal["AddToCell", "OverwriteCell", "RenameCell", "SkipNewCell"]
+            ],
+            "Specifies the conflict resolution if a cell name conflict arises.",
+            default="RenameCell",
+        ),
+    ]
+
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         views_updates: ViewsUpdate = {}
 
@@ -218,6 +234,8 @@ class StreamOut(KLayoutStep):
                 abspath(klayout_gds_out),
                 "--top",
                 self.config["DESIGN_NAME"],
+                "--conflict-resolution",
+                self.config["KLAYOUT_CONFLICT_RESOLUTION"],
             ]
             + self.get_cli_args(include_lefs=True, include_gds=True),
             env=env,
@@ -431,10 +449,77 @@ class DRC(KLayoutStep):
         )
         return subprocess_result["generated_metrics"]
 
+    def run_ihp_sg13g2(self, state_in: State, **kwargs) -> MetricsUpdate:
+        kwargs, env = self.extract_env(kwargs)
+
+        drc_script_path = self.config["KLAYOUT_DRC_RUNSET"]
+
+        reports_dir = os.path.join(self.step_dir, "reports")
+        mkdirp(reports_dir)
+        xml_report = os.path.join(reports_dir, "drc_violations.klayout.xml")
+        json_report = os.path.join(reports_dir, "drc_violations.klayout.json")
+
+        input_view = state_in[DesignFormat.GDS]
+        assert isinstance(input_view, Path)
+
+        opts = []
+        for k, v in self.config["KLAYOUT_DRC_OPTIONS"].items():
+            opts.extend(
+                [
+                    "-rd",
+                    f"{k}={v}",
+                ]
+            )
+
+        threads = self.config["KLAYOUT_DRC_THREADS"] or str(_get_process_limit())
+        if threads != "1":
+            opts.extend(
+                [
+                    "-rd",
+                    f"threads={threads}",
+                ]
+            )
+
+        info(f"Running KLayout DRC with {threads} threads…")
+
+        # Not pya script - DRC script is not part of OpenLane
+        self.run_subprocess(
+            [
+                "klayout",
+                "-b",
+                "-zz",
+                "-r",
+                drc_script_path,
+                "-rd",
+                f"in_gds={abspath(input_view)}",
+                "-rd",
+                f"report_file={abspath(xml_report)}",
+                *opts,
+            ]
+        )
+
+        subprocess_result = self.run_pya_script(
+            [
+                "python3",
+                os.path.join(
+                    get_script_dir(),
+                    "klayout",
+                    "xml_drc_report_to_json.py",
+                ),
+                f"--xml-file={abspath(xml_report)}",
+                f"--json-file={abspath(json_report)}",
+            ],
+            env=env,
+            log_to=os.path.join(self.step_dir, "xml_drc_report_to_json.log"),
+        )
+        return subprocess_result["generated_metrics"]
+
     def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
         metrics_updates: MetricsUpdate = {}
         if self.config["PDK"] in ["sky130A", "sky130B"]:
             metrics_updates = self.run_sky130(state_in, **kwargs)
+        elif self.config["PDK"] in ["ihp-sg13g2"]:
+            metrics_updates = self.run_ihp_sg13g2(state_in, **kwargs)
         else:
             self.warn(
                 f"KLayout DRC is not supported for the {self.config['PDK']} PDK. This step will be skipped."
@@ -443,6 +528,126 @@ class DRC(KLayoutStep):
         return {}, metrics_updates
 
 
+@Step.factory.register()
+class LVS(KLayoutStep):
+    id = "KLayout.LVS"
+    name = "Layout Versus Schematic (KLayout)"
+
+    inputs = [
+        DesignFormat.CDL,
+        DesignFormat.GDS,
+    ]
+    outputs = [DesignFormat.SPICE]
+
+    config_vars = KLayoutStep.config_vars + [
+        Variable(
+            "KLAYOUT_LVS_SCRIPT",
+            Optional[Path],
+            "A path to KLayout LVS script.",
+            pdk=True,
+        ),
+        Variable(
+            "KLAYOUT_LVS_OPTIONS",
+            Optional[Dict[str, Union[bool, int, str]]],
+            "Options passed directly to the KLayout LVS script. They vary from one PDK to another.",
+            pdk=True,
+        ),
+    ]
+
+    def run_ihp_sg13g2(
+        self, state_in: State, **kwargs
+    ) -> Tuple[ViewsUpdate, MetricsUpdate]:
+        kwargs, env = self.extract_env(kwargs)
+
+        lvs_script_path = self.config["KLAYOUT_LVS_SCRIPT"]
+
+        reports_dir = os.path.join(self.step_dir, "reports")
+        mkdirp(reports_dir)
+        lvsdb_report = os.path.join(reports_dir, "lvs.klayout.lvsdb")
+
+        input_view_gds = state_in[DesignFormat.GDS]
+        input_view_cdl = state_in[DesignFormat.CDL]
+        assert isinstance(input_view_gds, Path)
+        assert isinstance(input_view_cdl, Path)
+
+        output_spice = os.path.join(
+            self.step_dir,
+            f"{self.config['DESIGN_NAME']}.{DesignFormat.SPICE.value.extension}",
+        )
+
+        with NamedTemporaryFile("w") as f:
+            # Merge all CDL inputs
+            cdl_lst = [input_view_cdl]
+            cdl_lst.extend(self.config["CELL_CDLS"] or [])
+            cdl_lst.extend(self.config["EXTRA_CDLS"] or [])
+
+            for fn in cdl_lst:
+                with open(fn, "r") as cdl_fh:
+                    f.write(cdl_fh.read())
+
+            opts = []
+            for k, v in self.config["KLAYOUT_LVS_OPTIONS"].items():
+                opts.extend(
+                    [
+                        "-rd",
+                        f"{k}={v}",
+                    ]
+                )
+
+            # Not pya script - LVS script is not part of LibreLane
+            subprocess_result = self.run_subprocess(
+                [
+                    "klayout",
+                    "-b",
+                    "-zz",
+                    "-r",
+                    lvs_script_path,
+                    "-rd",
+                    f"input={abspath(input_view_gds)}",
+                    "-rd",
+                    f"schematic={abspath(f.name)}",
+                    "-rd",
+                    f"report={abspath(lvsdb_report)}",
+                    "-rd",
+                    f"target_netlist={abspath(output_spice)}",
+                ]
+                + opts,
+                env=env,
+            )
+
+            with open(subprocess_result["log_path"]) as fh:
+                for line in fh:
+                    if "INFO : Congratulations! Netlists match" in line:
+                        ok = True
+                        break
+                    elif "ERROR : Netlists don't match" in line:
+                        ok = False
+                        break
+                else:
+                    ok = False
+
+        views_updates: ViewsUpdate = {
+            DesignFormat.SPICE: Path(output_spice),
+        }
+        metrics_updates: MetricsUpdate = {
+            "design__lvs_error__count": 0 if ok else 1,
+        }
+
+        return views_updates, metrics_updates
+
+    def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
+        metrics_updates: MetricsUpdate = {}
+        views_updates: ViewsUpdate = {}
+        if self.config["PDK"] in ["ihp-sg13g2"]:
+            views_updates, metrics_updates = self.run_ihp_sg13g2(state_in, **kwargs)
+        else:
+            self.warn(
+                f"KLayout LVS is not supported for the {self.config['PDK']} PDK. This step will be skipped."
+            )
+
+        return views_updates, metrics_updates
+
+
 @Step.factory.register()
 class OpenGUI(KLayoutStep):
     """
@@ -480,7 +685,7 @@ class OpenGUI(KLayoutStep):
 
         layout = state_in[DesignFormat.DEF]
         if self.config["KLAYOUT_GUI_USE_GDS"]:
-            if gds := state_in[DesignFormat.GDS]:
+            if gds := state_in.get(DesignFormat.GDS):
                 layout = gds
         assert isinstance(layout, Path)
 

librelane/steps/openroad.py

@@ -2188,6 +2188,20 @@ class WriteViews(OpenROADStep):
         return os.path.join(get_script_dir(), "openroad", "write_views.tcl")
 
 
+@Step.factory.register()
+class WriteCDL(OpenROADStep):
+    """
+    Write CDL view of an ODB design
+    """
+
+    id = "OpenROAD.WriteCDL"
+    name = "Write CDL"
+    outputs = [DesignFormat.CDL]
+
+    def get_script_path(self):
+        return os.path.join(get_script_dir(), "openroad", "write_cdl.tcl")
+
+
 # Resizer Steps
 
 

librelane/steps/yosys.py

@@ -48,7 +48,7 @@ def _generate_read_deps(
     commands = ""
 
     synth_defines = [
-        f"PDK_{config['PDK']}",
+        f"PDK_{config['PDK'].replace('-','_')}",
         f"SCL_{config['STD_CELL_LIBRARY']}",
         "__librelane__",
         "__pnr__",

{librelane-3.0.0.dev26.dist-info → librelane-3.0.0.dev28.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: librelane
-Version: 3.0.0.dev26
+Version: 3.0.0.dev28
 Summary: An infrastructure for implementing chip design flows
 Home-page: https://github.com/librelane/librelane
 License: Apache-2.0

{librelane-3.0.0.dev26.dist-info → librelane-3.0.0.dev28.dist-info}/RECORD

@@ -1,25 +1,25 @@
 librelane/__init__.py,sha256=EMpoZrRmS_wsweKjhyAg52OXCK7HWQ8o8CVrYaX4ub0,1220
 librelane/__main__.py,sha256=Zq2h2ZTQqA0T7qpGFELJ1bzVQnv-951nnhJ0-9WzNaM,14541
 librelane/__version__.py,sha256=dbE4stCACDmIoxgKksesAkTa-_hi5dW6nPLWw9Pfq3Q,1486
-librelane/common/__init__.py,sha256=QhzRvLXLR2cGdYenayWYmCfgkTS836dWW41Ve1Wa5IE,1551
+librelane/common/__init__.py,sha256=FYBKTUKpAwexQSgCaH_IfbozmDk0hA1ITpl66J8Qcwo,1550
 librelane/common/cli.py,sha256=xi48GBGHRsYrLGwx40ARwpykHx7GnuHbJjHxjOwtZ5Y,2349
 librelane/common/drc.py,sha256=l1quZbHXGb7yjKCO5IFn-Xxf_zIx4f6kxqpNm3YmpOs,12809
 librelane/common/generic_dict.py,sha256=ASa5wtVcLuGlsBqGfLxLYXrYksqQB62iHljV04plIqI,10010
 librelane/common/metrics/__init__.py,sha256=nzdmeia1fN4CDPT604v-OHaBVydz-M4hz232g-jxJ6M,1521
-librelane/common/metrics/__main__.py,sha256=VfoOHFkGXtei6GLkPUD42X6io8QKFCHhxLMWOXPz_5E,12473
+librelane/common/metrics/__main__.py,sha256=1w23V_1-f0WUSfxG36ewNHctgPisQFFG4p-R-wZsyNs,12539
 librelane/common/metrics/library.py,sha256=CG7rubLdjuCQL9-9bzAC-64hf-KlH-iu_Fg0oKuesqs,7373
 librelane/common/metrics/metric.py,sha256=h3Xd26z5M80IJgVmmrBTjKcdGLb4I0wyjM-H4jdyi_0,6990
 librelane/common/metrics/util.py,sha256=Bl_9znlot7-Os2VigYLSmMf56aAkGdv3evWz9vfK7K4,9344
-librelane/common/misc.py,sha256=2zj62QbSuYaD2iYqGnM7vFR3ga41E3TxZpOOBYYIka8,13257
+librelane/common/misc.py,sha256=vjSfFT2KV5TNTxqeLt5EFqcprRrjrgNvgOJpBl7JpM4,13627
 librelane/common/ring_buffer.py,sha256=DGFen9y0JOmiL7E27tmzDTVSJKZtV-waF9hl5Rz9uek,1898
-librelane/common/tcl.py,sha256=G0__oR6azVCS2Aue87zboba7vAR7v-SVQeUbqfviiDA,2709
+librelane/common/tcl.py,sha256=AfTxbSLA0VUXVMMwoAQndyQTcEZQoQfMa4FFizZiEgU,4341
 librelane/common/toolbox.py,sha256=ijR__rVqQ_nJtfm34H-VdSCIeArKns7lVAc1TcTUSsQ,20975
 librelane/common/tpe.py,sha256=Txj0fVscXSDJTYmEKZ2ESFHOeqrhHnaPPiwWBgyx4g8,1285
 librelane/common/types.py,sha256=xo_OKq-2ue7JVpyQb6oUu6JuVSnLNEFKQCPBqNhZnQ4,3509
 librelane/config/__init__.py,sha256=lbJmD5CbrrrnaNdIUWqFIK488ea0uyej3iExh-9mkgE,1107
 librelane/config/__main__.py,sha256=NsJGoIOb950mdXql1zmzSq10wuFovK9NGWm011NNJ3A,4474
 librelane/config/config.py,sha256=bAxB0qpw95YoLGmMjvxAwrX1hcpHRvNhH7wjQdyW-DE,35031
-librelane/config/flow.py,sha256=RS8uspcrepl8GT5SsWrBQ-kmssO4c15_lrc2nBPVK5M,16482
+librelane/config/flow.py,sha256=DLB1h3UX_0cWgJblAmCSrsWL6dV0SEx0mz4ohIsV2uo,16892
 librelane/config/pdk_compat.py,sha256=ofqYuD-MgTcfvPVXpGJo8H1GKzCvN6sxHsK_OqCVXa8,12870
 librelane/config/preprocessor.py,sha256=ATi29SHz0_OBq1IqUkGxvhHUDKB5z5jO0KqvoQXg8R8,14913
 librelane/config/removals.py,sha256=vxqTuRTJ0jt2TX4KmFZCZPTwghDFkCVjIhF2iReHwJA,2958
@@ -42,7 +42,7 @@ librelane/examples/spm-user_project_wrapper/user_project_wrapper.v,sha256=zc6GC5
 librelane/flows/__init__.py,sha256=ghtmUG-taVpHJ3CKJRYZGn3dU0r93araT1EIGlBEsxg,896
 librelane/flows/builtins.py,sha256=tR14Qc1ZUey2w-Ar4DWOvxuP7LGPtMecCJq8WgcYJpk,773
 librelane/flows/classic.py,sha256=JB9gVgP2hHPhMuCJg7hvoj2BvJcvRec7suEXPgHmz14,10971
-librelane/flows/cli.py,sha256=P2LCFn5_RQ88yB0WuetpLAuWeKQXd-DrpCOMgnVh9Mg,16705
+librelane/flows/cli.py,sha256=_aJjlalCsmUeLiqy1D8VFmBJ0dLelx24erqaK2q-AOs,16706
 librelane/flows/flow.py,sha256=qly_ENbw8zHSS6ubUY56JrCRjKnfuSoN78suz1k4chw,36997
 librelane/flows/misc.py,sha256=32Om3isexesfKKiJZCajNmINc-xdv7eVx_tgoh9SR6U,2015
 librelane/flows/optimizing.py,sha256=OwZz6WGmXpliwO8vtmhjKHD-kzDyNv-zoCECZIigXsI,6076
@@ -50,14 +50,14 @@ librelane/flows/sequential.py,sha256=kBpR9kxfEfdTaNy9Ter2KNQXkW6qojCwoBsFJBwTq6I
 librelane/flows/synth_explore.py,sha256=8mpeuG6oxeEXVQi4NwS4I415eCu7Ak6DN4oK30h1eCQ,7418
 librelane/logging/__init__.py,sha256=mrTnzjpH6AOu2CiDZYfOMCVByAS2Xeg9HS4FJyXsJOE,1043
 librelane/logging/logger.py,sha256=kA61TGsR00Fi6kQSxgTC1pHpS_-zqC1PdQnYqnk2TWY,8632
-librelane/open_pdks_rev,sha256=_q6FiO0UljepWU99r9IgkbLrKLDIPbO-80--OFWrZxA,41
+librelane/pdk_hashes.yaml,sha256=wHPz6Ze4e1uhZTo7IKS4wcmU6ShcZdBtHcdACP5tYNI,153
 librelane/plugins.py,sha256=G5o2h1LT4a1LO1Q0gKXXuhqcEdjdTFkYU8QUSg2D2eM,820
 librelane/py.typed,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 librelane/scripts/base.sdc,sha256=zGPSBLDt-5dbYvm3AGbjsZsyKxjFOc4znyjwZM4wIps,3145
 librelane/scripts/klayout/Readme.md,sha256=hJs44QIB3lHPD3E-Z-tbAC1RBmt5Fl1khzQF2gRewLE,76
 librelane/scripts/klayout/open_design.py,sha256=0cBELVhSBGmp_KxDN0vsCEh6x1JPW0Q6cXkBd3S-XKk,2395
 librelane/scripts/klayout/render.py,sha256=FH-rp7Q363T0gD9_p-n4_suya4hfAPzL2jZIF0fmLwA,3833
-librelane/scripts/klayout/stream_out.py,sha256=0GALkaKkrjcnASng32Fxq93dsgC9Fi4Rr_qRBT-eFGU,5867
+librelane/scripts/klayout/stream_out.py,sha256=MLpe0oGl7oy2bD4ddk0ixRJgsiBUDzEv_UPwYspgT3s,6796
 librelane/scripts/klayout/xml_drc_report_to_json.py,sha256=6nwTymQ1ypA5OgSvqySxzIWqDgGlW_1tlbtauc0BUdE,1412
 librelane/scripts/klayout/xor.drc,sha256=Nm_6JR_png-31uajL3DrW3dVGo7Kd6G-zS9RTftL25o,3131
 librelane/scripts/magic/Readme.md,sha256=NaQrlxY8l8GT-kokJNlMHeAR3PksWVbFpSznOWWshhw,126
@@ -66,7 +66,7 @@ librelane/scripts/magic/def/antenna_check.tcl,sha256=T_r1CWgySFVlLMcoTrNXQ_aMRs_
 librelane/scripts/magic/def/mag.tcl,sha256=PuL3MH6pmZP5Qh2cJ0GygWNzaYjdCSCoAbOli-JB4fs,707
 librelane/scripts/magic/def/mag_gds.tcl,sha256=fwtQR9zPZpWqVmmLb-1hzY4WMCr4gbA3S0pTZsS9sss,2144
 librelane/scripts/magic/drc.tcl,sha256=gPGyI96lR10dJXcJACajzHaHiT6ayAYPJqrmmuQkABc,2395
-librelane/scripts/magic/extract_spice.tcl,sha256=lFNXfjIIzAWb2wda9ZtBOecENOOXyFBsh9HgrPYf7VQ,2737
+librelane/scripts/magic/extract_spice.tcl,sha256=-jDxVEGddch1YZLZXW1vFXhdLkeTjxk0d8eU1tBMBWc,2788
 librelane/scripts/magic/gds/drc_batch.tcl,sha256=O76rwxSrQgoCuoxk36tRBZkQaeMfJknlHrQA3mtU2JU,2198
 librelane/scripts/magic/gds/erase_box.tcl,sha256=wsVSwMlkZFJa_MEGNsdXLnXFvjZlrl_lzIWkJjcDBgg,929
 librelane/scripts/magic/gds/extras_mag.tcl,sha256=1raG0URUezUDEKkdDeJqdlS0Y5gb4IzQFnjFysHHlmU,1304
@@ -138,34 +138,35 @@ librelane/scripts/openroad/sta/check_macro_instances.tcl,sha256=j8DlW1wkVk5bLbG7
 librelane/scripts/openroad/sta/corner.tcl,sha256=0YAzHFGbs4zRsB5E7e8zdzFyLuzrpV1w_S2BgrLfqak,15235
 librelane/scripts/openroad/tapcell.tcl,sha256=4Ouy5U-_ct5Cfy3vuLQudWL0c1xWF_auLsr9rYh6dP4,1177
 librelane/scripts/openroad/ungpl.tcl,sha256=vhHxou1W3VROwJePoQzmWn0h0d5lQrrt1vofyt-Woek,761
+librelane/scripts/openroad/write_cdl.tcl,sha256=uPO1IROPTr5NrW0-VZA8tXQD8aseGeXDXDsU8TX-9nQ,460
 librelane/scripts/openroad/write_views.tcl,sha256=-MxTJsB4EF7l5trDaZe-VBFjhfzqRt8F5_DZrADTs0U,892
 librelane/scripts/pyosys/construct_abc_script.py,sha256=3CCDz5ZTEPpWLco-OvikTmn361-BNitqjQE_-5zHm14,6733
-librelane/scripts/pyosys/json_header.py,sha256=C1BmKFRbwMknXV_RVp5QGbAxCwU6ElE6UIGRZceHQpI,2315
-librelane/scripts/pyosys/synthesize.py,sha256=2NZWdtskSRGUGghYLkw-LGdEH_IL9Vfl3NUD2GR3Kdk,16910
+librelane/scripts/pyosys/json_header.py,sha256=gKla0V4tFhF5fR-zzudrTr6TjpqkV3c69PWk1fVfMgg,2332
+librelane/scripts/pyosys/synthesize.py,sha256=soDbOObGdCix3zDUQFIF6FvZn6_mT_GonkvH5exGQiA,16927
 librelane/scripts/pyosys/ys_common.py,sha256=t5LLEYoy4cfCIeEaAo8Nr51rXtlI8ZPe1h_kSbrky5M,3891
 librelane/scripts/tclsh/hello.tcl,sha256=kkR3akY7QnGHYXsQODYwLkMkUEOgWcNFtzaMTTEV2bY,34
 librelane/state/__init__.py,sha256=DZ_RyKMr2oj4p5d32u8MmDKfCxR7OEdDw-1HWKTpatA,949
 librelane/state/__main__.py,sha256=Ici4Ejg1ICUZNSYZRguC3BfEk_wFxsmE0ag0Vv8iY1I,1679
-librelane/state/design_format.py,sha256=75-XXzCfk5HUAJQAcdpwiHYkweeR9NwaXKtubCV0dqg,6461
+librelane/state/design_format.py,sha256=v1Nj-glM3Nc6SVXMZKanAMiaBjgDnW8KjAlmr_TiOqk,6560
 librelane/state/state.py,sha256=tYn2si8NlkVErOSWKfVhsgrMpyxeX2Hv9EAPsQBWx2c,11902
 librelane/steps/__init__.py,sha256=j3JYrdnWM74dYuEvE931oSrQI7FUz-hKWr8Mts8C0wg,1668
 librelane/steps/__main__.py,sha256=GQZiV4s-9GIF4AwP34W61zwgzMvPp-QTR4cNELi7r5c,13349
 librelane/steps/checker.py,sha256=HD5YFPAbHQKsFmBDrIAbo_0clZcCszNhIXb4lHaNIeQ,21629
 librelane/steps/common_variables.py,sha256=eih2eA1m0FpL8ydF5WWattwh_SxtzI55eb8gggJtBuY,12494
-librelane/steps/cvc_rv.py,sha256=TNnEQDJI5tEUq8OQelVmBWmNbLzygrvKsZ36utKDvp4,5543
-librelane/steps/klayout.py,sha256=EFtzu53bWm-Bg_xEovdR7fc1GbWTwqkcivtr1rivHWU,16615
+librelane/steps/cvc_rv.py,sha256=qeroQPjidSAMYSp3nJNiQBYt8V73kkz3JK97uioo7J8,5294
+librelane/steps/klayout.py,sha256=18B7trKjyD8HnGUVwrjQV8XRzGu298CuosM1WOzg9oM,23255
 librelane/steps/magic.py,sha256=m4cZH2VomJs0RudtV8avSaZVqRj1NP7Pm2P6qo2z2X0,20919
 librelane/steps/misc.py,sha256=8ubCvFeFEspXrgnzNWINY5-TXTyalNtlvcX8TSw0qdg,5685
 librelane/steps/netgen.py,sha256=R9sDWv-9wKMdi2rkuLQdOc4uLlbYhXcKKd6WsZsnLt0,8953
 librelane/steps/odb.py,sha256=-zsXi0jVdtfBfAJI0OC4x1jI_B2OX5YVn4uAn6NyFdk,38424
-librelane/steps/openroad.py,sha256=0wA8-fvtIDbaSteh8lY_VxW7cF_73MdNKqTvWc7Blf4,99284
+librelane/steps/openroad.py,sha256=hgpqsVQi7tFRlj75zefQkD3Vdmq21ubZAFWyU12WxUg,99586
 librelane/steps/openroad_alerts.py,sha256=IJyB4piBDCKXhkJswHGMYCRDwbdQsR0GZlrGGDhmW6Q,3364
 librelane/steps/pyosys.py,sha256=LY7qqxkhjfoyBBR7vdkm7ylabbxMJDwIoYm7mAUbLVY,23348
 librelane/steps/step.py,sha256=THIxZkhtkNYt1iRgMduD0ywrOTCaV7cCfUB2EqXN6-k,55751
 librelane/steps/tclstep.py,sha256=8-zpYOo562E86nm7f4DiTqUsLKY0AFtEJgrp9CnWWDw,10083
 librelane/steps/verilator.py,sha256=MWx2TpLqYyea9_jSeLG9c2S5ujvYERQZRFNaMhfHxZE,7916
-librelane/steps/yosys.py,sha256=uC72fb1yFXyIxrtcRu5DxxR3hadG19SlGh668yjhWHc,12694
-librelane-3.0.0.dev26.dist-info/METADATA,sha256=ndJNvx1YIso3n8GZhhQLFStMDVNpsjMTJ562JZGLULs,6561
-librelane-3.0.0.dev26.dist-info/WHEEL,sha256=Nq82e9rUAnEjt98J6MlVmMCZb-t9cYE2Ir1kpBmnWfs,88
-librelane-3.0.0.dev26.dist-info/entry_points.txt,sha256=GTBvXykNMMFsNKiJFgtEw7P1wb_VZIqVM35EFSpyZQE,263
-librelane-3.0.0.dev26.dist-info/RECORD,,
+librelane/steps/yosys.py,sha256=lYdZPFvjcmdu_NE6rtB94_dysIK2qwGdGb480W6pg2w,12711
+librelane-3.0.0.dev28.dist-info/METADATA,sha256=G4c7el3lW3tANOTRs4enKF5MHT-YYMOrBeLpARSsmIw,6561
+librelane-3.0.0.dev28.dist-info/WHEEL,sha256=Nq82e9rUAnEjt98J6MlVmMCZb-t9cYE2Ir1kpBmnWfs,88
+librelane-3.0.0.dev28.dist-info/entry_points.txt,sha256=GTBvXykNMMFsNKiJFgtEw7P1wb_VZIqVM35EFSpyZQE,263
+librelane-3.0.0.dev28.dist-info/RECORD,,

librelane/open_pdks_rev

@@ -1 +0,0 @@
-0fe599b2afb6708d281543108caf8310912f54af