librelane 3.0.0.dev23__py3-none-any.whl → 3.0.0.dev25__py3-none-any.whl

librelane/config/__main__.py

@@ -14,7 +14,6 @@
 import os
 import sys
 import json
-import functools
 from decimal import Decimal
 
 import click
@@ -111,9 +110,7 @@ def create_config(
                 print("At least one source RTL file is required.", file=sys.stderr)
                 exit(1)
     source_rtl_key = "VERILOG_FILES"
-    if not functools.reduce(
-        lambda acc, x: acc and (x.endswith(".sv") or x.endswith(".v")), source_rtl, True
-    ):
+    if not all((file.endswith(".sv") or file.endswith(".v")) for file in source_rtl):
         print(
             "Only Verilog/SystemVerilog files are supported by create-config.",
             file=sys.stderr,

librelane/config/removals.py

@@ -42,4 +42,5 @@ removed_variables: Dict[str, str] = {
     "FP_PADFRAME_CFG": "To be implemented.",
     "FP_CONTEXT_DEF": "To be implemented.",
     "FP_CONTEXT_LEF": "To be implemented.",
+    "SYNLIG_DEFER": "Synlig replaced with Slang.",
 }

librelane/config/variable.py

@@ -575,7 +575,7 @@ class Variable:
             kwargs_dict = {}
             for current_field in fields(validating_type):
                 key = current_field.name
-                subtype = current_field.type
+                subtype: Type[Any] = current_field.type  # type: ignore
                 explicitly_specified = False
                 if key in raw:
                     explicitly_specified = True

librelane/examples/spm/config.yaml

@@ -7,16 +7,16 @@ PNR_SDC_FILE: dir::src/impl.sdc
 SIGNOFF_SDC_FILE: dir::src/signoff.sdc
 
 # PDN
-FP_PDN_VOFFSET: 5
-FP_PDN_HOFFSET: 5
-FP_PDN_VWIDTH: 2
-FP_PDN_HWIDTH: 2
-FP_PDN_VPITCH: 30
-FP_PDN_HPITCH: 30
-FP_PDN_SKIPTRIM: true
+PDN_VOFFSET: 5
+PDN_HOFFSET: 5
+PDN_VWIDTH: 2
+PDN_HWIDTH: 2
+PDN_VPITCH: 30
+PDN_HPITCH: 30
+PDN_SKIPTRIM: true
 
 # Pin Order
-FP_PIN_ORDER_CFG: dir::pin_order.cfg
+IO_PIN_ORDER_CFG: dir::pin_order.cfg
 
 # Technology-Specific Configs
 pdk::sky130*:

librelane/examples/spm-user_project_wrapper/config.json

@@ -1,13 +1,25 @@
 {
     "DESIGN_NAME": "SPM_example",
-    "VERILOG_FILES": ["dir::./defines.v", "dir::./SPM_example.v"],
+    "VERILOG_FILES": [
+        "dir::./defines.v",
+        "dir::./SPM_example.v"
+    ],
     "CLOCK_PERIOD": 25,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_NET": "SPM.clk",
     "RT_MAX_LAYER": "met4",
     "FP_SIZING": "absolute",
-    "VDD_NETS": ["vccd1"],
-    "GND_NETS": ["vssd1"],
-    "FP_PDN_MULTILAYER": false,
-    "DIE_AREA": [0, 0, 600, 600]
+    "VDD_NETS": [
+        "vccd1"
+    ],
+    "GND_NETS": [
+        "vssd1"
+    ],
+    "PDN_MULTILAYER": false,
+    "DIE_AREA": [
+        0,
+        0,
+        600,
+        600
+    ]
 }

librelane/scripts/odbpy/reader.py

@@ -166,7 +166,7 @@ class OdbReader(object):
         grt.setMinLayerForClock(min_clk_idx)
         grt.setMaxLayerForClock(max_clk_idx)
         grt.setMacroExtension(self.config["GRT_MACRO_EXTENSION"])
-        grt.setOverflowIterations(self.config["GRT_OVERFLOW_ITERS"])
+        grt.setCongestionIterations(self.config["GRT_OVERFLOW_ITERS"])
         grt.setAllowCongestion(self.config["GRT_ALLOW_CONGESTION"])
         grt.setVerbose(True)
         grt.initFastRoute(min_layer_idx, max_layer_idx)

librelane/scripts/openroad/common/io.tcl

@@ -99,23 +99,35 @@ proc read_pdn_cfg {} {
 
     # Compatibility Layer for Deprecated Variables That May Still Be Used By
     # User Files
-    set ::env(DESIGN_IS_CORE) $::env(FP_PDN_MULTILAYER)
-    set ::env(FP_PDN_ENABLE_MACROS_GRID) $::env(PDN_CONNECT_MACROS_TO_GRID)
-    set ::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_RAIL_LAYER)
-    set ::env(FP_PDN_UPPER_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)
-    set ::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_VERTICAL_LAYER)
+    set unset_list {
+        DESIGN_IS_CORE
+        PDN_ENABLE_MACROS_GRID
+        PDN_RAILS_LAYER
+        PDN_UPPER_LAYER
+        PDN_LOWER_LAYER
+    }
+    set ::env(DESIGN_IS_CORE) $::env(PDN_MULTILAYER)
+    set ::env(PDN_ENABLE_MACROS_GRID) $::env(PDN_CONNECT_MACROS_TO_GRID)
+    set ::env(PDN_RAILS_LAYER) $::env(PDN_RAIL_LAYER)
+    set ::env(PDN_UPPER_LAYER) $::env(PDN_HORIZONTAL_LAYER)
+    set ::env(PDN_LOWER_LAYER) $::env(PDN_VERTICAL_LAYER)
+    foreach key [array names ::env] {
+        if { [string match PDN_* $key] } {
+            set fp_name FP_$key
+            lappend unset_list $fp_name
+            set ::env($fp_name) $::env($key)
+        }
+    }
 
-    if {[catch {source $::env(FP_PDN_CFG)} errmsg]} {
+    if {[catch {source $::env(PDN_CFG)} errmsg]} {
         puts stderr $errmsg
         exit 1
     }
 
     # Restore Environment
-    unset ::env(DESIGN_IS_CORE)
-    unset ::env(FP_PDN_ENABLE_MACROS_GRID)
-    unset ::env(FP_PDN_RAILS_LAYER)
-    unset ::env(FP_PDN_UPPER_LAYER)
-    unset ::env(FP_PDN_LOWER_LAYER)
+    foreach unsettable $unset_list {
+        unset ::env($unsettable)
+    }
 }
 
 
@@ -174,9 +186,9 @@ proc read_timing_info {args} {
     foreach nl $::env(_CURRENT_CORNER_NETLISTS) {
         puts "Reading macro netlist at '$nl'…"
         if { [catch {read_verilog $nl} err] } {
-            puts "Error while reading macro netlist '$nl':"
-            puts $err
-            puts "Make sure that this a gate-level netlist and not an RTL file."
+            puts stderr "Error while reading macro netlist '$nl':"
+            puts stderr $err
+            puts stderr "Make sure that this a gate-level netlist and not an RTL file."
             exit 1
         }
     }
@@ -185,9 +197,9 @@ proc read_timing_info {args} {
             if { [string_in_file $verilog_file $blackbox_wildcard] } {
                 puts "Found '$blackbox_wildcard' in '$verilog_file', skipping…"
             } elseif { [catch {puts "Reading Verilog model at '$verilog_file'…"; read_verilog $verilog_file} err] } {
-                puts "Error while reading $verilog_file:"
-                puts $err
-                puts "Make sure that this a gate-level netlist and not an RTL file, otherwise, you can add the following comment '$blackbox_wildcard' in the file to skip it and blackbox the modules inside if needed."
+                puts stderr "Error while reading $verilog_file:"
+                puts stderr $err
+                puts stderr "Make sure that this a gate-level netlist and not an RTL file, otherwise, you can add the following comment '$blackbox_wildcard' in the file to skip it and blackbox the modules inside if needed."
                 exit 1
             }
         }
@@ -411,6 +423,13 @@ proc write_views {args} {
         write_verilog $::env(SAVE_NL)
     }
 
+    if { [info exists ::env(SAVE_LOGICAL_NL)] } {
+        puts "Writing logic-only netlist to '$::env(SAVE_LOGICAL_NL)'…"
+        write_verilog\
+            -remove_cells "[get_physical_cells]"\
+            $::env(SAVE_LOGICAL_NL)
+    }
+
     if { [info exists ::env(SAVE_PNL)] } {
         puts "Writing powered netlist to '$::env(SAVE_PNL)'…"
         write_verilog -include_pwr_gnd $::env(SAVE_PNL)
@@ -575,7 +594,8 @@ proc get_layers {args} {
         flags {-constrained}
 
     if { ![info exists keys(-types)] } {
-        puts "\[ERROR\] Invalid usage of get_layers: -types is required."
+        puts stderr "\[ERROR\] Invalid usage of get_layers: -types is required."
+        return -code error
     }
 
     set layers [$::tech getLayers]

librelane/scripts/openroad/common/pdn_cfg.tcl

@@ -43,83 +43,83 @@ foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
 set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
     -secondary_power $secondary
 
-if { $::env(FP_PDN_MULTILAYER) == 1 } {
+if { $::env(PDN_MULTILAYER) == 1 } {
     define_pdn_grid \
         -name stdcell_grid \
         -starts_with POWER \
         -voltage_domain CORE \
-        -pins "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
+        -pins "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
 
     add_pdn_stripe \
         -grid stdcell_grid \
-        -layer $::env(FP_PDN_VERTICAL_LAYER) \
-        -width $::env(FP_PDN_VWIDTH) \
-        -pitch $::env(FP_PDN_VPITCH) \
-        -offset $::env(FP_PDN_VOFFSET) \
-        -spacing $::env(FP_PDN_VSPACING) \
+        -layer $::env(PDN_VERTICAL_LAYER) \
+        -width $::env(PDN_VWIDTH) \
+        -pitch $::env(PDN_VPITCH) \
+        -offset $::env(PDN_VOFFSET) \
+        -spacing $::env(PDN_VSPACING) \
         -starts_with POWER -extend_to_core_ring
 
     add_pdn_stripe \
         -grid stdcell_grid \
-        -layer $::env(FP_PDN_HORIZONTAL_LAYER) \
-        -width $::env(FP_PDN_HWIDTH) \
-        -pitch $::env(FP_PDN_HPITCH) \
-        -offset $::env(FP_PDN_HOFFSET) \
-        -spacing $::env(FP_PDN_HSPACING) \
+        -layer $::env(PDN_HORIZONTAL_LAYER) \
+        -width $::env(PDN_HWIDTH) \
+        -pitch $::env(PDN_HPITCH) \
+        -offset $::env(PDN_HOFFSET) \
+        -spacing $::env(PDN_HSPACING) \
         -starts_with POWER -extend_to_core_ring
 
     add_pdn_connect \
         -grid stdcell_grid \
-        -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
+        -layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
 } else {
     define_pdn_grid \
         -name stdcell_grid \
         -starts_with POWER \
         -voltage_domain CORE \
-        -pins $::env(FP_PDN_VERTICAL_LAYER)
+        -pins $::env(PDN_VERTICAL_LAYER)
 
     add_pdn_stripe \
         -grid stdcell_grid \
-        -layer $::env(FP_PDN_VERTICAL_LAYER) \
-        -width $::env(FP_PDN_VWIDTH) \
-        -pitch $::env(FP_PDN_VPITCH) \
-        -offset $::env(FP_PDN_VOFFSET) \
-        -spacing $::env(FP_PDN_VSPACING) \
+        -layer $::env(PDN_VERTICAL_LAYER) \
+        -width $::env(PDN_VWIDTH) \
+        -pitch $::env(PDN_VPITCH) \
+        -offset $::env(PDN_VOFFSET) \
+        -spacing $::env(PDN_VSPACING) \
         -starts_with POWER -extend_to_core_ring
 }
 
 # Adds the standard cell rails if enabled.
-if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
+if { $::env(PDN_ENABLE_RAILS) == 1 } {
     add_pdn_stripe \
         -grid stdcell_grid \
-        -layer $::env(FP_PDN_RAIL_LAYER) \
-        -width $::env(FP_PDN_RAIL_WIDTH) \
-        -followpins \
-        -starts_with POWER
+        -layer $::env(PDN_RAIL_LAYER) \
+        -width $::env(PDN_RAIL_WIDTH) \
+        -followpins
 
     add_pdn_connect \
         -grid stdcell_grid \
-        -layers "$::env(FP_PDN_RAIL_LAYER) $::env(FP_PDN_VERTICAL_LAYER)"
+        -layers "$::env(PDN_RAIL_LAYER) $::env(PDN_VERTICAL_LAYER)"
 }
 
 
 # Adds the core ring if enabled.
-if { $::env(FP_PDN_CORE_RING) == 1 } {
-    if { $::env(FP_PDN_MULTILAYER) == 1 } {
+if { $::env(PDN_CORE_RING) == 1 } {
+    if { $::env(PDN_MULTILAYER) == 1 } {
         add_pdn_ring \
+            -allow_out_of_die \
             -grid stdcell_grid \
-            -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)" \
-            -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
-            -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
-            -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
+            -layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)" \
+            -widths "$::env(PDN_CORE_RING_VWIDTH) $::env(PDN_CORE_RING_HWIDTH)" \
+            -spacings "$::env(PDN_CORE_RING_VSPACING) $::env(PDN_CORE_RING_HSPACING)" \
+            -core_offset "$::env(PDN_CORE_RING_VOFFSET) $::env(PDN_CORE_RING_HOFFSET)"
     } else {
-        throw APPLICATION "FP_PDN_CORE_RING cannot be used when FP_PDN_MULTILAYER is set to false."
+        throw APPLICATION "PDN_CORE_RING cannot be used when PDN_MULTILAYER is set to false."
         # add_pdn_ring \
         #     -grid stdcell_grid \
-        #     -layers "$::env(FP_PDN_VERTICAL_LAYER)" \
-        #     -widths "$::env(FP_PDN_CORE_RING_VWIDTH)" \
-        #     -spacings "$::env(FP_PDN_CORE_RING_VSPACING)" \
-        #     -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET)"
+        #     -layers "$::env(PDN_VERTICAL_LAYER)" \
+        #     -widths "$::env(PDN_CORE_RING_VWIDTH)" \
+        #     -spacings "$::env(PDN_CORE_RING_VSPACING)" \
+        #     -core_offset "$::env(PDN_CORE_RING_VOFFSET)"
     }
 }
 
@@ -128,8 +128,8 @@ define_pdn_grid \
     -default \
     -name macro \
     -starts_with POWER \
-    -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+    -halo "$::env(PDN_HORIZONTAL_HALO) $::env(PDN_VERTICAL_HALO)"
 
 add_pdn_connect \
     -grid macro \
-    -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
+    -layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"

librelane/scripts/openroad/common/set_global_connections.tcl

@@ -56,7 +56,7 @@ proc set_global_connections {} {
                 }
             }
             if { $matched != 1 } {
-                puts "\[ERROR\] No match found for regular expression '$instance_name' defined in PDN_MACRO_CONNECTIONS."
+                puts stderr "\[ERROR\] No match found for regular expression '$instance_name' defined in PDN_MACRO_CONNECTIONS."
                 exit_unless_gui 1
             }
 

librelane/scripts/openroad/drt.tcl

@@ -17,8 +17,8 @@ proc drt_run {i args} {
     set output_drc "-output_drc $::env(STEP_DIR)/$directory/$::env(DESIGN_NAME).drc"
     log_cmd detailed_route {*}$args {*}$output_drc
     if { $::env(DRT_SAVE_SNAPSHOTS) } {
-        foreach snapshot [glob -nocomplain drt_iter*.odb] {
-            file rename -force $snapshot $directory/[file tail $snapshot]
+        foreach snapshot [glob -nocomplain $::env(STEP_DIR)/drt_iter*.odb] {
+            file rename -force $snapshot $::env(STEP_DIR)/$directory/[file tail $snapshot]
         }
     }
     foreach drc_file [glob -nocomplain $::env(STEP_DIR)/$directory/*.drc] {
@@ -41,13 +41,11 @@ set max_layer $::env(RT_MAX_LAYER)
 if { [info exists ::env(DRT_MAX_LAYER)] } {
     set max_layer $::env(DRT_MAX_LAYER)
 }
-if { $::env(DRT_SAVE_SNAPSHOTS) } {
-    set_debug_level DRT snapshot 1
-}
 set drc_report_iter_step_arg ""
 if { $::env(DRT_SAVE_SNAPSHOTS) } {
     set_debug_level DRT snapshot 1
     set drc_report_iter_step_arg "-drc_report_iter_step 1"
+    detailed_route_debug -snapshot_dir "$::env(STEP_DIR)/$directory"
 }
 if { [info exists ::env(DRT_SAVE_DRC_REPORT_ITERS)] } {
     set drc_report_iter_step_arg "-drc_report_iter_step $::env(DRT_SAVE_DRC_REPORT_ITERS)"

librelane/scripts/openroad/floorplan.tcl

@@ -33,10 +33,18 @@ puts "Using site height: $::default_site_height and site width: $::default_site_
 
 unset_propagated_clock [all_clocks]
 
-set bottom_margin  [expr $::default_site_height * $::env(BOTTOM_MARGIN_MULT)]
-set top_margin  [expr $::default_site_height * $::env(TOP_MARGIN_MULT)]
-set left_margin [expr $::default_site_width * $::env(LEFT_MARGIN_MULT)]
-set right_margin [expr $::default_site_width * $::env(RIGHT_MARGIN_MULT)]
+proc set_margin {var site_dimension mult} {
+    set value [expr $site_dimension * $mult]
+    if { $value < 0 } {
+        puts stderr "\[ERROR IFP-0013\] Negative values not allowed for margins."
+        exit_unless_gui 1
+    }
+    uplevel 1 set "$var $value"
+}
+set_margin bottom_margin $::default_site_height $::env(BOTTOM_MARGIN_MULT)
+set_margin top_margin $::default_site_height $::env(TOP_MARGIN_MULT)
+set_margin left_margin $::default_site_width $::env(LEFT_MARGIN_MULT)
+set_margin right_margin $::default_site_width $::env(RIGHT_MARGIN_MULT)
 
 set arg_list [list]
 

librelane/scripts/openroad/ioplacer.tcl

@@ -15,50 +15,51 @@ source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 read_current_odb
 
 if { [info exists ::env(CONTEXTUAL_IO_FLAG)] } {
-	read_lef $::env(placement_tmpfiles)/top_level.lef
+    read_lef $::env(placement_tmpfiles)/top_level.lef
 }
 
-if { [info exists ::env(FP_IO_HLENGTH)] } {
-	set_pin_length -hor_length $::env(FP_IO_HLENGTH)
+if { [info exists ::env(IO_PIN_H_LENGTH)] } {
+    set_pin_length -hor_length $::env(IO_PIN_H_LENGTH)
 }
 
-if { [info exists ::env(FP_IO_VLENGTH)] } {
-	set_pin_length -ver_length $::env(FP_IO_VLENGTH)
+if { [info exists ::env(IO_PIN_V_LENGTH)] } {
+    set_pin_length -ver_length $::env(IO_PIN_V_LENGTH)
 }
 
-if { $::env(FP_IO_HEXTEND) != "0"} {
-	set_pin_length_extension -hor_extension $::env(FP_IO_HEXTEND)
+if { $::env(IO_PIN_H_EXTENSION) != "0"} {
+    set_pin_length_extension -hor_extension $::env(IO_PIN_H_EXTENSION)
 }
 
-if { $::env(FP_IO_VEXTEND) != "0"} {
-	set_pin_length_extension -ver_extension $::env(FP_IO_VEXTEND)
+if { $::env(IO_PIN_V_EXTENSION) != "0"} {
+    set_pin_length_extension -ver_extension $::env(IO_PIN_V_EXTENSION)
 }
 
-if {$::env(FP_IO_VTHICKNESS_MULT) != "" && $::env(FP_IO_HTHICKNESS_MULT) != ""} {
-	set_pin_thick_multiplier -hor_multiplier $::env(FP_IO_HTHICKNESS_MULT) \
-		-ver_multiplier $::env(FP_IO_VTHICKNESS_MULT)
+if {$::env(IO_PIN_V_THICKNESS_MULT) != "" && $::env(IO_PIN_H_THICKNESS_MULT) != ""} {
+    set_pin_thick_multiplier\
+        -hor_multiplier $::env(IO_PIN_H_THICKNESS_MULT) \
+        -ver_multiplier $::env(IO_PIN_V_THICKNESS_MULT)
 }
 
 set arg_list [list]
-if { $::env(FP_PPL_MODE) == "random_equidistant" } {
-	lappend arg_list -random
+if { $::env(IO_PIN_PLACEMENT_MODE) == "random_equidistant" } {
+    lappend arg_list -random
 }
 
-if { [info exists ::env(FP_IO_MIN_DISTANCE)] } {
-	lappend arg_list -min_distance $::env(FP_IO_MIN_DISTANCE)
+if { [info exists ::env(IO_PIN_MIN_DISTANCE)] } {
+    lappend arg_list -min_distance $::env(IO_PIN_MIN_DISTANCE)
 }
 
-if { $::env(FP_PPL_MODE) == "annealing" } {
-	lappend arg_list -annealing
+if { $::env(IO_PIN_PLACEMENT_MODE) == "annealing" } {
+    lappend arg_list -annealing
 }
 
 set HMETAL $::env(FP_IO_HLAYER)
 set VMETAL $::env(FP_IO_VLAYER)
 
 log_cmd place_pins {*}$arg_list \
-	-random_seed 42 \
-	-hor_layers $HMETAL \
-	-ver_layers $VMETAL
+    -random_seed 42 \
+    -hor_layers $HMETAL \
+    -ver_layers $VMETAL
 
 write_views
 

librelane/scripts/openroad/pdn.tcl

@@ -21,7 +21,7 @@ source $::env(SCRIPTS_DIR)/openroad/common/set_power_nets.tcl
 read_pdn_cfg
 
 set arg_list [list]
-if { $::env(FP_PDN_SKIPTRIM) } {
+if { $::env(PDN_SKIPTRIM) } {
     lappend arg_list -skip_trim
 }
 # run PDNGEN

librelane/scripts/openroad/sta/check_macro_instances.tcl

@@ -30,10 +30,10 @@ foreach {instance_name macro_name} $::env(_check_macro_instances) {
     set instances [get_cells -hierarchical $instance_name]
     set instance_count [llength $instances]
     if { $instance_count < 1 } {
-        puts "\[ERROR\] No macro instance $instance_name found."
+        puts stderr "\[ERROR\] No macro instance $instance_name found."
         incr error_count
     } elseif { $instance_count > 1 } {
-        puts "\[ERROR\] Macro instance name $instance_name matches multiple cells."
+        puts stderr "\[ERROR\] Macro instance name $instance_name matches multiple cells."
         incr error_count
     } else {
         # The next line doesn't actually matter because this is Tcl but I'd feel
@@ -42,7 +42,7 @@ foreach {instance_name macro_name} $::env(_check_macro_instances) {
 
         set master_name [get_property $instance ref_name]
         if { $master_name != $macro_name } {
-            puts "\[ERROR\] Instance $instance_name is configured as an instance of macro $macro_name, but is an instance of $master_name."
+            puts stderr "\[ERROR\] Instance $instance_name is configured as an instance of macro $macro_name, but is an instance of $master_name."
             incr error_count
         }
     }

librelane/scripts/openroad/sta/corner.tcl

@@ -54,7 +54,7 @@ puts "\n========================================================================
 puts "report_checks -path_delay min (Hold)"
 puts "============================================================================"
 puts "======================= [$corner name] Corner ===================================\n"
-report_checks -sort_by_slack -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner [$corner name]
+report_checks -sort_by_slack -path_delay min -fields {slew cap input net fanout} -format full_clock_expanded -group_path_count 1000 -corner [$corner name]
 puts ""
 puts "%OL_END_REPORT"
 
@@ -64,7 +64,7 @@ puts "\n========================================================================
 puts "report_checks -path_delay max (Setup)"
 puts "============================================================================"
 puts "======================= [$corner name] Corner ===================================\n"
-report_checks -sort_by_slack -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 1000 -corner [$corner name]
+report_checks -sort_by_slack -path_delay max -fields {slew cap input net fanout} -format full_clock_expanded -group_path_count 1000 -corner [$corner name]
 puts ""
 puts "%OL_END_REPORT"
 
@@ -74,7 +74,7 @@ puts "\n========================================================================
 puts "report_checks -unconstrained"
 puts "==========================================================================="
 puts "======================= [$corner name] Corner ===================================\n"
-report_checks -unconstrained -fields {slew cap input nets fanout} -format full_clock_expanded -corner [$corner name]
+report_checks -unconstrained -fields {slew cap input net fanout} -format full_clock_expanded -corner [$corner name]
 puts ""
 
 
@@ -82,7 +82,7 @@ puts "\n========================================================================
 puts "report_checks --slack_max -0.01"
 puts "============================================================================"
 puts "======================= [$corner name] Corner ===================================\n"
-report_checks -slack_max -0.01 -fields {slew cap input nets fanout} -format full_clock_expanded -corner [$corner name]
+report_checks -slack_max -0.01 -fields {slew cap input net fanout} -format full_clock_expanded -corner [$corner name]
 puts ""
 
 puts "\n==========================================================================="
@@ -260,7 +260,7 @@ if { [info exists ::env(STA_MAX_VIOLATOR_COUNT)] } {
     set max_violator_count $::env(STA_MAX_VIOLATOR_COUNT)
 }
 
-set hold_violating_paths [find_timing_paths -unique_paths_to_endpoint -path_delay min -sort_by_slack -group_count $max_violator_count -slack_max 0]
+set hold_violating_paths [find_timing_paths -unique_paths_to_endpoint -path_delay min -sort_by_slack -group_path_count $max_violator_count -slack_max 0]
 foreach path $hold_violating_paths {
     set start_pin [get_property $path startpoint]
     set end_pin [get_property $path endpoint]
@@ -279,7 +279,7 @@ foreach path $hold_violating_paths {
 }
 
 set worst_r2r_hold_slack 1e30
-set hold_paths [find_timing_paths -unique_paths_to_endpoint -path_delay min -sort_by_slack -group_count $max_violator_count -slack_max $worst_r2r_hold_slack]
+set hold_paths [find_timing_paths -unique_paths_to_endpoint -path_delay min -sort_by_slack -group_path_count $max_violator_count -slack_max $worst_r2r_hold_slack]
 foreach path $hold_paths {
     set start_pin [get_property $path startpoint]
     set end_pin [get_property $path endpoint]
@@ -295,7 +295,7 @@ foreach path $hold_paths {
     }
 }
 
-set setup_violating_paths [find_timing_paths -unique_paths_to_endpoint -path_delay max -sort_by_slack -group_count $max_violator_count -slack_max 0]
+set setup_violating_paths [find_timing_paths -unique_paths_to_endpoint -path_delay max -sort_by_slack -group_path_count $max_violator_count -slack_max 0]
 foreach path $setup_violating_paths {
     set start_pin [get_property $path startpoint]
     set end_pin [get_property $path endpoint]
@@ -314,7 +314,7 @@ foreach path $setup_violating_paths {
 }
 
 set worst_r2r_setup_slack 1e30
-set setup_paths [find_timing_paths -unique_paths_to_endpoint -path_delay max -sort_by_slack -group_count $max_violator_count -slack_max $worst_r2r_setup_slack]
+set setup_paths [find_timing_paths -unique_paths_to_endpoint -path_delay max -sort_by_slack -group_path_count $max_violator_count -slack_max $worst_r2r_setup_slack]
 foreach path $setup_paths {
     set start_pin [get_property $path startpoint]
     set end_pin [get_property $path endpoint]

librelane/scripts/pyosys/json_header.py

@@ -62,8 +62,7 @@ def json_header(
         synth_parameters=config["SYNTH_PARAMETERS"] or [],
         includes=includes,
         defines=defines,
-        use_synlig=config["USE_SYNLIG"],
-        synlig_defer=config["SYNLIG_DEFER"],
+        use_slang=config["USE_SLANG"],
     )
     d.run_pass(
         "hierarchy",

librelane/scripts/pyosys/synthesize.py

@@ -262,8 +262,7 @@ def synthesize(
             synth_parameters=[],
             includes=includes,
             defines=defines,
-            use_synlig=False,
-            synlig_defer=False,
+            use_slang=False,
         )
     elif verilog_files := config.get("VERILOG_FILES"):
         d.read_verilog_files(
@@ -272,8 +271,7 @@ def synthesize(
             synth_parameters=config["SYNTH_PARAMETERS"] or [],
             includes=includes,
             defines=defines,
-            use_synlig=config["USE_SYNLIG"],
-            synlig_defer=config["SYNLIG_DEFER"],
+            use_slang=config["USE_SLANG"],
         )
     elif vhdl_files := config.get("VHDL_FILES"):
         d.run_pass("plugin", "-i", "ghdl")
@@ -300,6 +298,8 @@ def synthesize(
         )
     except Exception:
         pass
+    if config["SYNTH_NORMALIZE_SINGLE_BIT_VECTORS"]:
+        d.run_pass("attrmap", "-remove", "single_bit_vector")
     d.run_pass("select", "-clear")
 
     lib_arguments = []