librelane 2.4.0.dev9__py3-none-any.whl → 3.0.0.dev23__py3-none-any.whl

librelane/scripts/openroad/common/set_rc.tcl

@@ -14,62 +14,181 @@
 
 # Resistance/Capacitance Overrides
 # Via resistance
-puts "\[INFO\] Setting RC values…"
-if { [info exist ::env(VIAS_RC)] } {
-    set vias_rc [split $::env(VIAS_RC) ","]
-    foreach via_rc $vias_rc {
-        set layer_name [lindex $via_rc 0]
-        set resistance [lindex $via_rc 1]
-        set_layer_rc -via $layer_name -resistance $resistance
+
+proc log_cmd_rc {cmd args} {
+    if { $::env(SET_RC_VERBOSE) } {
+        log_cmd $cmd {*}$args
+    } else {
+        $cmd {*}$args
     }
 }
 
-# Metal resistance and capacitence
-if { [info exist ::env(LAYERS_RC)] } {
-    set layers_rc [split $::env(LAYERS_RC) ","]
-    foreach layer_rc $layers_rc {
-        set layer_name [lindex $layer_rc 0]
-        set capacitance [lindex $layer_rc 1]
-        set resistance [lindex $layer_rc 2]
-        set_layer_rc -layer $layer_name -capacitance $capacitance -resistance $resistance
+proc set_layers_custom_rc {args} {
+    # Returns: All corners for which RC values were found
+    set i "0"
+    set tc_key "_LAYER_RC_$i"
+    set custom_corner_rc [list]
+    while { [info exists ::env($tc_key)] } {
+        # [$corner] + [layer] + [str(round(res, 8))] + [str(round(cap, 8))]
+        set corner_name [lindex $::env($tc_key) 0]
+        set layer_name [lindex $::env($tc_key) 1]
+        set res_value [lindex $::env($tc_key) 2]
+        set cap_value [lindex $::env($tc_key) 3]
+        log_cmd_rc set_layer_rc \
+            -layer $layer_name\
+            -capacitance $cap_value\
+            -corner $corner_name\
+            -resistance $res_value
+        incr i
+        set tc_key "_LAYER_RC_$i"
+        set corner [sta::find_corner $corner_name]
+        if { [lsearch $custom_corner_rc $corner] == -1 } {
+            lappend custom_corner_rc $corner
+        }
     }
+    return $custom_corner_rc
 }
 
-set layer_names [list]
-set layers [$::tech getLayers]
-set adding 0
-foreach layer $layers {
-    if { [$layer getRoutingLevel] >= 1 } {
-        set name [$layer getName]
-        if {"$::env(RT_MIN_LAYER)" == "$name"} {
-            set adding 1
+proc set_via_custom_r {args} {
+    set i "0"
+    set tc_key "_VIA_R_$i"
+    set custom_corner_r [list]
+    while { [info exists ::env($tc_key)] } {
+        set corner_name [lindex $::env($tc_key) 0]
+        set via_name [lindex $::env($tc_key) 1]
+        set res_value [lindex $::env($tc_key) 2]
+        log_cmd_rc set_layer_rc \
+            -via $via_name\
+            -resistance $res_value\
+            -corner $corner_name
+        incr i
+        set tc_key "_VIA_R_$i"
+        set corner [sta::find_corner $corner_name]
+        if { [lsearch $custom_corner_r $corner] == -1 } {
+            lappend custom_corner_r $corner
         }
-        if { $adding } {
-            lappend layer_names $name
+    }
+    return $custom_corner_r
+}
+
+proc set_layers_default_rc {corners} {
+    foreach layer [get_layers -type ROUTING] {
+        set layer_name [$layer getName]
+        lassign [rsz::dblayer_wire_rc $layer] layer_wire_res_ohm_m layer_wire_cap_farad_m
+        set layer_wire_res_per_unit_distance [expr $layer_wire_res_ohm_m * [sta::unit_scale distance] / [sta::unit_scale resistance]]
+        set layer_wire_cap_per_unit_distance [expr $layer_wire_cap_farad_m * [sta::unit_scale distance] / [sta::unit_scale capacitance]]
+        foreach corner "$corners" {
+            log_cmd_rc set_layer_rc \
+                -layer $layer_name\
+                -corner $corner\
+                -resistance $layer_wire_res_per_unit_distance\
+                -capacitance $layer_wire_cap_per_unit_distance
+        }
+    }
+}
+
+proc set_vias_default_r {corners} {
+    foreach layer [get_layers -types "CUT"] {
+        set layer_name [$layer getName]
+        set res [expr [$layer getResistance] / [sta::unit_scale resistance]]
+        foreach corner $corners {
+            log_cmd_rc set_layer_rc \
+                -corner $corner\
+                -resistance $res\
+                -via $layer_name
         }
+    }
+}
+
+proc set_wire_rc_wrapper {args} {
+    sta::parse_key_args "set_wire_rc_wrapper" args \
+        keys {}\
+        flags {-use_corners}
+
+    # We only want the layers that will actually be used for set_wire_rc's estimations.
+    set layer_names [get_layers -constrained -type ROUTING -map getName]
+    set signal_wire_rc_layers $layer_names
+    set clock_wire_rc_layers $layer_names
+    if { [info exist ::env(SIGNAL_WIRE_RC_LAYERS)] } {
+        set signal_wire_rc_layers $::env(SIGNAL_WIRE_RC_LAYERS)
+    }
+    if { [info exist ::env(CLOCK_WIRE_RC_LAYERS)] } {
+        set clock_wire_rc_layers $::env(CLOCK_WIRE_RC_LAYERS)
+    }
+    set signal_args [list]
+    lappend signal_args -signal
+    if { [llength $signal_wire_rc_layers] > 1 } {
+        lappend signal_args -layers "$signal_wire_rc_layers"
+    } else {
+        lappend signal_args -layer "$signal_wire_rc_layers"
+    }
+
+    set clock_args [list]
+    lappend clock_args -clock
+    if { [llength $clock_wire_rc_layers] > 1 } {
+        lappend clock_args -layers "$clock_wire_rc_layers"
+    } else {
+        lappend clock_args -layer "$clock_wire_rc_layers"
+    }
 
-        if {"$::env(RT_MAX_LAYER)" == "$name"} {
-            set adding 0
+    if { [info exists flags(-use_corners)] } {
+        foreach corner [sta::corners] {
+            log_cmd_rc set_wire_rc {*}$clock_args -corner [$corner name]
+            log_cmd_rc set_wire_rc {*}$signal_args -corner [$corner name]
         }
+    } else {
+        log_cmd_rc set_wire_rc {*}$clock_args
+        log_cmd_rc set_wire_rc {*}$signal_args
     }
 }
 
-set signal_wire_rc_layers $layer_names
-set clock_wire_rc_layers $layer_names
-if { [info exist ::env(SIGNAL_WIRE_RC_LAYERS)] } {
-    set signal_wire_rc_layers $::env(SIGNAL_WIRE_RC_LAYERS)
+# TODO: Replace with actual Tcl sets once we have access to the standard library
+proc set_diff {setA setB} {
+    set setC [list]
+    foreach element $setA {
+        if {[lsearch $setB $element] == -1} {
+            lappend setC $element
+        }
+    }
+    return $setC
 }
-if { [info exist ::env(CLOCK_WIRE_RC_LAYERS)] } {
-    set clock_wire_rc_layers $::env(CLOCK_WIRE_RC_LAYERS)
+
+# Flow as follows
+# 1. Set layers custom rc - if defined
+# 2. Set vias custom r - if defined
+# 3. If (1) doesn't override all the corners, set the default techlef value for the remaining corners for layers
+# 3.a If (2) doesn't override all the corners, set the default techlef value for the remaining corners for vias
+# 4. If (1) doesn't override the corners at all, call set_wire_rc without -corner, to ensure the default behavior
+# 5. If (1) does override (some) corners, we must use set_wire_rc with -corner, becuase otherwise set_wire_rc will set the default techlef value for all existing corners
+
+set corners_with_custom_layer_rc [set_layers_custom_rc]
+set corners_with_custom_via_r [set_via_custom_r]
+set corners_without_custom_layer_rc [set_diff [sta::corners] $corners_with_custom_layer_rc]
+set corners_without_custom_via_r [set_diff [sta::corners] $corners_with_custom_via_r]
+
+# If ANY CORNERS have custom RC values set, set the tech LEF values for the
+# remaining corners.
+#
+# If NO CORNERS have custom RC values set, do nothing. The set_wire_rc LATER
+# will automatically average the Tech LEF values.
+#
+# This is because, technically, while both behaviors SHOULD be identical, they
+# aren't because of roundoff errors emblematic of IEEE 754.
+if { [llength $corners_with_custom_layer_rc] } {
+    log_cmd_rc set_layers_default_rc [lmap corner $corners_without_custom_layer_rc "\$corner name"]
 }
-if { [llength $signal_wire_rc_layers] > 1 } {
-    set_wire_rc -signal -layers "$signal_wire_rc_layers"
-} else {
-    set_wire_rc -signal -layer "$signal_wire_rc_layers"
+if { [llength $corners_with_custom_via_r] } {
+    log_cmd_rc set_vias_default_r $corners_without_custom_via_r
 }
 
-if { [llength $clock_wire_rc_layers] > 1 } {
-    set_wire_rc -clock -layers "$clock_wire_rc_layers"
+
+# If ANY corners are set, supply -corner with the set_wire_rc command.
+#
+# If NONE are set, just use set_wire_rc and let it handle all corners.
+# For some godforsaken reason, set_wire_rc actually alters its own calculations
+# slightly depending on if -corner is passed or not.
+if { [llength $corners_with_custom_layer_rc] } {
+    log_cmd_rc set_wire_rc_wrapper -use_corners
 } else {
-    set_wire_rc -clock -layer "$clock_wire_rc_layers"
+    log_cmd_rc set_wire_rc_wrapper
 }

librelane/scripts/openroad/cts.tcl

@@ -14,7 +14,6 @@
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 source $::env(SCRIPTS_DIR)/openroad/common/resizer.tcl
 
-load_rsz_corners
 read_current_odb
 
 # set rc values
@@ -33,15 +32,36 @@ if { [info exists ::env(CTS_MAX_CAP)] } {
 if { [info exists ::env(CTS_MAX_SLEW)] } {
     lappend cts_characterization_args -max_slew [expr {$::env(CTS_MAX_SLEW) * 1e-9}]; # ns -> S
 }
-configure_cts_characterization {*}$cts_characterization_args
+log_cmd configure_cts_characterization {*}$cts_characterization_args
 
 puts "\[INFO\] Performing clock tree synthesis…"
 puts "\[INFO\] Looking for the following net(s): $::env(CLOCK_NET)"
 puts "\[INFO\] Running Clock Tree Synthesis…"
 
-set arg_list [list]
+proc get_buflist {} {
+    set result [list]
+    foreach selector $::env(CTS_CLK_BUFFERS) {
+        # if we can find an exact match, avoid expensive search operation
+        set exact_match [$::db findMaster $selector]
+        if { "$exact_match" == "NULL" } {
+            # time to dig for matches…
+            foreach lib $::libs {
+                foreach master [$lib getMasters] {
+                    set name [$master getName]
+                    if { [string match $selector $name] } {
+                        lappend result $name
+                    }
+                }
+            }
+        } else {
+            lappend result [$exact_match getName]
+        }
+    }
+    return $result
+}
 
-lappend arg_list -buf_list $::env(CTS_CLK_BUFFERS)
+set arg_list [list]
+lappend arg_list -buf_list [get_buflist]
 lappend arg_list -root_buf $::env(CTS_ROOT_BUFFER)
 lappend arg_list -sink_clustering_size $::env(CTS_SINK_CLUSTERING_SIZE)
 lappend arg_list -sink_clustering_max_diameter $::env(CTS_SINK_CLUSTERING_MAX_DIAMETER)
@@ -50,12 +70,23 @@ lappend arg_list -sink_clustering_enable
 if { $::env(CTS_DISTANCE_BETWEEN_BUFFERS) != 0 } {
     lappend arg_list -distance_between_buffers $::env(CTS_DISTANCE_BETWEEN_BUFFERS)
 }
-
 if { $::env(CTS_DISABLE_POST_PROCESSING) } {
     lappend arg_list -post_cts_disable
 }
+if { [info exists ::env(CTS_OBSTRUCTION_AWARE)] && $::env(CTS_OBSTRUCTION_AWARE) } {
+    lappend arg_list -obstruction_aware
+}
+if { [info exists ::env(CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT)] } {
+    lappend arg_list -sink_buffer_max_cap_derate [expr $::env(CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT) / 100.0]
+}
+if { [info exists ::env(CTS_DELAY_BUFFER_DERATE_PCT)] } {
+    lappend arg_list -delay_buffer_derate [expr $::env(CTS_DELAY_BUFFER_DERATE_PCT) / 100]
+}
+if { [info exists ::env(CTS_BALANCE_LEVELS)] && $::env(CTS_BALANCE_LEVELS) } {
+    lappend arg_list -balance_levels
+}
 
-clock_tree_synthesis {*}$arg_list
+log_cmd clock_tree_synthesis {*}$arg_list
 
 set_propagated_clock [all_clocks]
 

librelane/scripts/openroad/cut_rows.tcl

@@ -14,10 +14,25 @@
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 read_current_odb
 
-cut_rows\
-    -endcap_master $::env(ENDCAP_CELL)\
-    -halo_width_x $::env(FP_MACRO_HORIZONTAL_HALO)\
-    -halo_width_y $::env(FP_MACRO_VERTICAL_HALO)
+set arg_list [list]
+lappend arg_list -halo_width_x $::env(FP_MACRO_HORIZONTAL_HALO)
+lappend arg_list -halo_width_y $::env(FP_MACRO_VERTICAL_HALO)
+append_if_exists_argument arg_list FP_PRUNE_THRESHOLD -row_min_width
+append_if_exists_argument arg_list ENDCAP_CELL -endcap_master
+log_cmd cut_rows {*}$arg_list
+
+# # verify -row_min_width worked
+# if { [info exists ::env(FP_PRUNE_THRESHOLD)] } {
+#     foreach row [$::block getRows] {
+#         set bbox [$row getBBox]
+#         set width [expr ([$bbox xMax] - [$bbox xMin])]
+#         set width_um [expr $width / $::dbu]
+#         if { $width < $::env(FP_PRUNE_THRESHOLD) } {
+#             exit -1
+#             # odb::dbRow_destroy $row
+#         }
+#     }
+# }
 
 write_views
 

librelane/scripts/openroad/drt.tcl

@@ -11,6 +11,22 @@
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 # See the License for the specific language governing permissions and
 # limitations under the License.
+proc drt_run {i args} {
+    set directory "drt-run-${i}"
+    file mkdir "$::env(STEP_DIR)/$directory"
+    set output_drc "-output_drc $::env(STEP_DIR)/$directory/$::env(DESIGN_NAME).drc"
+    log_cmd detailed_route {*}$args {*}$output_drc
+    if { $::env(DRT_SAVE_SNAPSHOTS) } {
+        foreach snapshot [glob -nocomplain drt_iter*.odb] {
+            file rename -force $snapshot $directory/[file tail $snapshot]
+        }
+    }
+    foreach drc_file [glob -nocomplain $::env(STEP_DIR)/$directory/*.drc] {
+        file copy -force $drc_file $::env(STEP_DIR)/[file tail $drc_file]
+    }
+    write_db $::env(STEP_DIR)/$directory/$::env(DESIGN_NAME).odb
+}
+
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 read_current_odb
 
@@ -25,13 +41,48 @@ set max_layer $::env(RT_MAX_LAYER)
 if { [info exists ::env(DRT_MAX_LAYER)] } {
     set max_layer $::env(DRT_MAX_LAYER)
 }
+if { $::env(DRT_SAVE_SNAPSHOTS) } {
+    set_debug_level DRT snapshot 1
+}
+set drc_report_iter_step_arg ""
+if { $::env(DRT_SAVE_SNAPSHOTS) } {
+    set_debug_level DRT snapshot 1
+    set drc_report_iter_step_arg "-drc_report_iter_step 1"
+}
+if { [info exists ::env(DRT_SAVE_DRC_REPORT_ITERS)] } {
+    set drc_report_iter_step_arg "-drc_report_iter_step $::env(DRT_SAVE_DRC_REPORT_ITERS)"
+}
 
-detailed_route\
-    -bottom_routing_layer $min_layer\
-    -top_routing_layer $max_layer\
-    -output_drc $::env(STEP_DIR)/$::env(DESIGN_NAME).drc\
-    -droute_end_iter $::env(DRT_OPT_ITERS)\
-    -or_seed 42\
-    -verbose 1
+set i 0
 
-write_views
+set drt_args [list]
+lappend drt_args -bottom_routing_layer $min_layer
+lappend drt_args -top_routing_layer $max_layer
+lappend drt_args -droute_end_iter $::env(DRT_OPT_ITERS)
+lappend drt_args -or_seed 42
+lappend drt_args -verbose 1
+lappend drt_args {*}$drc_report_iter_step_arg
+drt_run $i {*}$drt_args
+
+incr i
+
+if { ![info exists ::env(DIODE_CELL)] } {
+    puts "\[INFO\] Skipping post-DRT antenna repair: 'DIODE_CELL' not set."
+} elseif { $::env(DRT_ANTENNA_REPAIR_ITERS) == 0 } {
+    puts "\[INFO\] Skipping post-DRT antenna repair: DRT_ANTENNA_REPAIR_ITERS set to 0."
+} else {
+    set diode_cell [lindex [split $::env(DIODE_CELL) "/"] 0]
+
+    while {$i <= $::env(DRT_ANTENNA_REPAIR_ITERS) && [log_cmd check_antennas]} {
+        puts "\[INFO\] Running antenna repair iteration $i…"
+        set diodes_inserted [log_cmd repair_antennas $diode_cell -ratio_margin $::env(DRT_ANTENNA_MARGIN)]
+        if {$diodes_inserted} {
+            drt_run $i {*}$drt_args
+        } else {
+            puts "\[INFO\] No diodes inserted. Ending antenna repair iterations."
+            break
+        }
+        incr i
+    }
+}
+write_views

librelane/scripts/openroad/dump_rc.tcl

@@ -0,0 +1,105 @@
+# Copyright 2020-2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
+read_pnr_libs
+read_lefs
+read_def $::env(CURRENT_DEF)
+set_global_vars
+
+set rc_header {%-20s%-20s%-20s%-20s}
+set rc_entry {%-20s%-20s%-20e%-20e}
+set r_header {%-20s%-20s}
+set r_entry {%-20s%-20e}
+
+proc scale_ohm_per_meter {value} {
+    set ohm_per_unit_distance [expr "$value * [sta::unit_scale distance]"]
+    set unit_res_per_unit_distance [expr "$ohm_per_unit_distance / [sta::unit_scale resistance]"]
+    return $unit_res_per_unit_distance
+}
+
+proc scale_f_per_meter {value} {
+    set f_per_unit_distance [expr "$value * [sta::unit_scale distance]"]
+    set unit_cap_per_unit_distance [expr "$f_per_unit_distance / [sta::unit_scale capacitance]"]
+    return $unit_cap_per_unit_distance
+}
+
+proc dblayer_rc_values {header} {
+    upvar 1 rc_header rc_header
+    upvar 1 rc_entry rc_entry
+    upvar 1 r_header r_header
+    upvar 1 r_entry r_entry
+
+    puts $header
+    puts "=== Routing Layers ==="
+    puts [format $rc_header "Name" "Direction" "Res/Unit Distance" "Cap/Unit Distance"]
+    foreach layer [get_layers -types "ROUTING"] {
+        lassign [rsz::dblayer_wire_rc $layer] layer_wire_res_ohm_m layer_wire_cap_farad_m
+        puts [format $rc_entry [$layer getName] [$layer getDirection] [scale_ohm_per_meter $layer_wire_res_ohm_m] [scale_f_per_meter $layer_wire_cap_farad_m]]
+    }
+
+    puts "=== Vias ==="
+    puts [format $r_header "Name" "Cut Resistance"]
+    foreach layer [get_layers -types "CUT"] {
+        set ohms_per_cut [$layer getResistance]
+        puts [format $r_entry [$layer getName] [expr "$ohms_per_cut / [sta::unit_scale resistance]"]]
+    }
+}
+
+proc resizer_rc_values {header} {
+    upvar 1 rc_header rc_header
+    upvar 1 rc_entry rc_entry
+    upvar 1 r_header r_header
+    upvar 1 r_entry r_entry
+
+    puts $header
+    foreach corner [sta::corners] {
+        puts "=== Corner [$corner name] ==="
+        puts "==== Estimation RC Values ===="
+        puts [format $rc_header "Name" "Direction" "Res/Unit Distance" "Cap/Unit Distance"]
+        puts [format $rc_entry "Signal" "Avg" [scale_ohm_per_meter [rsz::wire_signal_resistance $corner]] [scale_f_per_meter [rsz::wire_signal_capacitance $corner]]]
+        puts [format $rc_entry "Clock" "Avg" [scale_ohm_per_meter [rsz::wire_clk_resistance $corner]] [scale_f_per_meter [rsz::wire_clk_capacitance $corner]]]
+        puts "==== Rt. Layer RC Values ===="
+        puts [format $rc_header "Name" "Direction" "Res/Unit Distance" "Cap/Unit Distance"]
+        foreach layer [get_layers -types "ROUTING"] {
+            set resistance [expr [rsz::layer_resistance $layer $corner] / [sta::unit_scale resistance] * [sta::unit_scale distance]]
+            set capacitance [expr [rsz::layer_capacitance $layer $corner] / [sta::unit_scale capacitance] * [sta::unit_scale distance]]
+            puts [format $rc_entry [$layer getName] [$layer getDirection] $resistance $capacitance]
+        }
+        puts "==== Via R Values ===="
+        puts [format $r_header "Name" "Res/Unit Distance"]
+        foreach layer [get_layers -types "CUT"] {
+            set ohms_per_cut [rsz::layer_resistance $layer $corner]
+            set units_resistance_per_cut [expr $ohms_per_cut / [sta::unit_scale resistance]]
+            puts [format $r_entry [$layer getName] $units_resistance_per_cut]
+        }
+    }
+}
+
+
+puts "%OL_CREATE_REPORT tlef_values.rpt"
+report_units
+dblayer_rc_values "== Technology LEF Values =="
+puts "%OL_END_REPORT"
+
+source $::env(SCRIPTS_DIR)/openroad/common/set_rc.tcl
+
+puts "%OL_CREATE_REPORT layer_values_after.rpt"
+report_units
+dblayer_rc_values "== Layer Values (After Set RC) =="
+puts "%OL_END_REPORT"
+
+puts "%OL_CREATE_REPORT resizer_values_after.rpt"
+report_units
+resizer_rc_values "== Resizer RC Values (After Set RC) =="
+puts "%OL_END_REPORT"

librelane/scripts/openroad/fill.tcl

@@ -15,11 +15,11 @@ source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 read_current_odb
 
 set fill_list [list]
-foreach {pattern} $::env(DECAP_CELL) {
+foreach {pattern} $::env(DECAP_CELLS) {
     set stripped [string map {' {}} $pattern]
     lappend fill_list $stripped
 }
-foreach {pattern} $::env(FILL_CELL) {
+foreach {pattern} $::env(FILL_CELLS) {
     set stripped [string map {' {}} $pattern]
     lappend fill_list $stripped
 }

librelane/scripts/openroad/floorplan.tcl

@@ -53,7 +53,7 @@ puts "\[INFO\] Using $::env(FP_SIZING) sizing for the floorplan."
 if {$::env(FP_SIZING) == "absolute"} {
     if { [llength $::env(DIE_AREA)] != 4 } {
         puts stderr "Invalid die area string '$::env(DIE_AREA)'."
-        exit -1
+        exit_unless_gui 1
     }
     if { ! [info exists ::env(CORE_AREA)] } {
         set die_x0 [lindex $::env(DIE_AREA) 0]
@@ -73,7 +73,7 @@ if {$::env(FP_SIZING) == "absolute"} {
     } else {
         if { [llength $::env(CORE_AREA)] != 4 } {
             puts stderr "Invalid core area string '$::env(CORE_AREA)'."
-            exit -1
+            exit_unless_gui 1
         }
         puts "\[INFO\] Using the set CORE_AREA; ignoring core margin parameters"
     }
@@ -97,7 +97,9 @@ if { [info exists ::env(FP_OBSTRUCTIONS)] } {
     }
 }
 
-initialize_floorplan {*}$arg_list
+append_if_exists_argument arg_list FP_FLIP_SITES -flip_sites
+
+log_cmd initialize_floorplan {*}$arg_list
 
 insert_tiecells $::env(SYNTH_TIELO_CELL) -prefix "TIE_ZERO_"
 insert_tiecells $::env(SYNTH_TIEHI_CELL) -prefix "TIE_ONE_"

librelane/scripts/openroad/gpl.tcl

@@ -26,11 +26,11 @@ foreach inst $::insts {
 }
 
 if { !$placement_needed } {
-	puts stderr "\[WARNING\] All instances are FIXED/FIRM."
-	puts stderr "\[WARNING\] No need to perform global placement."
-	puts stderr "\[WARNING\] Skipping…"
+	puts "\[INFO\] All instances are FIXED/FIRM."
+	puts "\[INFO\] No need to perform global placement."
+	puts "\[INFO\] Skipping…"
 	write_views
-	exit 0
+	exit_unless_gui
 }
 
 set arg_list [list]
@@ -56,8 +56,7 @@ if { $::env(PL_SKIP_INITIAL_PLACEMENT) } {
 	lappend arg_list -skip_initial_place
 }
 
-
-if { [info exists ::env(__PL_SKIP_IO)] } {
+if { [info exists ::env(__PL_SKIP_IO)] && $::env(__PL_SKIP_IO) == "1" } {
 	lappend arg_list -skip_io
 }
 
@@ -74,9 +73,9 @@ set cell_pad_side [expr $::env(GPL_CELL_PADDING) / 2]
 lappend arg_list -pad_right $cell_pad_side
 lappend arg_list -pad_left $cell_pad_side
 lappend arg_list -init_wirelength_coef $::env(PL_WIRE_LENGTH_COEF)
+append_if_exists_argument arg_list PL_KEEP_RESIZE_BELOW_OVERFLOW -keep_resize_below_overflow
 
-puts "+ global_placement $arg_list"
-global_placement {*}$arg_list
+log_cmd global_placement {*}$arg_list
 
 
 source $::env(SCRIPTS_DIR)/openroad/common/set_rc.tcl

librelane/scripts/openroad/insert_buffer.tcl

@@ -121,7 +121,7 @@ if { [info exists ::env(INSERT_BUFFER_COMMAND) ]} {
     read_current_odb
 
     set arg_list [split $::env(INSERT_BUFFER_COMMAND) " "]
-    insert_buffer {*}$arg_list
+    log_cmd insert_buffer {*}$arg_list
 
     write_views
-}
+}

librelane/scripts/openroad/ioplacer.tcl

@@ -55,8 +55,7 @@ if { $::env(FP_PPL_MODE) == "annealing" } {
 set HMETAL $::env(FP_IO_HLAYER)
 set VMETAL $::env(FP_IO_VLAYER)
 
-puts "\[INFO\] place_pins args: $arg_list"
-place_pins {*}$arg_list \
+log_cmd place_pins {*}$arg_list \
 	-random_seed 42 \
 	-hor_layers $HMETAL \
 	-ver_layers $VMETAL

librelane/scripts/openroad/irdrop.tcl

@@ -27,7 +27,7 @@ if { [info exists ::env(VSRC_LOC_FILES)] } {
         lappend arg_list -net $net
         lappend arg_list -voltage_file $::env(STEP_DIR)/net-$net.csv
         lappend arg_list -vsrc $vsrc_file
-        analyze_power_grid {*}$arg_list
+        log_cmd analyze_power_grid {*}$arg_list
     }
     puts "%OL_END_REPORT"
 } else {
@@ -38,14 +38,14 @@ if { [info exists ::env(VSRC_LOC_FILES)] } {
         lappend arg_list -net $net
         lappend arg_list -voltage_file $::env(STEP_DIR)/net-$net.csv
         set_pdnsim_net_voltage -net $net -voltage $::env(LIB_VOLTAGE)
-        analyze_power_grid {*}$arg_list
+        log_cmd analyze_power_grid {*}$arg_list
     }
     foreach net "$::env(GND_NETS)" {
         set arg_list [list]
         lappend arg_list -net $net
         lappend arg_list -voltage_file $::env(STEP_DIR)/net-$net.csv
         set_pdnsim_net_voltage -net $net -voltage 0
-        analyze_power_grid {*}$arg_list
+        log_cmd analyze_power_grid {*}$arg_list
     }
     puts "%OL_END_REPORT"
 }