librelane 2.4.0.dev7__py3-none-any.whl → 3.0.0.dev22__py3-none-any.whl

librelane/scripts/openroad/pdn.tcl

@@ -23,30 +23,29 @@ read_pdn_cfg
 set arg_list [list]
 if { $::env(FP_PDN_SKIPTRIM) } {
     lappend arg_list -skip_trim
-    puts "adding -skip_trim to pdngen"
 }
 # run PDNGEN
-if {[catch {pdngen {*}$arg_list} errmsg]} {
+if {[catch {log_cmd pdngen {*}$arg_list} errmsg]} {
     puts stderr $errmsg
-    exit 1
-}
+    exit_unless_gui 1
+} else {
+    write_views
+    report_design_area_metrics
 
-write_views
-report_design_area_metrics
+    foreach {net} "$::env(VDD_NETS) $::env(GND_NETS)" {
+        set report_file $::env(STEP_DIR)/$net-grid-errors.rpt
 
-foreach {net} "$::env(VDD_NETS) $::env(GND_NETS)" {
-    set report_file $::env(STEP_DIR)/$net-grid-errors.rpt
+        # For some reason, check_power_grid is… totally okay if no nodes are found
+        # at all. i.e. PDN generation has completely failed.
+        # This is a fallback file.
+        set f [open $report_file "w"]
+        puts $f ""
+        close $f
 
-    # For some reason, check_power_grid is… totally okay if no nodes are found
-    # at all. i.e. PDN generation has completely failed.
-    # This is a fallback file.
-    set f [open $report_file "w"]
-    puts $f "violation type: no nodes"
-    puts $f "  srcs: "
-    puts $f "  - N/A"
-    close $f
+        if { [catch {check_power_grid -net $net -error_file $report_file} err] } {
+            puts stderr "\[WARNING\] Grid check for $net failed: $err"
+        }
 
-    if { [catch {check_power_grid -net $net -error_file $report_file} err] } {
-        puts stderr "\[WARNING\] Grid check for $net failed: $err"
     }
+
 }

librelane/scripts/openroad/rcx.tcl

@@ -26,7 +26,7 @@ if { !$::env(RCX_MERGE_VIA_WIRE_RES) } {
 # RCX
 puts "Using RCX ruleset '$::env(RCX_RULESET)'…"
 define_process_corner -ext_model_index 0 CURRENT_CORNER
-extract_parasitics $rcx_flags\
+log_cmd extract_parasitics $rcx_flags\
     -ext_model_file $::env(RCX_RULESET)\
     -lef_res
 write_views

librelane/scripts/openroad/repair_design.tcl

@@ -14,7 +14,6 @@
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 source $::env(SCRIPTS_DIR)/openroad/common/resizer.tcl
 
-load_rsz_corners
 read_current_odb
 
 unset_propagated_clock [all_clocks]
@@ -42,17 +41,25 @@ if { $::env(DESIGN_REPAIR_BUFFER_OUTPUT_PORTS) } {
     buffer_ports -outputs
 }
 
+set arg_list [list]
+lappend arg_list -verbose
+lappend arg_list -max_wire_length $::env(DESIGN_REPAIR_MAX_WIRE_LENGTH)
+lappend arg_list -slew_margin $::env(DESIGN_REPAIR_MAX_SLEW_PCT)
+lappend arg_list -cap_margin $::env(DESIGN_REPAIR_MAX_CAP_PCT)
+if { [info exists ::env(DESIGN_REPAIR_MAX_UTILIZATION)] } {
+    lappend arg_list -max_utilization $::env(DESIGN_REPAIR_MAX_UTILIZATION)
+}
+if { [info exists ::env(DESIGN_REPAIR_BUFFER_GAIN)] } {
+    lappend arg_list -buffer_gain $::env(DESIGN_REPAIR_BUFFER_GAIN)
+}
 # Repair Design
-repair_design -verbose \
-    -max_wire_length $::env(DESIGN_REPAIR_MAX_WIRE_LENGTH) \
-    -slew_margin $::env(DESIGN_REPAIR_MAX_SLEW_PCT) \
-    -cap_margin $::env(DESIGN_REPAIR_MAX_CAP_PCT)
+log_cmd repair_design {*}$arg_list
 
 if { $::env(DESIGN_REPAIR_TIE_FANOUT) } {
     # repair tie lo fanout
-    repair_tie_fanout -separation $::env(DESIGN_REPAIR_TIE_SEPARATION) $::env(SYNTH_TIELO_CELL)
+    repair_tie_fanout -verbose -separation $::env(DESIGN_REPAIR_TIE_SEPARATION) $::env(SYNTH_TIELO_CELL)
     # repair tie hi fanout
-    repair_tie_fanout -separation $::env(DESIGN_REPAIR_TIE_SEPARATION) $::env(SYNTH_TIEHI_CELL)
+    repair_tie_fanout -verbose -separation $::env(DESIGN_REPAIR_TIE_SEPARATION) $::env(SYNTH_TIEHI_CELL)
 }
 
 report_floating_nets -verbose

librelane/scripts/openroad/repair_design_postgrt.tcl

@@ -14,7 +14,6 @@
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 source $::env(SCRIPTS_DIR)/openroad/common/resizer.tcl
 
-load_rsz_corners
 read_current_odb
 
 set_propagated_clock [all_clocks]
@@ -31,11 +30,19 @@ source $::env(SCRIPTS_DIR)/openroad/common/grt.tcl
 #}
 estimate_parasitics -global_routing
 
-# Repair design
-repair_design -verbose \
-    -max_wire_length $::env(GRT_DESIGN_REPAIR_MAX_WIRE_LENGTH) \
-    -slew_margin $::env(GRT_DESIGN_REPAIR_MAX_SLEW_PCT) \
-    -cap_margin $::env(GRT_DESIGN_REPAIR_MAX_CAP_PCT)
+# Repair Design
+set arg_list [list]
+lappend arg_list -verbose
+lappend arg_list -max_wire_length $::env(GRT_DESIGN_REPAIR_MAX_WIRE_LENGTH)
+lappend arg_list -slew_margin $::env(GRT_DESIGN_REPAIR_MAX_SLEW_PCT)
+lappend arg_list -cap_margin $::env(GRT_DESIGN_REPAIR_MAX_CAP_PCT)
+if { [info exists ::env(GRT_DESIGN_REPAIR_MAX_UTILIZATION)] } {
+    lappend arg_list -max_utilization $::env(GRT_DESIGN_REPAIR_MAX_UTILIZATION)
+}
+if { [info exists ::env(GRT_DESIGN_REPAIR_BUFFER_GAIN)] } {
+    lappend arg_list -buffer_gain $::env(GRT_DESIGN_REPAIR_BUFFER_GAIN)
+}
+log_cmd repair_design {*}$arg_list
 
 # Re-DPL and GRT
 source $::env(SCRIPTS_DIR)/openroad/common/dpl.tcl

librelane/scripts/openroad/rsz_timing_postcts.tcl

@@ -1,4 +1,4 @@
-# Copyright 2020-2023 Efabless Corporation
+# Copyright 2020-2024 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -14,7 +14,6 @@
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 source $::env(SCRIPTS_DIR)/openroad/common/resizer.tcl
 
-load_rsz_corners
 read_current_odb
 
 set_propagated_clock [all_clocks]
@@ -34,9 +33,11 @@ lappend setup_args -verbose
 lappend setup_args -setup
 lappend setup_args -setup_margin $::env(PL_RESIZER_SETUP_SLACK_MARGIN)
 lappend setup_args -max_buffer_percent $::env(PL_RESIZER_SETUP_MAX_BUFFER_PCT)
-if { $::env(PL_RESIZER_GATE_CLONING) != 1 } {
-    lappend setup_args -skip_gate_cloning
-}
+append_if_not_flag setup_args PL_RESIZER_SETUP_BUFFERING -skip_buffering
+append_if_not_flag setup_args PL_RESIZER_SETUP_BUFFER_REMOVAL -skip_buffer_removal
+append_if_not_flag setup_args PL_RESIZER_SETUP_GATE_CLONING -skip_gate_cloning
+append_if_exists_argument setup_args PL_RESIZER_SETUP_REPAIR_TNS_PCT -repair_tns
+append_if_exists_argument setup_args PL_RESIZER_SETUP_MAX_UTIL_PCT -max_utilization
 
 set hold_args [list]
 lappend hold_args -verbose
@@ -44,16 +45,16 @@ lappend hold_args -hold
 lappend hold_args -setup_margin $::env(PL_RESIZER_SETUP_SLACK_MARGIN)
 lappend hold_args -hold_margin $::env(PL_RESIZER_HOLD_SLACK_MARGIN)
 lappend hold_args -max_buffer_percent $::env(PL_RESIZER_HOLD_MAX_BUFFER_PCT)
-if { $::env(PL_RESIZER_ALLOW_SETUP_VIOS) == 1 } {
-    lappend hold_args -allow_setup_violations
-}
+append_if_flag hold_args PL_RESIZER_ALLOW_SETUP_VIOS -allow_setup_violations
+append_if_exists_argument hold_args PL_RESIZER_HOLD_REPAIR_TNS_PCT -repair_tns
+append_if_exists_argument hold_args PL_RESIZER_HOLD_MAX_UTIL_PCT -max_utilization
 
 if { $::env(PL_RESIZER_FIX_HOLD_FIRST) == 1 } {
-    repair_timing {*}$hold_args
-    repair_timing {*}$setup_args
+    log_cmd repair_timing {*}$hold_args
+    log_cmd repair_timing {*}$setup_args
 } else {
-    repair_timing {*}$setup_args
-    repair_timing {*}$hold_args
+    log_cmd repair_timing {*}$setup_args
+    log_cmd repair_timing {*}$hold_args
 }
 
 # Legalize

librelane/scripts/openroad/rsz_timing_postgrt.tcl

@@ -1,4 +1,4 @@
-# Copyright 2020-2023 Efabless Corporation
+# Copyright 2020-2024 Efabless Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -14,7 +14,6 @@
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 source $::env(SCRIPTS_DIR)/openroad/common/resizer.tcl
 
-load_rsz_corners
 read_current_odb
 
 set_propagated_clock [all_clocks]
@@ -37,9 +36,11 @@ lappend setup_args -verbose
 lappend setup_args -setup
 lappend setup_args -setup_margin $::env(GRT_RESIZER_SETUP_SLACK_MARGIN)
 lappend setup_args -max_buffer_percent $::env(GRT_RESIZER_SETUP_MAX_BUFFER_PCT)
-if { $::env(GRT_RESIZER_GATE_CLONING) != 1 } {
-    lappend setup_args -skip_gate_cloning
-}
+append_if_not_flag setup_args GRT_RESIZER_SETUP_BUFFERING -skip_buffering
+append_if_not_flag setup_args GRT_RESIZER_SETUP_BUFFER_REMOVAL -skip_buffer_removal
+append_if_not_flag setup_args GRT_RESIZER_SETUP_GATE_CLONING -skip_gate_cloning
+append_if_exists_argument setup_args GRT_RESIZER_SETUP_REPAIR_TNS_PCT -repair_tns
+append_if_exists_argument setup_args GRT_RESIZER_SETUP_MAX_UTIL_PCT -max_utilization
 
 set hold_args [list]
 lappend hold_args -verbose
@@ -47,16 +48,16 @@ lappend hold_args -hold
 lappend hold_args -setup_margin $::env(GRT_RESIZER_SETUP_SLACK_MARGIN)
 lappend hold_args -hold_margin $::env(GRT_RESIZER_HOLD_SLACK_MARGIN)
 lappend hold_args -max_buffer_percent $::env(GRT_RESIZER_HOLD_MAX_BUFFER_PCT)
-if { $::env(GRT_RESIZER_ALLOW_SETUP_VIOS) == 1 } {
-    lappend hold_args -allow_setup_violations
-}
+append_if_flag hold_args GRT_RESIZER_ALLOW_SETUP_VIOS -allow_setup_violations
+append_if_exists_argument hold_args GRT_RESIZER_HOLD_REPAIR_TNS_PCT -repair_tns
+append_if_exists_argument hold_args GRT_RESIZER_HOLD_MAX_UTIL_PCT -max_utilization
 
 if { $::env(GRT_RESIZER_FIX_HOLD_FIRST) == 1 } {
-    repair_timing {*}$hold_args
-    repair_timing {*}$setup_args
+    log_cmd repair_timing {*}$hold_args
+    log_cmd repair_timing {*}$setup_args
 } else {
-    repair_timing {*}$setup_args
-    repair_timing {*}$hold_args
+    log_cmd repair_timing {*}$setup_args
+    log_cmd repair_timing {*}$hold_args
 }
 
 # Re-DPL and GRT

librelane/scripts/openroad/sta/check_macro_instances.tcl

@@ -49,5 +49,5 @@ foreach {instance_name macro_name} $::env(_check_macro_instances) {
 }
 
 if { $error_count != 0 } {
-    exit -1
+    exit_unless_gui 1
 }

librelane/scripts/openroad/tapcell.tcl

@@ -14,12 +14,19 @@
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 read_current_odb
 
-tapcell\
-    -distance $::env(FP_TAPCELL_DIST)\
-    -tapcell_master "$::env(WELLTAP_CELL)"\
-    -endcap_master "$::env(ENDCAP_CELL)"\
-    -halo_width_x $::env(FP_MACRO_HORIZONTAL_HALO)\
-    -halo_width_y $::env(FP_MACRO_VERTICAL_HALO)
+set tapcell_args [list]
+append_if_exists_argument tapcell_args FP_TAPCELL_DIST -distance
+append_if_exists_argument tapcell_args WELLTAP_CELL -tapcell_master
+append_if_exists_argument tapcell_args ENDCAP_CELL -endcap_master
 
+if { [llength tapcell_args] } {
+    log_cmd tapcell\
+        -halo_width_x $::env(FP_MACRO_HORIZONTAL_HALO)\
+        -halo_width_y $::env(FP_MACRO_VERTICAL_HALO)\
+        {*}$tapcell_args
+
+} else {
+    puts "\[INFO\] WELLTAP_CELL and ENDCAP_CELL both unspecified. Doing nothing."
+}
 
 write_views

librelane/scripts/openroad/ungpl.tcl

@@ -0,0 +1,23 @@
+# Copyright 2024 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
+read_current_odb
+
+set ::insts [$::block getInsts]
+
+foreach inst $::insts {
+    $inst setPlacementStatus "NONE"
+}
+
+write_views

librelane/state/__init__.py

@@ -20,5 +20,5 @@ This module manages the State of a Design before and after the execution of an
 LibreLane step. The State is essentially a list of views in various formats in
 addition to the cumulative set of metrics created by previous Steps.
 """
-from .design_format import DesignFormat, DesignFormatObject
+from .design_format import DesignFormat
 from .state import State, InvalidState, StateElement

librelane/state/design_format.py

@@ -11,26 +11,38 @@
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 # See the License for the specific language governing permissions and
 # limitations under the License.
-from enum import Enum
-from typing import Dict, Optional
-from dataclasses import dataclass, replace
+from __future__ import annotations
+from dataclasses import dataclass, field, replace
+from typing import Dict, List, Optional, ClassVar
+from deprecated.sphinx import deprecated
+
+
+class DFMetaclass(type):
+    def __getattr__(Self, key: str):
+        if df := Self.factory.get(key):
+            return df
+        raise AttributeError(
+            "Unknown DesignFormat or Type[DesignFormat] attribute",
+            key,
+            Self,
+        )
 
 
 @dataclass
-class DesignFormatObject:
+class DesignFormat(metaclass=DFMetaclass):
     """
     Metadata about the various possible text or binary representations (views)
     of any design.
 
-    For example, ``DesignFormat.NETLIST.value`` has the metadata for Netlist
-    views.
+    For example, ``DesignFormat.nl`` has the metadata for Netlist views.
 
-    :param id: A lowercase alphanumeric identifier for the design format.
-        Some IDs in LibreLane 2.X use dashes. This is an inconsistency that will
-        be addressed in the next major version of LibreLane as it would be a
-        breaking change.
+    :param id: A lowercase alphanumeric/underscore identifier for the design
+        format.
     :param extension: The file extension for designs saved in this format.
-    :param name: A human-readable name for this design format.
+    :param full_name: A human-readable name for this design format.
+    :param alts: A list of alternate ids used to access the DesignFormat by
+        the subscript operator. Includes its OpenLane <3.0.0 enumeration name
+        for limited backwards compatibility.
     :param folder_override: The subdirectory when
         :meth:`librelane.state.State.save_snapshot` is called on a state. If
         unset, the value for ``id`` will be used.
@@ -40,7 +52,8 @@ class DesignFormatObject:
 
     id: str
     extension: str
-    name: str
+    full_name: str
+    alts: List[str] = field(default_factory=list)
     folder_override: Optional[str] = None
     multiple: bool = False
 
@@ -51,145 +64,184 @@ class DesignFormatObject:
         return self.folder_override or self.id
 
     @property
-    def optional(self) -> bool:
-        return self._instance_optional
-
-
-class DesignFormat(Enum):
-    """
-    An `enumeration <https://docs.python.org/3/library/enum.html>`_ of a number
-    of :class:`librelane.state.DesignFormatObject`\\s representing the various
-    possible text or binary representations (views) supported by LibreLane
-    states.
-
-    Members of this enumeration are used as the keys of
-    :class:`librelane.state.State` objects.
-    """
-
-    NETLIST: DesignFormatObject = DesignFormatObject(
-        "nl",
-        "nl.v",
-        "Verilog Netlist",
-    )
-    POWERED_NETLIST: DesignFormatObject = DesignFormatObject(
-        "pnl",
-        "pnl.v",
-        "Powered Verilog Netlist",
-    )
-    POWERED_NETLIST_SDF_FRIENDLY: DesignFormatObject = DesignFormatObject(
-        "pnl-sdf-friendly",
-        "pnl-sdf.v",
-        "Powered Verilog Netlist For SDF Simulation (Without Fill Cells)",
-        folder_override="pnl",
-    )
-    POWERED_NETLIST_NO_PHYSICAL_CELLS: DesignFormatObject = DesignFormatObject(
-        "pnl-npc",
-        "pnl-npc.v",
-        "Powered Verilog Netlist Without Physical Cells (Fill Cells and Diode Cells)",
-        folder_override="pnl",
-    )
-
-    DEF: DesignFormatObject = DesignFormatObject(
-        "def",
-        "def",
-        "Design Exchange Format",
-    )
-    LEF: DesignFormatObject = DesignFormatObject(
-        "lef",
-        "lef",
-        "Library Exchange Format",
-    )
-    OPENROAD_LEF: DesignFormatObject = DesignFormatObject(
-        "openroad-lef",
-        "openroad.lef",
-        "Library Exchange Format Generated by OpenROAD",
-        folder_override="lef",
-    )
-    ODB: DesignFormatObject = DesignFormatObject(
-        "odb",
-        "odb",
-        "OpenDB Database",
+    @deprecated(
+        "The DesignFormat is directly returned now, no need for .value",
+        version="3.0.0",
+        action="once",
     )
+    def value(self) -> DesignFormat:
+        return self
 
-    SDC: DesignFormatObject = DesignFormatObject(
-        "sdc",
-        "sdc",
-        "Design Constraints",
-    )
-    SDF: DesignFormatObject = DesignFormatObject(
-        "sdf",
-        "sdf",
-        "Standard Delay Format",
-        multiple=True,
-    )
-    SPEF: DesignFormatObject = DesignFormatObject(
-        "spef",
-        "spef",
-        "Standard Parasitics Extraction Format",
-        multiple=True,  # nom, min, max, ...
-    )
-    LIB: DesignFormatObject = DesignFormatObject(
-        "lib",
-        "lib",
-        "LIB Timing Library Format",
-        multiple=True,
-    )
-    SPICE: DesignFormatObject = DesignFormatObject(
-        "spice",
-        "spice",
-        "Simulation Program with Integrated Circuit Emphasis",
-    )
-
-    MAG: DesignFormatObject = DesignFormatObject(
-        "mag",
-        "mag",
-        "Magic VLSI View",
-    )
+    @property
+    def optional(self) -> bool:
+        return self._instance_optional
 
-    GDS: DesignFormatObject = DesignFormatObject(
-        "gds",
-        "gds",
-        "GDSII Stream",
-    )
-    MAG_GDS: DesignFormatObject = DesignFormatObject(
-        "mag_gds",
-        "magic.gds",
-        "GDSII Stream (Magic)",
-    )
-    KLAYOUT_GDS: DesignFormatObject = DesignFormatObject(
-        "klayout_gds",
-        "klayout.gds",
-        "GDSII Stream (KLayout)",
+    @property
+    @deprecated(
+        ".name has been removed because it's redundant, use .id",
+        version="3.0.0",
+        action="once",
     )
+    def name(self) -> str:
+        return self.id
 
-    JSON_HEADER: DesignFormatObject = DesignFormatObject(
-        "json_h",
-        "h.json",
-        "Design JSON Header File",
-    )
-    VERILOG_HEADER: DesignFormatObject = DesignFormatObject(
-        "vh",
-        "vh",
-        "Verilog Header",
-    )
+    def register(self):
+        self.__class__.factory.register(self)
 
     def __str__(self) -> str:
-        return self.value.id
+        return self.id
+
+    def __hash__(self):
+        return hash(self.id)
 
     @staticmethod
+    @deprecated(
+        "Use DesignFormat.factory.get",
+        version="3.0.0",
+        action="once",
+    )
     def by_id(id: str) -> Optional["DesignFormat"]:
-        return _designformat_by_id.get(id)
+        return DesignFormat.factory.get(id)
+
+    class DesignFormatFactory(object):
+        """
+        A factory singleton for DesignFormats, allowing them to be registered
+        and then retrieved by a string name.
+
+        See https://en.wikipedia.org/wiki/Factory_(object-oriented_programming) for
+        a primer.
+        """
+
+        _registry: ClassVar[Dict[str, DesignFormat]] = {}
+
+        @classmethod
+        def register(Self, df: DesignFormat) -> DesignFormat:
+            """
+            Adds a DesignFormat to the registry using its
+            :attr:`DesignFormat.id`, :attr:`DesignFormat.name` and
+            :attr:`DesignFormat.alts` attributes.
+            """
+            Self._registry[df.id] = df
+            for alt in df.alts:
+                Self._registry[alt] = df
+            return df
+
+        @classmethod
+        def get(Self, name: str) -> Optional[DesignFormat]:
+            """
+            Retrieves a DesignFormat type from the registry using a lookup
+            string.
+
+            :param name: The registered name of the Step. Case-insensitive.
+            """
+            return Self._registry.get(name)
+
+        @classmethod
+        def list(Self) -> List[str]:
+            """
+            :returns: A list of IDs of all registered DesignFormat.
+            """
+            return [cls.id for cls in Self._registry.values()]
+
+    factory: ClassVar = DesignFormatFactory
 
     def mkOptional(self) -> "DesignFormat":
-        # HACK: Create ephemeral DesignFormat copy until 3.0.0 lets us do this
-        # a bit more appropriately.
-        clone = object.__new__(DesignFormat)
-        clone._name_ = self._name_
-        clone._value_ = replace(self._value_)
-        clone._value_._instance_optional = True
-        return clone
-
-
-_designformat_by_id: Dict[str, "DesignFormat"] = {
-    format.value.id: format for format in DesignFormat
-}
+        return replace(self, _instance_optional=True)
+
+
+# Common Design Formats
+DesignFormat(
+    "nl",
+    "nl.v",
+    "Verilog Netlist",
+    alts=["NETLIST"],
+).register()
+
+DesignFormat(
+    "pnl",
+    "pnl.v",
+    "Powered Verilog Netlist",
+    alts=["POWERED_NETLIST"],
+).register()
+
+DesignFormat(
+    "sdf_pnl",
+    "sdf_pnl.v",
+    "Powered Verilog Netlist for SDF Simulation (No Fills)",
+    alts=["SDF_FRIENDLY_POWERED_NETLIST"],
+    folder_override="pnl",
+).register()
+
+DesignFormat(
+    "logical_pnl",
+    "logical_pnl.v",
+    "Logical cell-only Powered Verilog Netlist",
+    alts=["LOGICAL_POWERED_NETLIST"],
+    folder_override="pnl",
+).register()
+
+DesignFormat(
+    "def",
+    "def",
+    "Design Exchange Format",
+    alts=["def_", "DEF"],
+).register()
+
+DesignFormat(
+    "lef",
+    "lef",
+    "Library Exchange Format",
+    alts=["LEF"],
+).register()
+
+DesignFormat(
+    "sdc",
+    "sdc",
+    "Design Constraints",
+    alts=["SDC"],
+).register()
+
+DesignFormat(
+    "sdf",
+    "sdf",
+    "Standard Delay Format",
+    alts=["SDF"],
+    multiple=True,
+).register()
+
+DesignFormat(
+    "spef",
+    "spef",
+    "Standard Parasitics Extraction Format",
+    alts=["SPEF"],
+    multiple=True,  # nom, min, max, ...
+).register()
+
+DesignFormat(
+    "lib",
+    "lib",
+    "LIB Timing Library Format",
+    alts=["LIB"],
+    multiple=True,
+).register()
+
+DesignFormat(
+    "spice",
+    "spice",
+    "Simulation Program with Integrated Circuit Emphasis",
+    alts=["SPICE"],
+).register()
+
+DesignFormat(
+    "gds",
+    "gds",
+    "GDSII Stream",
+    alts=["GDS"],
+).register()
+
+DesignFormat(
+    "vh",
+    "vh",
+    "Verilog Header",
+    alts=["VERILOG_HEADER"],
+).register()