jukefa-asmgen 0.6.0__py3-none-any.whl

asmgen/__init__.py

@@ -0,0 +1,5 @@
+# ------------------------------------------------------------------------------
+# SPDX-License-Identifier: MIT OR GPL-3.0-or-later
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@fz-juelich.de>
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@xcpp.org>
+# ------------------------------------------------------------------------------

asmgen/asmblocks/__init__.py

@@ -0,0 +1,8 @@
+# ------------------------------------------------------------------------------
+# SPDX-License-Identifier: MIT OR GPL-3.0-or-later
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@fz-juelich.de>
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@xcpp.org>
+# ------------------------------------------------------------------------------
+"""
+Module containing ASM generator abstract class and implementations for different ISAs
+"""

asmgen/asmblocks/aarch64/__init__.py

@@ -0,0 +1,9 @@
+# ------------------------------------------------------------------------------
+# SPDX-License-Identifier: MIT OR GPL-3.0-or-later
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@fz-juelich.de>
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@xcpp.org>
+# ------------------------------------------------------------------------------
+"""
+AArch64 asm generator, register types and scalar memory ops
+"""
+from .gen import aarch64

asmgen/asmblocks/aarch64/gen.py

@@ -0,0 +1,259 @@
+# ------------------------------------------------------------------------------
+# SPDX-License-Identifier: MIT OR GPL-3.0-or-later
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@fz-juelich.de>
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@xcpp.org>
+# ------------------------------------------------------------------------------
+"""
+ARM64/AArch64 asm generator and related types
+"""
+
+from copy import deepcopy
+from typing import Union
+
+from ..noarch import compiler_family
+from ..noarch import asmgen,comparison
+from ...registers import (
+    adt_size,
+
+    asm_data_type as adt,
+    greg_base, freg_base
+)
+
+from .types import aarch64_greg,aarch64_freg
+from ...callconv.callconv import callconv
+
+from .opmem import aarch64_load, aarch64_store
+from .opmem import aarch64_prefetch
+from ...registers import asm_data_type as _ADT
+from ..op.operand import operand_modifier as _opd_mod
+from ..op.opmove import opmove_modifier as _move_mod
+from ..op.scalar import BITS_GP as _BITS_GP
+from ..op.opset import opset_modifier as _opset_mod
+from ..op.optransform import optransform_modifier as _opd3_mod
+
+_GP = _ADT.UINT64  # general registers' arithmetic: 64-bit
+
+class aarch64(asmgen):
+    """
+    ARM64/AArch64 asmgen implementation
+    """
+
+    #: -march's base, and the features as its extensions (per backend)
+    MARCH_BASE = "armv8-a"
+    MARCH_EXTENSIONS : dict[str, str] = {}
+
+    def compiler_flags(self, compiler : str = "gcc") -> list[str]:
+        compiler_family(compiler)
+        enabled = self.enabled_features()
+        extensions = [self.MARCH_EXTENSIONS[f] for f in self.FEATURES
+                      if f in enabled and f in self.MARCH_EXTENSIONS]
+        return ["-march=" + "+".join([self.MARCH_BASE] + extensions)]
+
+    #: the nop: nop
+    NOP_BYTES = 4
+    NOP_ENCODING = 0xd503201f
+
+    dt_greg_pfx = {
+            adt.DOUBLE : "x",
+            adt.SINGLE : "w",
+            }
+
+    cb_insts = {
+            'NZ' : 'cbnz',
+            'EZ' : 'cbz',
+            'NE' : 'b.ne',
+            'EQ' : 'b.eq',
+            'LE' : 'b.le',
+            'GE' : 'b.ge',
+            'LT' : 'b.lt',
+            'GT' : 'b.gt',
+            }
+
+    def __init__(self):
+        super().__init__()
+        self.callconvs = {
+            "aapcs64" : callconv(
+                param_regs={ 'greg' : list(range(0, 8)),
+                             'freg' : list(range(0, 8))},
+                caller_save_lists={ 'greg' : list(range(0, 8)) + # func args/return vals
+                                             [8] + # XR, indirect result reg
+                                             list(range(9,16)) + # locals
+                                             [18] # platform reg
+                                        ,
+                                    'freg' : list(range(0, 8)) +
+                                             list(range(16,32))
+                                   },
+                callee_save_lists={ 'greg' : list(range(19,29)) + # Callee-saved
+                                             [29, # Frame Pointer
+                                              30  # Link Register
+                                              ] +
+                                             [31], # SP
+                                    'freg' : list(range(8,16))},
+                spreg=31)
+            }
+        self.load = aarch64_load(asmwrap=self.asmwrap)
+        self.store = aarch64_store(asmwrap=self.asmwrap)
+        self.prefetch = aarch64_prefetch(asmwrap=self.asmwrap)
+        self.default_callconv = "aapcs64"
+
+    def create_callconv(self, name : str = "default"):
+
+        if "default" == name:
+            name = self.default_callconv
+
+        return deepcopy(self.callconvs[name])
+
+    def label(self, *, label : str) -> str:
+        return self.asmwrap(f"{self.labelstr(label)}:")
+
+    def jump(self, *, label : str) -> str:
+        return self.asmwrap(f"b {self.labelstr(label)}")
+
+    def loopbegin(self, *, reg : greg_base,
+                  label : str) -> str:
+        asmblock  = self.asmwrap(f"{self.labelstr(label)}:")
+        asmblock += self.asmwrap(f"sub {reg},{reg},1")
+        return asmblock
+
+    def loopbegin_nz(self, *, reg : greg_base,
+                     label : str,
+                     labelskip : str) -> str:
+        asmblock  = self.asmwrap(f"cmp {reg},0")
+        asmblock += self.asmwrap(f"b.eq {self.labelstr(labelskip)}")
+        asmblock += self.asmwrap(f"{self.labelstr(label)}:")
+        asmblock += self.asmwrap(f"sub {reg},{reg},1")
+        return asmblock
+
+    def loopend(self, *, reg : greg_base,
+                label : str) -> str:
+        asmblock  = self.asmwrap(f"cmp {reg},0")
+        asmblock += self.asmwrap(f"b.ne {self.labelstr(label)}")
+        return asmblock
+
+    def fcb(self, *, reg1, reg2, cmp: comparison, label: str, dt: adt, greg=None) -> str:
+        """
+        cb on FP registers: equality as floating point, so -0.0 equals 0.0
+        and NaN equals nothing
+        """
+        insts = {'EQ': 'b.eq', 'EZ': 'b.eq', 'NE': 'b.ne', 'NZ': 'b.ne',
+                 'LT': 'b.mi', 'LE': 'b.ls', 'GT': 'b.gt', 'GE': 'b.ge'}
+        other = reg2 if reg2 is not None else "#0.0"
+        return self.asmwrap(f"fcmp {reg1},{other}") + \
+            self.asmwrap(f"{insts[cmp.name]} {self.labelstr(label)}")
+
+    def cb(self, *, reg1, reg2, cmp: comparison, label: str,
+           dt: adt | None = None, greg: greg_base | None = None) -> str:
+        if isinstance(reg1, freg_base):
+            return self.fcb(reg1=reg1, reg2=reg2, cmp=cmp, label=label, dt=dt, greg=greg)
+        inst = self.cb_insts[cmp.name]
+        if reg2 is None:
+            return self.asmwrap(f"{inst} {reg1},{self.labelstr(label)}")
+
+        return self.asmwrap(f"cmp {reg1},{reg2}")+\
+            self.asmwrap(f"{inst} {self.labelstr(label)}")
+
+    def jzero(self, *, reg : greg_base,
+              label : str) -> str:
+        asmblock  = self.asmwrap(f"cmp {reg},0")
+        asmblock += self.asmwrap(f"b.eq {self.labelstr(label)}")
+        return asmblock
+
+    def jfzero(self, *, freg1 : freg_base, freg2 : freg_base,
+               greg : greg_base, label : str,
+               dt : adt):
+        asmblock  = self.asmwrap(f"fcmp {freg1},#0.0")
+        asmblock += self.asmwrap(f"b.eq {self.labelstr(label)}")
+        return asmblock
+
+    def shared_registers(self) -> list[tuple[str, str, dict[int, int] | None]]:
+        # a scalar FP register is the low part of the vector register
+        return [("freg", "vreg", None)]
+
+    def reserved_registers(self) -> dict[str, dict[str, int]]:
+        # x18 is the platform register on Apple and Windows
+        return {"greg": {"sp": 31, "lr": 30, "fp": 29, "platform": 18}}
+    def max_gregs(self):
+        return 32
+    def max_mregs(self):
+        return 0
+    def max_fregs(self):
+        return 32
+
+    def kiterkleft_pow2(self, *, kreg : greg_base,
+                        kleftreg : greg_base,
+                        unroll : int) -> str:
+        """
+        kiterkleft variant for unroll values that are powers of 2
+        
+        Can be simplified down to a "right shift" and "and"
+        """
+
+        asmblock = ""
+
+        unrollpower = unroll.bit_length()-1
+
+        # Example unroll=4: kleft = k & 0b0111
+        asmblock += self.asmwrap(f"and {kleftreg},{kreg},#{unroll-1}")
+        # Example unroll=4: k = k >> 2
+        asmblock += self.shift(adreg=kreg, bimm=unrollpower, cdreg=kreg, a_dt=_GP, c_dt=_GP, modifiers={_opd3_mod.SHR})
+
+        return asmblock
+
+    def kiterkleft(self, *, kreg : greg_base,
+                   kleftreg : greg_base,
+                   tmpreg : greg_base,
+                   unroll : int) -> str:
+
+        if unroll.bit_count() == 1:
+            return self.kiterkleft_pow2(kreg=kreg,kleftreg=kleftreg,unroll=unroll)
+
+        # TODO: Division by invariant multiplication (the naive attempt below fails,
+        #       need to read up on it)
+
+        # runroll = (1<<64) // unroll
+        # shift   = 64 - unroll.bit_length()
+        # asmblock = ""
+
+        # # Move reciprocal into tmpreg
+        # asmblock += self.asmwrap(f"mov  {tmpreg}, #{(runroll >>  0) & 0xFFFF}")
+        # asmblock += self.asmwrap(f"movk {tmpreg}, #{(runroll >> 16) & 0xFFFF}, lsl 16")
+        # asmblock += self.asmwrap(f"movk {tmpreg}, #{(runroll >> 32) & 0xFFFF}, lsl 32")
+        # asmblock += self.asmwrap(f"movk {tmpreg}, #{(runroll >> 48) & 0xFFFF}, lsl 48")
+
+
+        # # tmp = k // unroll
+        # asmblock += self.mul_greg_greg(dst=tmpreg, reg1=kreg, reg2=tmpreg)
+        # asmblock += self.shift_greg_right(reg=tmpreg,bit_count=shift)
+        #
+        # # kleft = k - (tmp * unroll)
+        # asmblock += self.mov_greg_imm(reg=kleftreg, imm=unroll)
+        # asmblock += self.asmwrap(f"msub {kleftreg},{tmpreg},{kleftreg},{kreg}")
+
+        # # k = tmp
+        # asmblock += self.mov_greg(src=tmpreg,dst=kreg)
+
+        # return asmblock
+
+
+        # DIV version
+
+        asmblock = ""
+
+        asmblock += self.set(dreg=kleftreg, dt=_GP, modifiers={_opset_mod.CONST}, value=unroll)
+        # tmp = k // unroll
+        asmblock += self.asmwrap(f"udiv {tmpreg},{kreg},{kleftreg}")
+        # kleft = k - (tmp * unroll)
+        asmblock += self.asmwrap(f"msub {kleftreg},{tmpreg},{kleftreg},{kreg}")
+        # k = tmp
+        asmblock += self.move(dregs=[tmpreg, kreg], dts=[_GP, _GP])
+
+
+        return asmblock
+
+
+
+    def greg(self, reg_idx : int) -> greg_base:
+        return aarch64_greg(reg_idx)
+
+    def freg(self, reg_idx : int, dt : adt) -> freg_base:
+        return aarch64_freg(reg_idx=reg_idx, dt=dt)

asmgen/asmblocks/aarch64/opmem/__init__.py

@@ -0,0 +1,11 @@
+# ------------------------------------------------------------------------------
+# SPDX-License-Identifier: MIT OR GPL-3.0-or-later
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@fz-juelich.de>
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@xcpp.org>
+# ------------------------------------------------------------------------------
+"""
+Meta-module for Base AArch64 opmem operations
+"""
+from .load import *
+from .store import *
+from .prefetch import *

asmgen/asmblocks/aarch64/opmem/base.py

@@ -0,0 +1,182 @@
+# ------------------------------------------------------------------------------
+# SPDX-License-Identifier: MIT OR GPL-3.0-or-later
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@fz-juelich.de>
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@xcpp.org>
+# ------------------------------------------------------------------------------
+"""
+Aarch64 opmem operations
+"""
+
+from typing import Callable
+
+from ...op import (
+    opmem,
+    opmem_modifier as mod,
+    opmem_action,
+    operation_signature,
+    operand_modifier as opd_mod,
+)
+from ...op.constraint import ValueType
+from ....registers import asm_data_type as adt, adt_size
+
+from ..types import aarch64_greg, aarch64_freg
+
+from .signatures import make_aarch64_opmem_signatures
+from ...op.opmem import param_signatures
+
+class aarch64_opmem(opmem):
+    """
+    AArch64 scalar instruction with 1 data operand and 1 address operand.
+    Handles standard scalar loads/stores (ldr, str, ldrb, strh, etc.)
+    """
+
+    def __init__(self, action: opmem_action,
+                 asmwrap : Callable[[str],str]):
+        self.action = action
+        self.asmwrap=asmwrap
+
+        sigs = make_aarch64_opmem_signatures()
+        self.signatures = sigs + param_signatures(sigs)
+
+    def all_signatures(self) -> list[operation_signature]:
+        return self.signatures
+
+    @property
+    def inst_base(self):
+        """
+        Base root for the instruction
+        """
+        if self.action == opmem_action.LOAD:
+            return "ldr"
+        if self.action == opmem_action.STORE:
+            return "str"
+        raise ValueError(f"Invalid action: {self.action}")
+
+    # I explicitly want it this way
+    # pylint: disable-next=too-many-branches
+    def diagnose_failure(self,
+                         modifiers: set[mod],
+                         operand_modifiers : dict[str,set[opd_mod]],
+                         kwargs : dict[str,ValueType],
+                         dts : dict[str,adt]):
+
+        if mod.TINDEX in modifiers:
+            raise ValueError(
+                    "Base AArch64 has no ld/st with 2D tile offset indices")
+        if mod.VINDEX in modifiers:
+            raise ValueError(
+                    "Base AArch64 has no ld/st with 1D vector offset indices")
+        #if mod.GLANE in modifiers:
+        #    raise ValueError("Base AArch64 has no GP-reg lane ld/st")
+        #if mod.ILANE in modifiers:
+        #    raise ValueError("Base AArch64 has no immediate lane ld/st")
+        if mod.TOFFSET in modifiers:
+            raise ValueError("Base AArch64 has no ld/st with 2D tile offsets")
+        if mod.VOFFSET in modifiers:
+            raise ValueError("Base AArch64 has no ld/st with vector offsets")
+        if mod.ISTRIDE in modifiers:
+            raise ValueError(
+                    "Base AArch64 has no ld/st with immediate strides")
+        if mod.GSTRIDE in modifiers:
+            raise ValueError("Base AArch64 has no ld/st with GP-reg strides")
+        if mod.STRUCT in modifiers:
+            raise ValueError("Base AArch64 has no structured ld/st")
+        #if mod.BCAST in modifiers:
+        #    raise ValueError("Base AArch64 has no broadcasting ld/st")
+        if mod.MASK in modifiers:
+            raise ValueError("Base AArch64 has no masked ld/st")
+        #if mod.ROW in modifiers:
+        #    raise ValueError("Base AArch64 has no row selection ld/st")
+        #if mod.COL in modifiers:
+        #    raise ValueError("Base AArch64 has no column selection ld/st")
+        if mod.NT in modifiers:
+            raise NotImplementedError("Non-temporals for Base AArch64 not yet implemented")
+
+        # `dts` has one entry per passed `dreg`; ld/st always use exactly one
+        # register, data-less ops (prefetches) use none
+        if self.action in (opmem_action.LOAD, opmem_action.STORE) \
+                and len(dts) != 1:
+            raise ValueError("AArch64 scalar load/store uses exactly one register.")
+
+        if mod.POSTINC in modifiers:
+            if "iinc" in kwargs and "increg" in kwargs:
+                raise ValueError("iinc, increg are mutually exclusive")
+            if "iinc" not in kwargs and "increg" not in kwargs:
+                raise ValueError("Missing one of these parameters: iinc, increg")
+
+        if mod.IOFFSET in modifiers and "ioffset" not in kwargs:
+            raise ValueError("Missing operand: ioffset")
+
+        if mod.GOFFSET in modifiers and "offreg" not in kwargs:
+            raise ValueError("Missing operand: offreg")
+
+    def get_addressing(self,
+                       areg: aarch64_greg,
+                       modifiers: set[mod], **kwargs) -> str:
+        """
+        Constructs the addressing string
+
+        :param areg: address register
+        :param modifiers: operation modifiers
+        
+        :return: string containing the addressing
+        """
+        if mod.PARAM in modifiers:
+            return f"%[{kwargs['param']}]"
+        if not isinstance(areg, aarch64_greg):
+            raise ValueError(f"{areg} is not an aarch64_greg")
+
+        base_addr = f"[{areg}]"
+
+        if mod.POSTINC in modifiers:
+            increg = kwargs.get("increg", None)
+            if increg is not None:
+                return f"{base_addr}, {increg}"
+
+            iinc = kwargs["iinc"]
+            return f"{base_addr}, #{iinc}"
+
+        if mod.IOFFSET in modifiers:
+            ioffset = kwargs["ioffset"]
+            if ioffset == 0:
+                return base_addr
+            return f"[{areg}, #{ioffset}]"
+
+        if mod.GOFFSET in modifiers:
+            offreg = kwargs["offreg"]
+            return f"[{areg}, {offreg}]"
+
+        return base_addr
+
+    def get_inst_mnemonic(self, dt: adt, is_freg: bool) -> str:
+        """
+        Construct instruction mnemonic
+        """
+        base = self.inst_base
+
+        if is_freg:
+            return base
+
+        size = adt_size(dt)
+        if size == 1:
+            return base + "b"
+        if size == 2:
+            return base + "h"
+
+        return base
+
+    def implementation(self, *, dregs: list, agreg : aarch64_greg|None = None,
+                       modifiers: set[mod], **kwargs) -> str:
+
+        if len(dregs) != 1:
+            raise ValueError(
+                    "AArch64 scalar load/store uses exactly one register.")
+
+        a_dt = kwargs['a_dt']
+        dreg = dregs[0].retype(dt=a_dt)
+        is_freg = isinstance(dreg, aarch64_freg)
+
+        inst = self.get_inst_mnemonic(a_dt, is_freg)
+        addressing = self.get_addressing(agreg, modifiers, **kwargs)
+
+        return self.asmwrap(f"{inst} {dreg}, {addressing}")

asmgen/asmblocks/aarch64/opmem/load.py

@@ -0,0 +1,21 @@
+# ------------------------------------------------------------------------------
+# SPDX-License-Identifier: MIT OR GPL-3.0-or-later
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@fz-juelich.de>
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@xcpp.org>
+# ------------------------------------------------------------------------------
+"""
+Base AArch64 load instructions
+"""
+
+from typing import Callable
+
+from ...op import opmem_action as action
+from .base import aarch64_opmem
+
+class aarch64_load(aarch64_opmem):
+    """
+    RISC-V freg and greg loads
+    """
+
+    def __init__(self, asmwrap : Callable[[str],str]):
+        super().__init__(action=action.LOAD, asmwrap=asmwrap)

asmgen/asmblocks/aarch64/opmem/prefetch.py

@@ -0,0 +1,40 @@
+# ------------------------------------------------------------------------------
+# SPDX-License-Identifier: MIT OR GPL-3.0-or-later
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@fz-juelich.de>
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@xcpp.org>
+# ------------------------------------------------------------------------------
+"""
+Base AArch64 prefetch instructions
+"""
+
+from typing import Callable
+
+from ...op import opmem_action as action
+from ...op import opmem_modifier as mod
+from ...op import operand_modifier as opd_mod
+from ..types import aarch64_greg
+from .base import aarch64_opmem
+from .signatures import make_aarch64_prefetch_signatures
+
+class aarch64_prefetch(aarch64_opmem):
+    """
+    Base AArch64 prefetch (prfm PLDL1KEEP).
+
+    Data-less opmem (no dregs/dt). Cache level/locality/target selection
+    is not exposed yet.
+    """
+
+    def __init__(self,
+                 asmwrap : Callable[[str],str]):
+        super().__init__(action=action.PREFETCH, asmwrap=asmwrap)
+        self.signatures = make_aarch64_prefetch_signatures()
+
+    # pylint: disable-next=arguments-differ
+    def implementation(self, *, agreg: aarch64_greg,
+                       modifiers: set[mod],
+                       operand_modifiers : dict[str,set[opd_mod]],
+                       **kwargs) -> str:
+        del operand_modifiers
+
+        addressing = self.get_addressing(agreg, modifiers, **kwargs)
+        return self.asmwrap(f"prfm PLDL1KEEP, {addressing}")

asmgen/asmblocks/aarch64/opmem/signatures.py

@@ -0,0 +1,134 @@
+# ------------------------------------------------------------------------------
+# SPDX-License-Identifier: MIT OR GPL-3.0-or-later
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@fz-juelich.de>
+# Copyright (C) 2021 Stepan Nassyr <s.nassyr@xcpp.org>
+# ------------------------------------------------------------------------------
+"""
+Valid signatures for AArch64  opmem operations
+"""
+
+from ....registers import adt_size
+from ...op.constraint import either_constraint, minmax_constraint, multiple_constraint
+from ...op import (
+    operation_signature as sig,
+    operand_shape as osh,
+    operand_type as ot,
+    operand_role as orl,
+    register_type as rt,
+    opmem_modifier as mod
+)
+
+from ....registers import asm_data_type as adt, adt_is_float
+
+_FLOATS = [adt.FP64, adt.FP32, adt.FP16, adt.FP8E4M3, adt.FP8E5M2]
+_INTS = [adt.SINT64, adt.SINT32, adt.SINT16, adt.SINT8,
+         adt.UINT64, adt.UINT32, adt.UINT16, adt.UINT8]
+
+
+def _scale(dt) -> int:
+    """
+    What an unsigned immediate offset is scaled by: the access's size - a
+    prefetch's (no data) 8, as prfm's
+    """
+    return 8 if dt is None else adt_size(dt)
+
+def make_aarch64_opmem_signatures():
+    """
+    Generate signatures for AArch64 opmem operations
+    """
+    sigs = []
+
+
+    for dt in _FLOATS+_INTS:
+
+        a_rt = rt.FP if adt_is_float(dt) else rt.GP
+
+        # (f)ld without offset
+        sigs.append(sig(
+        modifiers=set(),
+        structural_params={},
+        operands={
+            'adreg': osh(ot.REGISTER, orl.DATA, a_rt, dt),
+            'agreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64)
+            }
+        ))
+        # (f)ld with immediate offset
+        sigs.append(sig(
+        modifiers={mod.IOFFSET},
+        structural_params={},
+        operands={
+            'adreg': osh(ot.REGISTER, orl.DATA, a_rt, dt),
+            'agreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64),
+            'ioffset': osh(ot.IMMEDIATE, orl.PARAM, None, adt.SINT64, value_constraints=[either_constraint(options=[
+                [minmax_constraint(minval=0, maxval=4095*_scale(dt)), multiple_constraint(multiple=_scale(dt))],
+                [minmax_constraint(minval=-256, maxval=255)]])])
+            }
+        ))
+        # (f)ld with gp-reg offset
+        sigs.append(sig(
+        modifiers={mod.GOFFSET},
+        structural_params={},
+        operands={
+            'adreg': osh(ot.REGISTER, orl.DATA, a_rt, dt),
+            'agreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64),
+            'offreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64)
+            }
+        ))
+        # (f)ld with postinc immediate offset
+        sigs.append(sig(
+        modifiers={mod.POSTINC},
+        structural_params={},
+        operands={
+            'adreg': osh(ot.REGISTER, orl.DATA, a_rt, dt),
+            'agreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64),
+            'iinc': osh(ot.IMMEDIATE, orl.PARAM, None, adt.SINT64, value_constraints=[minmax_constraint(minval=-256, maxval=255)])
+            }
+        ))
+        # (f)ld with postinc gp-reg offset
+        sigs.append(sig(
+        modifiers={mod.POSTINC},
+        structural_params={},
+        operands={
+            'adreg': osh(ot.REGISTER, orl.DATA, a_rt, dt),
+            'agreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64),
+            'increg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64)
+            }
+        ))
+
+    return sigs
+
+
+def make_aarch64_prefetch_signatures():
+    """
+    Generate signatures for AArch64 prefetch operations
+    """
+    return [
+        # prefetch without offset
+        sig(
+        modifiers=set(),
+        structural_params={},
+        operands={
+            'agreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64)
+            }
+        ),
+        # prefetch with immediate offset
+        sig(
+        modifiers={mod.IOFFSET},
+        structural_params={},
+        operands={
+            'agreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64),
+            'ioffset': osh(ot.IMMEDIATE, orl.PARAM, None, adt.SINT64, value_constraints=[either_constraint(options=[
+                [minmax_constraint(minval=0, maxval=4095*_scale(None)), multiple_constraint(multiple=_scale(None))],
+                [minmax_constraint(minval=-256, maxval=255)]])])
+            }
+        ),
+        # prefetch with gp-reg offset
+        sig(
+        modifiers={mod.GOFFSET},
+        structural_params={},
+        operands={
+            'agreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64),
+            'offreg': osh(ot.REGISTER, orl.ADDRESS, rt.GP, adt.UINT64)
+            }
+        ),
+    ]