floogen 0.8.0__py3-none-any.whl

floogen/__init__.py

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+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0

floogen/cli.py

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+#!/usr/bin/env python3
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Author: Tim Fischer <fischeti@iis.ee.ethz.ch>
+
+import argparse
+from pathlib import Path
+from importlib.resources import files
+
+from mako.template import Template
+
+from floogen.config_parser import parse_config
+from floogen.query import handle_query
+from floogen.model.network import Network
+from floogen.utils import verible_format
+
+tpl_dir = files("floogen") / "templates"
+
+def render_template(context: dict, tpl: Path,
+                    outdir: Path = None, file_name: str = None,
+                    format_output: bool=False, verible_fmt_bin: str = None,
+                    verible_fmt_args: str = None):
+    """Render a template, format if requested and write to file or print to stdout."""
+    if not tpl.exists():
+        # Search in the internal template directory if the template exists there
+        if (tpl_dir / tpl.name).exists():
+            tpl = tpl_dir / tpl.name
+        else:
+            raise FileNotFoundError(f"Template not found: {tpl}")
+    rendered = Template(filename=str(tpl.resolve())).render(**context)
+    if format_output:
+        rendered = verible_format(rendered, verible_fmt_bin, verible_fmt_args)
+    if outdir:
+        outdir.mkdir(parents=True, exist_ok=True)
+        if file_name:
+            outfile = outdir / file_name
+        else:
+            outfile = outdir / tpl.stem
+        with open(outfile, "w+", encoding="utf-8") as f:
+            f.write(rendered)
+    else:
+        print(rendered)
+
+
+def build_parser() -> argparse.ArgumentParser:
+    """Parse the command line arguments."""
+
+    # Parser that holds all common options
+    common = argparse.ArgumentParser(add_help=False)
+    common.add_argument(
+        "-c", "--config", type=Path, required=True,
+        help="Path to the configuration file."
+    )
+    common.add_argument(
+        "-o", "--outdir", type=Path, required=False,
+        help=(
+            "Path to the output directory of the generated output files. "
+            "If not specified, the files are printed to stdout."
+        ),
+    )
+
+    # Parser for SystemVerilog formatting options
+    sv_format = argparse.ArgumentParser(add_help=False)
+    sv_format.add_argument(
+        "--no-format",
+        dest="no_format",
+        action="store_true",
+        help="Do not format the output.",
+    )
+    sv_format.add_argument(
+        "--verible-fmt-bin",
+        type=str,
+        default=None,
+        help="Overwrite default `verible-verilog-format` binary.",
+    )
+    sv_format.add_argument(
+        "--verible-fmt-args",
+        type=str,
+        default=None,
+        help="Additional arguments to pass to `verible-verilog-format`.",
+    )
+    sv_format.add_argument(
+        "--name",
+        type=str,
+        default=None,
+        help="Override the module/package name and prefix for generated files."
+    )
+
+    # Top-level parser
+    parser = argparse.ArgumentParser(
+        description="FlooGen: A Network-on-Chip Generator for FlooNoC",
+        add_help=True,
+    )
+
+    subparsers = parser.add_subparsers(dest="command")
+
+    # floogen rtl -> pkg + top
+    subparsers.add_parser(
+        "rtl",
+        parents=[common, sv_format],
+        add_help=True,
+        help="Generate both the NoC package and top-module.",
+    )
+
+    # floogen pkg
+    subparsers.add_parser(
+        "pkg",
+        parents=[common, sv_format],
+        add_help=True,
+        help="Generate the NoC package.",
+    )
+
+    # floogen top
+    subparsers.add_parser(
+        "top",
+        parents=[common, sv_format],
+        add_help=True,
+        help="Generate the NoC top-module.",
+    )
+
+    # floogen rdl
+    p_rdl = subparsers.add_parser(
+        "rdl",
+        parents=[common],
+        add_help=True,
+        help="Generate the SystemRDL of all endpoint address regions.",
+    )
+    p_rdl.add_argument(
+        "--as-mem",
+        dest="as_mem",
+        action="store_true",
+        default=False,
+        help="Add memory blocks for address regions without 'rdl_name' declared.",
+    )
+    p_rdl.add_argument(
+        "--memwidth",
+        dest="memwidth",
+        type=int,
+        default=8,
+        help="Use the memory width of the RDL address region as the width of the memory block.",
+    )
+
+    # floogen templates <template1> <template2> ...
+    p_templates = subparsers.add_parser(
+        "template",
+        parents=[common, sv_format],
+        add_help=True,
+        help="Render custom (external) templates.",
+    )
+    p_templates.add_argument(
+        "template",
+        type=Path,
+        nargs="+",
+        help="Path to external template to render. Multiple templates can be specified.",
+    )
+
+    # floogen visualize
+    subparsers.add_parser(
+        "visualize",
+        parents=[common],
+        add_help=True,
+        help="Visualize the network graph.",
+    )
+
+    # floogen query <key>
+    p_query = subparsers.add_parser(
+        "query",
+        parents=[common],
+        add_help=True,
+        help="Query a specific key in the configuration.",
+    )
+    p_query.add_argument(
+        "query",
+        type=str,
+        help="Key to query in the configuration.",
+    )
+
+    return parser
+
+
+def main():
+    """Generates the network."""
+
+    parser = build_parser()
+    args = parser.parse_args()
+
+    if args.command is None:
+        parser.print_help()
+        return 0
+
+    network = parse_config(Network, args.config)
+
+    network.create_network()
+    network.compile_network()
+    network.gen_routing_info()
+
+    # The general context to pass to all templates
+    context = {"noc": network}
+
+    # Additional render arguments
+    render_kwargs = {"outdir": args.outdir}
+
+    # Command specific render arguments
+    match args.command:
+        case "rtl" | "pkg" | "top" | "template":
+            render_kwargs["format_output"] = not args.no_format
+            render_kwargs["verible_fmt_bin"] = args.verible_fmt_bin
+            render_kwargs["verible_fmt_args"] = args.verible_fmt_args
+            context["name"] = args.name or network.name
+            pkg_file_name = f"floo_{args.name or network.name}_noc_pkg.sv"
+            top_file_name = f"floo_{args.name or network.name}_noc.sv"
+        case "rdl":
+            rdl_file_name = f"{network.name}_addrmap.rdl"
+
+
+    match args.command:
+        case "rtl":
+            render_template(context,
+                tpl=tpl_dir / "floo_noc_pkg.sv.mako",
+                file_name=pkg_file_name,
+                **render_kwargs,
+            )
+            render_template(context,
+                tpl=tpl_dir / "floo_noc.sv.mako",
+                file_name=top_file_name,
+                **render_kwargs,
+            )
+        case "pkg":
+            render_template(context,
+                tpl=tpl_dir / "floo_noc_pkg.sv.mako",
+                file_name=pkg_file_name,
+                **render_kwargs,
+            )
+        case "top":
+            render_template(context,
+                tpl=tpl_dir / "floo_noc.sv.mako",
+                file_name=top_file_name,
+                **render_kwargs,
+            )
+        case "rdl":
+            context["rdl_as_mem"] = args.as_mem
+            context["rdl_memwidth"] = args.memwidth
+            render_template(context,
+                tpl=tpl_dir / "floo_addrmap.rdl.mako",
+                file_name=rdl_file_name,
+                **render_kwargs,
+            )
+        case "template":
+            for tpl in args.template:
+                render_template(context,
+                    tpl=tpl,
+                    **render_kwargs,
+                )
+        case "visualize":
+            if args.outdir:
+                network.visualize(filename=args.outdir / (network.name + ".pdf"))
+            else:
+                network.visualize(savefig=False)
+        case "query":
+            handle_query(network, args.query)
+
+
+if __name__ == "__main__":
+    main()

floogen/config_parser.py

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+#!/usr/bin/env python3
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Author: Tim Fischer <fischeti@iis.ee.ethz.ch>
+
+from pathlib import Path
+import logging
+from typing import List, Union, Tuple, Mapping, TypeVar
+
+from pydantic import ValidationError, BaseModel
+
+from ruamel.yaml.comments import CommentedMap
+from ruamel.yaml import YAMLError
+import ruamel.yaml
+
+import click
+
+logger = logging.getLogger("padrick.ConfigParser")
+
+
+def get_error_context(config_file: Path, line, column, context_before=4, context_after=4):
+    """Retrieves the context surrounding an error in a configuration file."""
+    lines_to_return = []
+    with config_file.open() as file:
+        for line_idx, line in enumerate(file.readlines()):
+            if line_idx + 1 == line:
+                lines_to_return.append(line)
+                lines_to_return.append(click.style(column * " " + "^\n", blink=True, fg="yellow"))
+            elif line_idx + 1 >= line - context_before and line_idx + 1 <= line + context_after:
+                lines_to_return.append(line)
+    return "".join(lines_to_return)
+
+
+def get_human_readable_error_path(config_data: dict, error_location: List[Union[str, int]]):
+    """Transforms a list of path segments into a human readable string."""
+    transformed_path_segments = []
+    node = config_data
+    for path_segment in error_location:
+        try:
+            node = node[path_segment]
+        except KeyError:
+            transformed_path_segments.append(path_segment)
+            break
+        if isinstance(path_segment, int):
+            transformed_path_segments.append(node.get("name", path_segment))
+        else:
+            transformed_path_segments.append(path_segment)
+    return "->".join(transformed_path_segments)
+
+
+def get_file_location(
+    config_data: CommentedMap, error_location: List[Union[str, int]]
+) -> Tuple[Tuple[int, int], Mapping]:
+    """Retrieves the location of an error in a configuration file."""
+    node = config_data
+    location = (node.lc.line + 1, node.lc.col)
+    subtree = node
+    for path_segment in error_location:
+        try:
+            location = (node.lc.data[path_segment][0] + 1, node.lc.data[path_segment][1])
+            node = node[path_segment]
+            if isinstance(node, Mapping):
+                subtree = node
+        except KeyError:
+            break
+    return location, subtree
+
+
+T = TypeVar("T", bound=BaseModel)
+
+
+def parse_config(cls: T, config_file: Path) -> Union[T, None]:
+    """Parses a configuration file and returns a validated model."""
+    with config_file.open() as file:
+        try:
+            yaml = ruamel.yaml.YAML(typ="rt")
+            # enable support for !include directives (see pyyaml-include package)
+            # if not include_base_dir:
+            #     include_base_dir = config_file.parent
+            # if not ignore_includes:
+            #     include_constructor = YamlIncludeConstructor(base_dir=str(include_base_dir))
+            # else:
+            #     include_constructor = IgnoreIncludeConstructor
+            # yaml.register_class(include_constructor)
+            config_data = yaml.load(file)
+            # config_data = ruamel.yaml.load(file, Loader=ruamel.yaml.RoundTripLoader)
+        except YAMLError as e:
+            logger.error("Error while parsing config_file:\n %s", e)
+            return None
+        try:
+            model = cls.model_validate(config_data)
+            return model
+        except ValidationError as e:
+            logger.error(
+                "Encountered %s validation errors while parsing the configuration file:",
+                len(e.errors()),
+            )
+            for error in e.errors():
+                if error["type"] == "extra":
+                    error[
+                        "msg"
+                    ] = f'Unknown field {error["loc"][-1]}. \
+                        Did you mispell the field name?'
+                if error["type"] == "missing":
+                    error["msg"] = f'Missing field \'{error["loc"][-1]}\''
+                else:
+                    error["msg"] = f'{error["msg"]} (field \'{error["loc"][-1]}\')'
+                # error_path = get_human_readable_error_path(config_data, error["loc"])
+                (line, column), _ = get_file_location(config_data, error["loc"])
+                error_context = get_error_context(config_file, line, column, context_after=10)
+                logger.error("Line %s, Column %s:", line, column)
+                logger.error("...\n%s\n...", error_context)
+                logger.error("Error: %s", error["msg"])
+            return None

floogen/examples/axi_mesh_id.yml

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+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: axi_mesh
+description: "AXI mesh configuration with table-based routing for FlooGen"
+network_type: "axi"
+
+routing:
+  route_algo: "ID"
+  use_id_table: true
+
+protocols:
+  - name: "axi_in"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 48
+    id_width: 4
+    user_width: 1
+    type_prefix: # prevents `axi_axi` prefix
+  - name: "axi_out"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 48
+    id_width: 2
+    user_width: 1
+    type_prefix: # prevents `axi_axi` prefix
+
+endpoints:
+  - name: "cluster"
+    array: [4, 4]
+    addr_range:
+      base: 0x0000_0000_0000
+      size: 0x0000_0001_0000
+    mgr_port_protocol:
+      - "axi_in"
+    sbr_port_protocol:
+      - "axi_out"
+  - name: "hbm"
+    array: [4]
+    addr_range:
+      base: 0x0000_8000_0000
+      size: 0x0000_0001_0000
+    sbr_port_protocol:
+      - "axi_out"
+
+routers:
+  - name: "router"
+    array: [4, 4]
+    degree: 5
+
+connections:
+  - src: "cluster"
+    dst: "router"
+    src_range:
+    - [0, 3]
+    - [0, 3]
+    dst_range:
+    - [0, 3]
+    - [0, 3]
+    dst_dir: "Eject"
+  - src: "hbm"
+    dst: "router"
+    src_range:
+    - [0, 3]
+    dst_range:
+    - [0, 0]
+    - [0, 3]
+    dst_dir: "West"

floogen/examples/axi_mesh_src.yml

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+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: axi_mesh
+description: "AXI mesh configuration with source-based routing for FlooGen"
+network_type: "axi"
+
+routing:
+  route_algo: "SRC"
+  use_id_table: true
+
+protocols:
+  - name: "axi_in"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 48
+    id_width: 4
+    user_width: 1
+    type_prefix: # prevents `axi_axi` prefix
+  - name: "axi_out"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 48
+    id_width: 2
+    user_width: 1
+    type_prefix: # prevents `axi_axi` prefix
+
+endpoints:
+  - name: "cluster"
+    array: [4, 4]
+    addr_range:
+      base: 0x0000_0000_0000
+      size: 0x0000_0001_0000
+    mgr_port_protocol:
+      - "axi_in"
+    sbr_port_protocol:
+      - "axi_out"
+  - name: "hbm"
+    array: [4]
+    addr_range:
+      base: 0x0000_8000_0000
+      size: 0x0000_0001_0000
+    sbr_port_protocol:
+      - "axi_out"
+
+routers:
+  - name: "router"
+    array: [4, 4]
+    degree: 5
+
+connections:
+  - src: "cluster"
+    dst: "router"
+    src_range:
+    - [0, 3]
+    - [0, 3]
+    dst_range:
+    - [0, 3]
+    - [0, 3]
+    dst_dir: "Eject"
+  - src: "hbm"
+    dst: "router"
+    src_range:
+    - [0, 3]
+    dst_range:
+    - [0, 0]
+    - [0, 3]
+    dst_dir: "West"

floogen/examples/axi_mesh_xy.yml

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+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: axi_mesh
+description: "AXI mesh configuration with XY routing for FlooGen"
+network_type: "axi"
+
+routing:
+  route_algo: "XY"
+  use_id_table: true
+
+protocols:
+  - name: "axi_in"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 48
+    id_width: 4
+    user_width: 1
+    type_prefix: # prevents `axi_axi` prefix
+  - name: "axi_out"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 48
+    id_width: 2
+    user_width: 1
+    type_prefix: # prevents `axi_axi` prefix
+
+endpoints:
+  - name: "cluster"
+    array: [4, 4]
+    addr_range:
+      base: 0x0000_0000_0000
+      size: 0x0000_0001_0000
+    mgr_port_protocol:
+      - "axi_in"
+    sbr_port_protocol:
+      - "axi_out"
+  - name: "hbm"
+    array: [4]
+    addr_range:
+      base: 0x0000_8000_0000
+      size: 0x0000_0001_0000
+    sbr_port_protocol:
+      - "axi_out"
+
+routers:
+  - name: "router"
+    array: [4, 4]
+    degree: 5
+
+connections:
+  - src: "cluster"
+    dst: "router"
+    src_range:
+    - [0, 3]
+    - [0, 3]
+    dst_range:
+    - [0, 3]
+    - [0, 3]
+    dst_dir: "Eject"
+  - src: "hbm"
+    dst: "router"
+    src_range:
+    - [0, 3]
+    dst_range:
+    - [0, 0]
+    - [0, 3]
+    dst_dir: "West"

floogen/examples/collective.yml

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+# Copyright 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Example: full collective support
+#   - narrow + wide multicast
+#   - barrier (LSB-AND)
+#   - narrow reduction: all integer ops (Add, Mul, MinS, MinU, MaxS, MaxU)
+#   - wide reduction: only Add and Max (selective ops example)
+
+name: nw_mesh_collective
+description: "4x4 NW mesh with full collective operation support"
+network_type: "narrow-wide"
+
+routing:
+  route_algo: "XY"
+  use_id_table: true
+  collective:
+    en_narrow_multicast: true
+    en_wide_multicast: true
+    en_barrier: true
+    en_narrow_reduction:
+      rd_pipeline_depth: 1   # all integer ops, custom hw config
+    en_wide_reduction:       # selective FP ops, default hw config
+      ops: [Add, Max]
+      rd_pipeline_depth: 5
+      cut_offload_intf: true
+  # decouple_rw: Phys
+  vc_impl: preempt
+
+protocols:
+  - name: "narrow_in"
+    type: "narrow"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 48
+    id_width: 5
+    user_width:
+      collective_mask: 48
+      collective_op: 4
+      user: 5
+  - name: "narrow_out"
+    type: "narrow"
+    protocol: "AXI4"
+    data_width: 64
+    addr_width: 48
+    id_width: 2
+    user_width:
+      collective_mask: 48
+      collective_op: 4
+      user: 5
+  - name: "wide_in"
+    type: "wide"
+    protocol: "AXI4"
+    data_width: 512
+    addr_width: 48
+    id_width: 3
+    user_width:
+      collective_mask: 48
+      collective_op: 4
+  - name: "wide_out"
+    type: "wide"
+    protocol: "AXI4"
+    data_width: 512
+    addr_width: 48
+    id_width: 1
+    user_width:
+      collective_mask: 48
+      collective_op: 4
+
+endpoints:
+  - name: "cluster"
+    array: [4, 4]
+    addr_range:
+      base: 0x2000_0000
+      size: 0x0004_0000
+      en_collective: true
+    mgr_port_protocol:
+      - "narrow_in"
+      - "wide_in"
+    sbr_port_protocol:
+      - "narrow_out"
+      - "wide_out"
+
+routers:
+  - name: "router"
+    array: [4, 4]
+    degree: 5
+
+connections:
+  - src: "cluster"
+    dst: "router"
+    src_range:
+    - [0, 3]
+    - [0, 3]
+    dst_range:
+    - [0, 3]
+    - [0, 3]
+    dst_dir: "Eject"