esiaccel 0.1.0__cp313-cp313-manylinux_2_27_x86_64.manylinux_2_28_x86_64.whl

esiaccel/codegen.py

@@ -0,0 +1,197 @@
+#  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+#  See https://llvm.org/LICENSE.txt for license information.
+#  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+# Code generation from ESI manifests to source code. C++ header support included
+# with the runtime, though it is intended to be extensible for other languages.
+
+from typing import List, TextIO, Type, Optional
+from .accelerator import AcceleratorConnection
+from .esiCppAccel import ModuleInfo
+from . import types
+
+import argparse
+from pathlib import Path
+import textwrap
+import sys
+
+_thisdir = Path(__file__).absolute().resolve().parent
+
+
+class Generator:
+  """Base class for all generators."""
+
+  language: Optional[str] = None
+
+  def __init__(self, conn: AcceleratorConnection):
+    self.manifest = conn.manifest()
+
+  def generate(self, output_dir: Path, system_name: str):
+    raise NotImplementedError("Generator.generate() must be overridden")
+
+
+class CppGenerator(Generator):
+  """Generate C++ headers from an ESI manifest."""
+
+  language = "C++"
+
+  # Supported bit widths for lone integer types.
+  int_width_support = set([8, 16, 32, 64])
+
+  def get_type_str(self, type: types.ESIType) -> str:
+    """Get the textual code for the storage class of a type.
+
+    Examples: uint32_t, int64_t, CustomStruct."""
+
+    if isinstance(type, (types.BitsType, types.IntType)):
+      if type.bit_width not in self.int_width_support:
+        raise ValueError(f"Unsupported integer width: {type.bit_width}")
+      if isinstance(type, (types.BitsType, types.UIntType)):
+        return f"uint{type.bit_width}_t"
+      return f"int{type.bit_width}_t"
+    raise NotImplementedError(f"Type '{type}' not supported for C++ generation")
+
+  def get_consts_str(self, module_info: ModuleInfo) -> str:
+    """Get the C++ code for a constant in a module."""
+    const_strs: List[str] = [
+        f"static constexpr {self.get_type_str(const.type)} "
+        f"{name} = 0x{const.value:x};"
+        for name, const in module_info.constants.items()
+    ]
+    return "\n".join(const_strs)
+
+  def write_modules(self, output_dir: Path, system_name: str):
+    """Write the C++ header. One for each module in the manifest."""
+
+    for module_info in self.manifest.module_infos:
+      s = f"""
+      /// Generated header for {system_name} module {module_info.name}.
+      #pragma once
+      #include "types.h"
+
+      namespace {system_name} {{
+      class {module_info.name} {{
+      public:
+        {self.get_consts_str(module_info)}
+      }};
+      }} // namespace {system_name}
+      """
+
+      hdr_file = output_dir / f"{module_info.name}.h"
+      with open(hdr_file, "w") as hdr:
+        hdr.write(textwrap.dedent(s))
+
+  def write_type(self, hdr: TextIO, type: types.ESIType):
+    if isinstance(type, (types.BitsType, types.IntType)):
+      # Bit vector types use standard C++ types.
+      return
+    raise NotImplementedError(f"Type '{type}' not supported for C++ generation")
+
+  def write_types(self, output_dir: Path, system_name: str):
+    hdr_file = output_dir / "types.h"
+    with open(hdr_file, "w") as hdr:
+      hdr.write(
+          textwrap.dedent(f"""
+      // Generated header for {system_name} types.
+      #pragma once
+
+      #include <cstdint>
+
+      namespace {system_name} {{
+      """))
+
+      for type in self.manifest.type_table:
+        try:
+          self.write_type(hdr, type)
+        except NotImplementedError:
+          sys.stderr.write(
+              f"Warning: type '{type}' not supported for C++ generation\n")
+
+      hdr.write(
+          textwrap.dedent(f"""
+      }} // namespace {system_name}
+      """))
+
+  def generate(self, output_dir: Path, system_name: str):
+    self.write_types(output_dir, system_name)
+    self.write_modules(output_dir, system_name)
+
+
+def run(generator: Type[Generator] = CppGenerator,
+        cmdline_args=sys.argv) -> int:
+  """Create and run a generator reading options from the command line."""
+
+  argparser = argparse.ArgumentParser(
+      description=f"Generate {generator.language} headers from an ESI manifest",
+      formatter_class=argparse.RawDescriptionHelpFormatter,
+      epilog=textwrap.dedent("""
+        Can read the manifest from either a file OR a running accelerator.
+
+        Usage examples:
+          # To read the manifest from a file:
+          esi-cppgen --file /path/to/manifest.json
+
+          # To read the manifest from a running accelerator:
+          esi-cppgen --platform cosim --connection localhost:1234
+      """))
+
+  argparser.add_argument("--file",
+                         type=str,
+                         default=None,
+                         help="Path to the manifest file.")
+  argparser.add_argument(
+      "--platform",
+      type=str,
+      help="Name of platform for live accelerator connection.")
+  argparser.add_argument(
+      "--connection",
+      type=str,
+      help="Connection string for live accelerator connection.")
+  argparser.add_argument(
+      "--output-dir",
+      type=str,
+      default="esi",
+      help="Output directory for generated files. Recommend adding either `esi`"
+      " or the system name to the end of the path so as to avoid header name"
+      "conflicts. Defaults to `esi`")
+  argparser.add_argument(
+      "--system-name",
+      type=str,
+      default="esi_system",
+      help="Name of the ESI system. For C++, this will be the namespace.")
+
+  if (len(cmdline_args) <= 1):
+    argparser.print_help()
+    return 1
+  args = argparser.parse_args(cmdline_args[1:])
+
+  if args.file is not None and args.platform is not None:
+    print("Cannot specify both --file and --platform")
+    return 1
+
+  conn: AcceleratorConnection
+  if args.file is not None:
+    conn = AcceleratorConnection("trace", f"-:{args.file}")
+  elif args.platform is not None:
+    if args.connection is None:
+      print("Must specify --connection with --platform")
+      return 1
+    conn = AcceleratorConnection(args.platform, args.connection)
+  else:
+    print("Must specify either --file or --platform")
+    return 1
+
+  output_dir = Path(args.output_dir)
+  if output_dir.exists() and not output_dir.is_dir():
+    print(f"Output directory {output_dir} is not a directory")
+    return 1
+  if not output_dir.exists():
+    output_dir.mkdir(parents=True)
+
+  gen = generator(conn)
+  gen.generate(output_dir, args.system_name)
+  return 0
+
+
+if __name__ == '__main__':
+  sys.exit(run())

esiaccel/cosim/Cosim_DpiPkg.sv

@@ -0,0 +1,85 @@
+//===- Cosim_DpiPkg.sv - ESI cosim DPI declarations ---------*- verilog -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Package: Cosim_DpiPkg
+//
+// DPI-exposed funcs for cosimserver cosimulation unit-test.
+//
+//===----------------------------------------------------------------------===//
+
+package Cosim_DpiPkg;
+
+// --------------------- Cosim RPC Server --------------------------------------
+
+// Start cosimserver (spawns server for HW-initiated work, listens for
+// connections from new SW-clients).
+import "DPI-C" sv2cCosimserverInit = function int cosim_init();
+
+// Teardown cosimserver (disconnects from primary server port, stops connections
+// from active clients).
+import "DPI-C" sv2cCosimserverFinish = function void cosim_finish();
+
+// --------------------- Endpoint Management -----------------------------------
+
+// Register simulated device endpoints.
+// - return 0 on success, non-zero on failure (duplicate EP registered).
+import "DPI-C" sv2cCosimserverEpRegister =
+  function int cosim_ep_register(
+    // The endpoint ID.
+    input string endpoint_id,
+    // The ESI type id which the _RPC client_ is sending us.
+    input string from_host_type_id,
+    // The send types max size, in bytes.
+    input int from_host_type_size,
+    // The ESI type id which we are sending to the _RPC client_.
+    input string to_host_type_id,
+    // The recv types max size, in bytes.
+    input int to_host_type_size);
+
+// --------------------- Endpoint Accessors ------------------------------------
+
+// Attempt to send data to a client.
+// - return 0 on success, negative on failure (unregistered EP).
+import "DPI-C" sv2cCosimserverEpTryPut =
+  function int cosim_ep_tryput(
+    // The ID of the endpoint to which the data should be sent.
+    input string endpoint_id,
+    // A data buffer.
+    input byte unsigned data[],
+    // (Optional) Size of the buffer. If negative, will be dynamically detected.
+    input int data_size = -1
+    );
+
+// Attempt to recieve data from a client.
+//   - Returns negative when call failed (e.g. EP not registered).
+//   - If no message, return 0 with size_bytes == 0.
+//   - Assumes buffer is large enough to contain entire message. Fails if not
+//   large enough. (In the future, will add support for getting the message into
+//   a fixed-size buffer over multiple calls.)
+import "DPI-C" sv2cCosimserverEpTryGet =
+  function int cosim_ep_tryget(
+    // The ID of the endpoint from which data should be recieved.
+    input string endpoint_id,
+    // The buffer in which to put the data. This should be 'output', but the
+    // open source simulator Verilator doesn't seem to have a way to do this.
+    inout byte unsigned data[],
+    // Input: indicates the size of the data[] buffer. If -1, dynamically detect
+    // size.
+    // Output: the size of the message.
+    inout int unsigned data_size
+    );
+
+// --------------------- Manifest ----------------------------------------------
+
+import "DPI-C" sv2cCosimserverSetManifest =
+  function void cosim_set_manifest(
+    input int signed esi_version,
+    input byte unsigned compressed_manifest[]
+  );
+
+endpackage // Cosim_DpiPkg

esiaccel/cosim/Cosim_Endpoint.sv

@@ -0,0 +1,189 @@
+//===- Cosim_Endpoint.sv - ESI cosim primary RTL module -----*- verilog -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Package: Cosim_DpiPkg
+//
+// Main cosim <--> dpi bridge module.
+//
+//===----------------------------------------------------------------------===//
+
+import Cosim_DpiPkg::*;
+
+module Cosim_Endpoint_ToHost
+#(
+  parameter string ENDPOINT_ID = "",
+  parameter string TO_HOST_TYPE_ID = "",
+  parameter int TO_HOST_SIZE_BITS = -1
+)
+(
+  input  logic clk,
+  input  logic rst,
+
+  input  logic DataInValid,
+  output logic DataInReady,
+  input  logic [TO_HOST_SIZE_BITS-1:0] DataIn
+);
+
+  initial begin
+    int rc;
+    rc = cosim_init();
+    if (rc != 0)
+      $error("Cosim init failed (%d)", rc);
+    rc = cosim_ep_register(ENDPOINT_ID, "", 0,
+                            TO_HOST_TYPE_ID, TO_HOST_SIZE_BYTES);
+    if (rc != 0)
+      $error("Cosim endpoint (%s) register failed: %d", ENDPOINT_ID, rc);
+  end
+
+  /// **********************
+  /// Data in management.
+  ///
+
+  localparam int TO_HOST_SIZE_BYTES = int'((TO_HOST_SIZE_BITS+7)/8);
+  // The number of bits over a byte.
+  localparam int TO_HOST_SIZE_BITS_DIFF = TO_HOST_SIZE_BITS % 8;
+  localparam int TO_HOST_SIZE_BYTES_FLOOR = int'(TO_HOST_SIZE_BITS/8);
+  localparam int TO_HOST_SIZE_BYTES_FLOOR_IN_BITS
+      = TO_HOST_SIZE_BYTES_FLOOR * 8;
+
+  assign DataInReady = 1'b1;
+  byte unsigned DataInBuffer[TO_HOST_SIZE_BYTES-1:0];
+
+  always@(posedge clk) begin
+    if (~rst) begin
+      if (DataInValid) begin
+        int rc;
+        rc = cosim_ep_tryput(ENDPOINT_ID, DataInBuffer, TO_HOST_SIZE_BYTES);
+        if (rc != 0)
+          $error("cosim_ep_tryput(%s, *, %d) = %d Error! (Data lost)",
+            ENDPOINT_ID, TO_HOST_SIZE_BYTES, rc);
+      end
+    end
+  end
+
+  // Assign packed input bit array to unpacked byte array.
+  genvar iIn;
+  generate
+    for (iIn=0; iIn<TO_HOST_SIZE_BYTES_FLOOR; iIn++)
+      assign DataInBuffer[iIn] = DataIn[((iIn+1)*8)-1:iIn*8];
+    if (TO_HOST_SIZE_BITS_DIFF != 0)
+      // If the type is not a multiple of 8, we've got to copy the extra bits.
+      assign DataInBuffer[TO_HOST_SIZE_BYTES - 1]
+                         [TO_HOST_SIZE_BITS_DIFF - 1:0] =
+             DataIn[(TO_HOST_SIZE_BYTES_FLOOR_IN_BITS +
+                     TO_HOST_SIZE_BITS_DIFF - 1) :
+                       TO_HOST_SIZE_BYTES_FLOOR_IN_BITS];
+  endgenerate
+
+  initial begin
+    $display("TO_HOST_SIZE_BITS: %d", TO_HOST_SIZE_BITS);
+    $display("TO_HOST_SIZE_BYTES: %d", TO_HOST_SIZE_BYTES);
+    $display("TO_HOST_SIZE_BITS_DIFF: %d", TO_HOST_SIZE_BITS_DIFF);
+    $display("TO_HOST_SIZE_BYTES_FLOOR: %d", TO_HOST_SIZE_BYTES_FLOOR);
+    $display("TO_HOST_SIZE_BYTES_FLOOR_IN_BITS: %d",
+             TO_HOST_SIZE_BYTES_FLOOR_IN_BITS);
+  end
+
+endmodule
+
+module Cosim_Endpoint_FromHost
+#(
+  parameter string ENDPOINT_ID = "",
+  parameter string FROM_HOST_TYPE_ID = "",
+  parameter int FROM_HOST_SIZE_BITS = -1
+)
+(
+  input  logic clk,
+  input  logic rst,
+
+  output logic DataOutValid,
+  input  logic DataOutReady,
+  output logic [FROM_HOST_SIZE_BITS-1:0] DataOut
+);
+
+  // Handle initialization logic.
+  initial begin
+    int rc;
+    rc = cosim_init();
+    if (rc != 0)
+      $error("Cosim init failed (%d)", rc);
+    rc = cosim_ep_register(ENDPOINT_ID, FROM_HOST_TYPE_ID, FROM_HOST_SIZE_BYTES,
+                            "", 0);
+    if (rc != 0)
+      $error("Cosim endpoint (%s) register failed: %d", ENDPOINT_ID, rc);
+  end
+
+  /// *******************
+  /// Data out management.
+  ///
+
+  localparam int FROM_HOST_SIZE_BYTES = int'((FROM_HOST_SIZE_BITS+7)/8);
+  // The number of bits over a byte.
+  localparam int FROM_HOST_SIZE_BITS_DIFF = FROM_HOST_SIZE_BITS % 8;
+  localparam int FROM_HOST_SIZE_BYTES_FLOOR = int'(FROM_HOST_SIZE_BITS/8);
+  localparam int FROM_HOST_SIZE_BYTES_FLOOR_IN_BITS
+      = FROM_HOST_SIZE_BYTES_FLOOR * 8;
+
+  byte unsigned DataOutBuffer[FROM_HOST_SIZE_BYTES-1:0];
+  always @(posedge clk) begin
+    if (~rst) begin
+      if (DataOutValid && DataOutReady) // A transfer occurred.
+        DataOutValid <= 1'b0;
+
+      if (!DataOutValid || DataOutReady) begin
+        int data_limit;
+        int rc;
+
+        data_limit = FROM_HOST_SIZE_BYTES;
+        rc = cosim_ep_tryget(ENDPOINT_ID, DataOutBuffer, data_limit);
+        if (rc < 0) begin
+          $error("cosim_ep_tryget(%s, *, %d -> %d) returned an error (%d)",
+            ENDPOINT_ID, FROM_HOST_SIZE_BYTES, data_limit, rc);
+        end else if (rc > 0) begin
+          $error("cosim_ep_tryget(%s, *, %d -> %d) had data left over! (%d)",
+            ENDPOINT_ID, FROM_HOST_SIZE_BYTES, data_limit, rc);
+        end else if (rc == 0) begin
+          if (data_limit == FROM_HOST_SIZE_BYTES)
+            DataOutValid <= 1'b1;
+          else if (data_limit == 0)
+            begin end // No message.
+          else
+            $error(
+              "cosim_ep_tryget(%s, *, %d -> %d) did not load entire buffer!",
+              ENDPOINT_ID, FROM_HOST_SIZE_BYTES, data_limit);
+        end
+      end
+    end else begin
+      DataOutValid <= 1'b0;
+    end
+  end
+
+  // Assign packed output bit array from unpacked byte array.
+  genvar iOut;
+  generate
+    for (iOut=0; iOut<FROM_HOST_SIZE_BYTES_FLOOR; iOut++)
+      assign DataOut[((iOut+1)*8)-1:iOut*8] = DataOutBuffer[iOut];
+    if (FROM_HOST_SIZE_BITS_DIFF != 0)
+      // If the type is not a multiple of 8, we've got to copy the extra bits.
+      assign DataOut[(FROM_HOST_SIZE_BYTES_FLOOR_IN_BITS +
+                      FROM_HOST_SIZE_BITS_DIFF - 1) :
+                        FROM_HOST_SIZE_BYTES_FLOOR_IN_BITS]
+             = DataOutBuffer[FROM_HOST_SIZE_BYTES - 1]
+                            [FROM_HOST_SIZE_BITS_DIFF - 1 : 0];
+  endgenerate
+
+  initial begin
+    $display("FROM_HOST_SIZE_BITS: %d", FROM_HOST_SIZE_BITS);
+    $display("FROM_HOST_SIZE_BYTES: %d", FROM_HOST_SIZE_BYTES);
+    $display("FROM_HOST_SIZE_BITS_DIFF: %d", FROM_HOST_SIZE_BITS_DIFF);
+    $display("FROM_HOST_SIZE_BYTES_FLOOR: %d", FROM_HOST_SIZE_BYTES_FLOOR);
+    $display("FROM_HOST_SIZE_BYTES_FLOOR_IN_BITS: %d",
+             FROM_HOST_SIZE_BYTES_FLOOR_IN_BITS);
+  end
+
+endmodule

esiaccel/cosim/Cosim_Manifest.sv

@@ -0,0 +1,32 @@
+//===- Cosim_Manifest.sv - ESI manifest module -------------*- verilog -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// A cosimulated design needs to instantiate this ONCE with the zlib-compressed
+// JSON manifest as the parameter.
+//
+//===----------------------------------------------------------------------===//
+
+import Cosim_DpiPkg::*;
+
+module Cosim_Manifest
+#(
+  parameter int COMPRESSED_MANIFEST_SIZE = 0,
+  parameter int unsigned ESI_VERSION = 0
+)(
+  input logic [COMPRESSED_MANIFEST_SIZE-1:0][7:0] compressed_manifest
+);
+
+  byte unsigned compressed_manifest_bytes[COMPRESSED_MANIFEST_SIZE-1:0];
+  always_comb
+    for (int i=0; i<COMPRESSED_MANIFEST_SIZE; i++)
+      compressed_manifest_bytes[i] = compressed_manifest[i];
+
+  always@(compressed_manifest)
+    cosim_set_manifest(ESI_VERSION, compressed_manifest_bytes);
+
+endmodule

esiaccel/cosim/driver.cpp

@@ -0,0 +1,131 @@
+//===- driver.cpp - ESI Verilator software driver -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// A fairly standard, boilerplate Verilator C++ simulation driver. Assumes the
+// top level exposes just two signals: 'clk' and 'rst'.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef TOP_MODULE
+#define TOP_MODULE ESI_Cosim_Top
+#endif // TOP_MODULE
+
+// Macro black magic to get the header file name and class name from the
+// TOP_MODULE macro. Need to disable formatting for this section, as
+// clang-format messes it up by inserting spaces.
+
+// clang-format off
+#define STRINGIFY_MACRO(x) STR(x)
+#define STR(x) #x
+#define EXPAND(x)x
+#define CONCAT3(n1, n2, n3) STRINGIFY_MACRO(EXPAND(n1)EXPAND(n2)EXPAND(n3))
+#define TOKENPASTE(x, y) x ## y
+#define CLASSNAME(x, y) TOKENPASTE(x, y)
+
+#include CONCAT3(V,TOP_MODULE,.h)
+// clang-format on
+
+#include "verilated_vcd_c.h"
+
+#include "signal.h"
+#include <iostream>
+#include <thread>
+
+vluint64_t timeStamp;
+
+// Stop the simulation gracefully on ctrl-c.
+volatile bool stopSimulation = false;
+void handle_sigint(int) { stopSimulation = true; }
+
+// Called by $time in Verilog.
+double sc_time_stamp() { return timeStamp; }
+
+int main(int argc, char **argv) {
+  // Register graceful exit handler.
+  signal(SIGINT, handle_sigint);
+
+  Verilated::commandArgs(argc, argv);
+
+  // Construct the simulated module's C++ model.
+  auto &dut = *new CLASSNAME(V, TOP_MODULE)();
+  char *waveformFile = getenv("SAVE_WAVE");
+
+  char *periodStr = getenv("DEBUG_PERIOD");
+  unsigned debugPeriod = 0;
+  if (periodStr) {
+    debugPeriod = std::stoi(periodStr);
+    std::cout << "[driver] Setting debug period to " << debugPeriod
+              << std::endl;
+  }
+
+#ifdef TRACE
+  VerilatedVcdC *tfp = nullptr;
+#endif
+
+  if (waveformFile) {
+#ifdef TRACE
+    tfp = new VerilatedVcdC();
+    Verilated::traceEverOn(true);
+    dut.trace(tfp, 99); // Trace 99 levels of hierarchy
+    tfp->open(waveformFile);
+    std::cout << "[driver] Writing trace to " << waveformFile << std::endl;
+#else
+    std::cout
+        << "[driver] Warning: waveform file specified, but not a debug build"
+        << std::endl;
+#endif
+  }
+
+  std::cout << "[driver] Starting simulation" << std::endl;
+
+  // TODO: Add max speed (cycles per second) option for small, interactive
+  // simulations to reduce waveform for debugging. Should this be a command line
+  // option or configurable over the cosim interface?
+
+  // Reset.
+  dut.rst = 1;
+  dut.clk = 0;
+
+  // TODO: Support ESI reset handshake in the future.
+  // Run for a few cycles with reset held.
+  for (timeStamp = 0; timeStamp < 8 && !Verilated::gotFinish(); timeStamp++) {
+    dut.eval();
+    dut.clk = !dut.clk;
+#ifdef TRACE
+    if (tfp)
+      tfp->dump(timeStamp);
+#endif
+  }
+
+  // Take simulation out of reset.
+  dut.rst = 0;
+
+  // Run for the specified number of cycles out of reset.
+  for (; !Verilated::gotFinish() && !stopSimulation; timeStamp++) {
+    dut.eval();
+    dut.clk = !dut.clk;
+
+#ifdef TRACE
+    if (tfp)
+      tfp->dump(timeStamp);
+#endif
+    if (debugPeriod)
+      std::this_thread::sleep_for(std::chrono::milliseconds(debugPeriod));
+  }
+
+  // Tell the simulator that we're going to exit. This flushes the output(s) and
+  // frees whatever memory may have been allocated.
+  dut.final();
+#ifdef TRACE
+  if (tfp)
+    tfp->close();
+#endif
+
+  std::cout << "[driver] Ending simulation at tick #" << timeStamp << std::endl;
+  return 0;
+}

esiaccel/cosim/driver.sv

@@ -0,0 +1,60 @@
+//===- driver.sv - ESI cosim testbench driver -----------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Contains the top module driver for an ESI cosimulation. It simply provides a
+// clock and reset signal. In the future, the reset signal will become a reset
+// handshake.
+//
+//===----------------------------------------------------------------------===//
+
+`timescale 1ns / 100ps
+
+`ifndef TOP_MODULE
+`define TOP_MODULE ESI_Cosim_Top
+`endif
+
+module driver();
+
+  logic clk = 0;
+  logic rst = 0;
+
+  `TOP_MODULE top (
+    .clk(clk),
+    .rst(rst)
+  );
+
+  always begin
+    // A clock period is #4.
+    clk = ~clk;
+    #2;
+  end
+
+  initial begin
+    int cycles;
+
+    $display("[driver] Starting simulation");
+
+    rst = 1;
+    // Hold in reset for 4 cycles.
+    @(posedge clk);
+    @(posedge clk);
+    @(posedge clk);
+    @(posedge clk);
+    rst = 0;
+
+    if ($value$plusargs ("cycles=%d", cycles)) begin
+      int i;
+      for (i = 0; i < cycles; i++) begin
+        @(posedge clk);
+      end
+      $display("[driver] Ending simulation at tick #%0d", $time);
+      $finish();
+    end
+  end
+
+endmodule