esiaccel 0.0.17.dev447__cp310-cp310-win_amd64.whl → 0.1.5.dev406__cp310-cp310-win_amd64.whl

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Files changed (54) hide show
  1. esiaccel/CosimBackend.dll +0 -0
  2. esiaccel/CosimBackend.lib +0 -0
  3. esiaccel/ESICppRuntime.dll +0 -0
  4. esiaccel/ESICppRuntime.lib +0 -0
  5. esiaccel/EsiCosimDpiServer.dll +0 -0
  6. esiaccel/EsiCosimDpiServer.lib +0 -0
  7. esiaccel/MtiPli.dll +0 -0
  8. esiaccel/MtiPli.lib +0 -0
  9. esiaccel/__init__.py +10 -1
  10. esiaccel/abseil_dll.dll +0 -0
  11. esiaccel/accelerator.py +7 -0
  12. esiaccel/cares.dll +0 -0
  13. esiaccel/cmake/esiaccelConfig.cmake +1 -1
  14. esiaccel/cosim/Cosim_DpiPkg.sv +85 -0
  15. esiaccel/cosim/Cosim_Endpoint.sv +218 -0
  16. esiaccel/cosim/Cosim_Manifest.sv +32 -0
  17. esiaccel/cosim/driver.cpp +131 -0
  18. esiaccel/cosim/driver.sv +74 -0
  19. esiaccel/cosim/questa.py +141 -0
  20. esiaccel/cosim/simulator.py +382 -0
  21. esiaccel/cosim/verilator.py +92 -0
  22. esiaccel/esi-cosim.py +104 -0
  23. esiaccel/esiCppAccel.cp310-win_amd64.pyd +0 -0
  24. esiaccel/esiquery.exe +0 -0
  25. esiaccel/include/esi/Accelerator.h +31 -15
  26. esiaccel/include/esi/CLI.h +77 -0
  27. esiaccel/include/esi/Common.h +32 -3
  28. esiaccel/include/esi/Context.h +1 -1
  29. esiaccel/include/esi/Design.h +11 -4
  30. esiaccel/include/esi/Engines.h +124 -0
  31. esiaccel/include/esi/Logging.h +57 -7
  32. esiaccel/include/esi/Manifest.h +0 -2
  33. esiaccel/include/esi/Ports.h +47 -6
  34. esiaccel/include/esi/Services.h +144 -41
  35. esiaccel/include/esi/Types.h +103 -5
  36. esiaccel/include/esi/Values.h +313 -0
  37. esiaccel/include/esi/backends/Cosim.h +85 -0
  38. esiaccel/include/esi/backends/RpcServer.h +55 -0
  39. esiaccel/include/esi/backends/Trace.h +5 -6
  40. esiaccel/libcrypto-3-x64.dll +0 -0
  41. esiaccel/libprotobuf.dll +0 -0
  42. esiaccel/libssl-3-x64.dll +0 -0
  43. esiaccel/re2.dll +0 -0
  44. esiaccel/types.py +132 -26
  45. esiaccel/utils.py +21 -3
  46. esiaccel/zlib1.dll +0 -0
  47. {esiaccel-0.0.17.dev447.dist-info → esiaccel-0.1.5.dev406.dist-info}/METADATA +3 -3
  48. esiaccel-0.1.5.dev406.dist-info/RECORD +54 -0
  49. {esiaccel-0.0.17.dev447.dist-info → esiaccel-0.1.5.dev406.dist-info}/WHEEL +1 -1
  50. esiaccel/bin/esiquery.exe +0 -0
  51. esiaccel-0.0.17.dev447.dist-info/RECORD +0 -28
  52. {esiaccel-0.0.17.dev447.dist-info → esiaccel-0.1.5.dev406.dist-info}/entry_points.txt +0 -0
  53. {esiaccel-0.0.17.dev447.dist-info → esiaccel-0.1.5.dev406.dist-info/licenses}/LICENSE +0 -0
  54. {esiaccel-0.0.17.dev447.dist-info → esiaccel-0.1.5.dev406.dist-info}/top_level.txt +0 -0
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esiaccel/MtiPli.dll ADDED
Binary file
esiaccel/MtiPli.lib ADDED
Binary file
esiaccel/__init__.py CHANGED
@@ -1,7 +1,8 @@
1
1
  # Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
2
2
  # See https://llvm.org/LICENSE.txt for license information.
3
3
  # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
4
-
4
+ import sys
5
+ import os
5
6
  from .accelerator import AcceleratorConnection
6
7
 
7
8
  from .esiCppAccel import (AppID, Type, BundleType, ChannelType, ArrayType,
@@ -11,3 +12,11 @@ __all__ = [
11
12
  "AcceleratorConnection", "AppID", "Type", "BundleType", "ChannelType",
12
13
  "ArrayType", "StructType", "BitsType", "UIntType", "SIntType"
13
14
  ]
15
+
16
+ if sys.platform == "win32":
17
+ """Ensure that ESI libraries are in the dll path on Windows. Necessary to
18
+ call when users build against the esiaccel-provided prebuilt CMake/prebuilt
19
+ libraries, before they are loaded via. python.
20
+ """
21
+ from .utils import get_dll_dir
22
+ os.add_dll_directory(str(get_dll_dir()))
Binary file
esiaccel/accelerator.py CHANGED
@@ -41,6 +41,13 @@ class AcceleratorConnection:
41
41
  def get_service_hostmem(self) -> cpp.HostMem:
42
42
  return self.cpp_accel.get_service_hostmem()
43
43
 
44
+ def get_accelerator(self) -> "Accelerator":
45
+ """
46
+ Return an accelerator that may be owned by this accelerator connection.
47
+ If no accelerator is owned, will throw.
48
+ """
49
+ return Accelerator(self.cpp_accel.get_accelerator())
50
+
44
51
 
45
52
  from .esiCppAccel import HostMemOptions
46
53
 
esiaccel/cares.dll ADDED
Binary file
@@ -10,6 +10,6 @@ if(WIN32)
10
10
  )
11
11
  else()
12
12
  set_target_properties(esiaccel::ESICppRuntime PROPERTIES
13
- IMPORTED_LOCATION "${CMAKE_CURRENT_LIST_DIR}/../lib/ESICppRuntime.so"
13
+ IMPORTED_LOCATION "${CMAKE_CURRENT_LIST_DIR}/.././libESICppRuntime.so"
14
14
  )
15
15
  endif()
@@ -0,0 +1,85 @@
1
+ //===- Cosim_DpiPkg.sv - ESI cosim DPI declarations ---------*- verilog -*-===//
2
+ //
3
+ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
+ // See https://llvm.org/LICENSE.txt for license information.
5
+ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
+ //
7
+ //===----------------------------------------------------------------------===//
8
+ //
9
+ // Package: Cosim_DpiPkg
10
+ //
11
+ // DPI-exposed funcs for cosimserver cosimulation unit-test.
12
+ //
13
+ //===----------------------------------------------------------------------===//
14
+
15
+ package Cosim_DpiPkg;
16
+
17
+ // --------------------- Cosim RPC Server --------------------------------------
18
+
19
+ // Start cosimserver (spawns server for HW-initiated work, listens for
20
+ // connections from new SW-clients).
21
+ import "DPI-C" sv2cCosimserverInit = function int cosim_init();
22
+
23
+ // Teardown cosimserver (disconnects from primary server port, stops connections
24
+ // from active clients).
25
+ import "DPI-C" sv2cCosimserverFinish = function void cosim_finish();
26
+
27
+ // --------------------- Endpoint Management -----------------------------------
28
+
29
+ // Register simulated device endpoints.
30
+ // - return 0 on success, non-zero on failure (duplicate EP registered).
31
+ import "DPI-C" sv2cCosimserverEpRegister =
32
+ function int cosim_ep_register(
33
+ // The endpoint ID.
34
+ input string endpoint_id,
35
+ // The ESI type id which the _RPC client_ is sending us.
36
+ input string from_host_type_id,
37
+ // The send types max size, in bytes.
38
+ input int from_host_type_size,
39
+ // The ESI type id which we are sending to the _RPC client_.
40
+ input string to_host_type_id,
41
+ // The recv types max size, in bytes.
42
+ input int to_host_type_size);
43
+
44
+ // --------------------- Endpoint Accessors ------------------------------------
45
+
46
+ // Attempt to send data to a client.
47
+ // - return 0 on success, negative on failure (unregistered EP).
48
+ import "DPI-C" sv2cCosimserverEpTryPut =
49
+ function int cosim_ep_tryput(
50
+ // The ID of the endpoint to which the data should be sent.
51
+ input string endpoint_id,
52
+ // A data buffer.
53
+ input byte unsigned data[],
54
+ // (Optional) Size of the buffer. If negative, will be dynamically detected.
55
+ input int data_size = -1
56
+ );
57
+
58
+ // Attempt to recieve data from a client.
59
+ // - Returns negative when call failed (e.g. EP not registered).
60
+ // - If no message, return 0 with size_bytes == 0.
61
+ // - Assumes buffer is large enough to contain entire message. Fails if not
62
+ // large enough. (In the future, will add support for getting the message into
63
+ // a fixed-size buffer over multiple calls.)
64
+ import "DPI-C" sv2cCosimserverEpTryGet =
65
+ function int cosim_ep_tryget(
66
+ // The ID of the endpoint from which data should be recieved.
67
+ input string endpoint_id,
68
+ // The buffer in which to put the data. This should be 'output', but the
69
+ // open source simulator Verilator doesn't seem to have a way to do this.
70
+ inout byte unsigned data[],
71
+ // Input: indicates the size of the data[] buffer. If -1, dynamically detect
72
+ // size.
73
+ // Output: the size of the message.
74
+ inout int unsigned data_size
75
+ );
76
+
77
+ // --------------------- Manifest ----------------------------------------------
78
+
79
+ import "DPI-C" sv2cCosimserverSetManifest =
80
+ function void cosim_set_manifest(
81
+ input int signed esi_version,
82
+ input byte unsigned compressed_manifest[]
83
+ );
84
+
85
+ endpackage // Cosim_DpiPkg
@@ -0,0 +1,218 @@
1
+ //===- Cosim_Endpoint.sv - ESI cosim primary RTL module -----*- verilog -*-===//
2
+ //
3
+ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
+ // See https://llvm.org/LICENSE.txt for license information.
5
+ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
+ //
7
+ //===----------------------------------------------------------------------===//
8
+ //
9
+ // Package: Cosim_DpiPkg
10
+ //
11
+ // Main cosim <--> dpi bridge module.
12
+
13
+
14
+ //
15
+ //===----------------------------------------------------------------------===//
16
+
17
+ import Cosim_DpiPkg::*;
18
+
19
+ module Cosim_Endpoint_ToHost
20
+ #(
21
+ parameter string ENDPOINT_ID = "",
22
+ parameter string TO_HOST_TYPE_ID = "",
23
+ parameter int TO_HOST_SIZE_BITS = -1
24
+ )
25
+ (
26
+ input logic clk,
27
+ input logic rst,
28
+
29
+ input logic DataInValid,
30
+ output logic DataInReady,
31
+ input logic [TO_HOST_SIZE_BITS-1:0] DataIn
32
+ );
33
+
34
+ initial begin
35
+ int rc;
36
+ rc = cosim_init();
37
+ if (rc != 0)
38
+ $error("Cosim init failed (%d)", rc);
39
+ rc = cosim_ep_register(ENDPOINT_ID, "", 0,
40
+ TO_HOST_TYPE_ID, TO_HOST_SIZE_BYTES);
41
+ if (rc != 0)
42
+ $error("Cosim endpoint (%s) register failed: %d", ENDPOINT_ID, rc);
43
+ end
44
+
45
+ /// **********************
46
+ /// Data in management.
47
+ ///
48
+
49
+ localparam int TO_HOST_SIZE_BYTES = int'((TO_HOST_SIZE_BITS+7)/8);
50
+ // The number of bits over a byte.
51
+ localparam int TO_HOST_SIZE_BITS_DIFF = TO_HOST_SIZE_BITS % 8;
52
+ localparam int TO_HOST_SIZE_BYTES_FLOOR = int'(TO_HOST_SIZE_BITS/8);
53
+ localparam int TO_HOST_SIZE_BYTES_FLOOR_IN_BITS
54
+ = TO_HOST_SIZE_BYTES_FLOOR * 8;
55
+
56
+ assign DataInReady = 1'b1;
57
+ byte unsigned DataInBuffer[TO_HOST_SIZE_BYTES-1:0];
58
+
59
+ always@(posedge clk) begin
60
+ if (~rst) begin
61
+ if (DataInValid) begin
62
+ int rc;
63
+ rc = cosim_ep_tryput(ENDPOINT_ID, DataInBuffer, TO_HOST_SIZE_BYTES);
64
+ if (rc != 0)
65
+ $error("cosim_ep_tryput(%s, *, %d) = %d Error! (Data lost)",
66
+ ENDPOINT_ID, TO_HOST_SIZE_BYTES, rc);
67
+ end
68
+ end
69
+ end
70
+
71
+ // Assign packed input bit array to unpacked byte array.
72
+ genvar iIn;
73
+ generate
74
+ for (iIn=0; iIn<TO_HOST_SIZE_BYTES_FLOOR; iIn++)
75
+ assign DataInBuffer[iIn] = DataIn[((iIn+1)*8)-1:iIn*8];
76
+ if (TO_HOST_SIZE_BITS_DIFF != 0)
77
+ // If the type is not a multiple of 8, we've got to copy the extra bits.
78
+ assign DataInBuffer[TO_HOST_SIZE_BYTES - 1]
79
+ [TO_HOST_SIZE_BITS_DIFF - 1:0] =
80
+ DataIn[(TO_HOST_SIZE_BYTES_FLOOR_IN_BITS +
81
+ TO_HOST_SIZE_BITS_DIFF - 1) :
82
+ TO_HOST_SIZE_BYTES_FLOOR_IN_BITS];
83
+ endgenerate
84
+
85
+ endmodule
86
+
87
+ module Cosim_Endpoint_FromHost
88
+ #(
89
+ parameter string ENDPOINT_ID = "",
90
+ parameter string FROM_HOST_TYPE_ID = "",
91
+ parameter int FROM_HOST_SIZE_BITS = -1
92
+ )
93
+ (
94
+ input logic clk,
95
+ input logic rst,
96
+
97
+ output logic DataOutValid,
98
+ input logic DataOutReady,
99
+ output logic [FROM_HOST_SIZE_BITS-1:0] DataOut
100
+ );
101
+
102
+ // Handle initialization logic.
103
+ initial begin
104
+ int rc;
105
+ rc = cosim_init();
106
+ if (rc != 0)
107
+ $error("Cosim init failed (%d)", rc);
108
+ rc = cosim_ep_register(ENDPOINT_ID, FROM_HOST_TYPE_ID, FROM_HOST_SIZE_BYTES,
109
+ "", 0);
110
+ if (rc != 0)
111
+ $error("Cosim endpoint (%s) register failed: %d", ENDPOINT_ID, rc);
112
+ end
113
+
114
+ /// ***********************
115
+ /// Useful constants.
116
+
117
+ localparam int FROM_HOST_SIZE_BYTES = int'((FROM_HOST_SIZE_BITS+7)/8);
118
+ // The number of bits over a byte.
119
+ localparam int FROM_HOST_SIZE_BITS_DIFF = FROM_HOST_SIZE_BITS % 8;
120
+ localparam int FROM_HOST_SIZE_BYTES_FLOOR = int'(FROM_HOST_SIZE_BITS/8);
121
+ localparam int FROM_HOST_SIZE_BYTES_FLOOR_IN_BITS
122
+ = FROM_HOST_SIZE_BYTES_FLOOR * 8;
123
+
124
+ // Buffer to hold incoming data directly from the DPI calls.
125
+ byte unsigned DataOutBuffer[FROM_HOST_SIZE_BYTES-1:0];
126
+
127
+ // Pipeline interface signals for buffering DataOut.
128
+ // DataOut_a_valid is asserted when a complete message is available in
129
+ // DataOut_a buffer and waiting to be accepted by the skid buffer.
130
+ logic DataOut_a_valid;
131
+ // Packed representation of the byte buffer to feed the skid input.
132
+ logic [FROM_HOST_SIZE_BITS-1:0] DataOut_a;
133
+ // Ready/valid wires between this module and the skid buffer.
134
+ wire DataOut_a_ready;
135
+ wire DataOut_x_valid;
136
+ wire [FROM_HOST_SIZE_BITS-1:0] DataOut_x;
137
+
138
+ always @(posedge clk) begin
139
+ if (~rst) begin
140
+ // If the skid buffer accepted the input token this cycle, clear the
141
+ // internal valid that indicates we have buffered data.
142
+ if (DataOut_a_valid && DataOut_a_ready)
143
+ DataOut_a_valid <= 1'b0;
144
+
145
+ // Only attempt to fetch data from the host when the skid buffer can
146
+ // accept it (DataOut_a_ready).
147
+ if (!DataOut_a_valid && DataOut_a_ready) begin
148
+ int data_limit;
149
+ int rc;
150
+
151
+ data_limit = FROM_HOST_SIZE_BYTES;
152
+ rc = cosim_ep_tryget(ENDPOINT_ID, DataOutBuffer, data_limit);
153
+ if (rc < 0) begin
154
+ $error("cosim_ep_tryget(%s, *, %d -> %d) returned an error (%d)",
155
+ ENDPOINT_ID, FROM_HOST_SIZE_BYTES, data_limit, rc);
156
+ end else if (rc > 0) begin
157
+ $error("cosim_ep_tryget(%s, *, %d -> %d) had data left over! (%d)",
158
+ ENDPOINT_ID, FROM_HOST_SIZE_BYTES, data_limit, rc);
159
+ end else if (rc == 0) begin
160
+ if (data_limit == FROM_HOST_SIZE_BYTES)
161
+ DataOut_a_valid <= 1'b1;
162
+ else if (data_limit == 0)
163
+ begin end // No message.
164
+ else
165
+ $error(
166
+ "cosim_ep_tryget(%s, *, %d -> %d) did not load entire buffer!",
167
+ ENDPOINT_ID, FROM_HOST_SIZE_BYTES, data_limit);
168
+ end
169
+ end
170
+ end else begin
171
+ DataOut_a_valid <= 1'b0;
172
+ end
173
+ end
174
+
175
+ // Pack the byte array into a single vector that will be handed to the
176
+ // skid buffer as its input payload.
177
+ genvar iOut;
178
+ generate
179
+ for (iOut=0; iOut<FROM_HOST_SIZE_BYTES_FLOOR; iOut++)
180
+ assign DataOut_a[((iOut+1)*8)-1:iOut*8] = DataOutBuffer[iOut];
181
+ if (FROM_HOST_SIZE_BITS_DIFF != 0)
182
+ // If the type is not a multiple of 8, copy the extra bits.
183
+ assign DataOut_a[(FROM_HOST_SIZE_BYTES_FLOOR_IN_BITS +
184
+ FROM_HOST_SIZE_BITS_DIFF - 1) :
185
+ FROM_HOST_SIZE_BYTES_FLOOR_IN_BITS]
186
+ = DataOutBuffer[FROM_HOST_SIZE_BYTES - 1]
187
+ [FROM_HOST_SIZE_BITS_DIFF - 1 : 0];
188
+ endgenerate
189
+
190
+ /// *******************
191
+ /// Data out management.
192
+ ///
193
+ /// It has been observed that some simulators (verilator) does not handle
194
+ /// combinational driving from DPI well (resulting in non-determinism wrt
195
+ /// some of the combinational outputs being dropped/replicated). Questa does
196
+ /// not show this behavior.
197
+ /// A mitigation is to add a skid buffer to decouple the DPI interface
198
+ /// from the output interface.
199
+
200
+ // Instantiate a single-stage pipeline to buffer tokens that arrive from
201
+ // the host and present them to the module's output with proper
202
+ // ready/valid handshaking.
203
+ ESI_PipelineStage #(.WIDTH(FROM_HOST_SIZE_BITS)) out_pipe (
204
+ .clk(clk),
205
+ .rst(rst),
206
+ .a_valid(DataOut_a_valid),
207
+ .a(DataOut_a),
208
+ .a_ready(DataOut_a_ready),
209
+ .x_valid(DataOut_x_valid),
210
+ .x(DataOut_x),
211
+ .x_ready(DataOutReady)
212
+ );
213
+
214
+ // Drive the module's outward-facing signals from the pipeline output.
215
+ assign DataOutValid = DataOut_x_valid;
216
+ assign DataOut = DataOut_x;
217
+
218
+ endmodule
@@ -0,0 +1,32 @@
1
+ //===- Cosim_Manifest.sv - ESI manifest module -------------*- verilog -*-===//
2
+ //
3
+ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
+ // See https://llvm.org/LICENSE.txt for license information.
5
+ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
+ //
7
+ //===----------------------------------------------------------------------===//
8
+ //
9
+ // A cosimulated design needs to instantiate this ONCE with the zlib-compressed
10
+ // JSON manifest as the parameter.
11
+ //
12
+ //===----------------------------------------------------------------------===//
13
+
14
+ import Cosim_DpiPkg::*;
15
+
16
+ module Cosim_Manifest
17
+ #(
18
+ parameter int COMPRESSED_MANIFEST_SIZE = 0,
19
+ parameter int unsigned ESI_VERSION = 0
20
+ )(
21
+ input logic [COMPRESSED_MANIFEST_SIZE-1:0][7:0] compressed_manifest
22
+ );
23
+
24
+ byte unsigned compressed_manifest_bytes[COMPRESSED_MANIFEST_SIZE-1:0];
25
+ always_comb
26
+ for (int i=0; i<COMPRESSED_MANIFEST_SIZE; i++)
27
+ compressed_manifest_bytes[i] = compressed_manifest[i];
28
+
29
+ always@(compressed_manifest)
30
+ cosim_set_manifest(ESI_VERSION, compressed_manifest_bytes);
31
+
32
+ endmodule
@@ -0,0 +1,131 @@
1
+ //===- driver.cpp - ESI Verilator software driver -------------------------===//
2
+ //
3
+ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
+ // See https://llvm.org/LICENSE.txt for license information.
5
+ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
+ //
7
+ //===----------------------------------------------------------------------===//
8
+ //
9
+ // A fairly standard, boilerplate Verilator C++ simulation driver. Assumes the
10
+ // top level exposes just two signals: 'clk' and 'rst'.
11
+ //
12
+ //===----------------------------------------------------------------------===//
13
+
14
+ #ifndef TOP_MODULE
15
+ #define TOP_MODULE ESI_Cosim_Top
16
+ #endif // TOP_MODULE
17
+
18
+ // Macro black magic to get the header file name and class name from the
19
+ // TOP_MODULE macro. Need to disable formatting for this section, as
20
+ // clang-format messes it up by inserting spaces.
21
+
22
+ // clang-format off
23
+ #define STRINGIFY_MACRO(x) STR(x)
24
+ #define STR(x) #x
25
+ #define EXPAND(x)x
26
+ #define CONCAT3(n1, n2, n3) STRINGIFY_MACRO(EXPAND(n1)EXPAND(n2)EXPAND(n3))
27
+ #define TOKENPASTE(x, y) x ## y
28
+ #define CLASSNAME(x, y) TOKENPASTE(x, y)
29
+
30
+ #include CONCAT3(V,TOP_MODULE,.h)
31
+ // clang-format on
32
+
33
+ #include "verilated_fst_c.h"
34
+
35
+ #include "signal.h"
36
+ #include <iostream>
37
+ #include <thread>
38
+
39
+ vluint64_t timeStamp;
40
+
41
+ // Stop the simulation gracefully on ctrl-c.
42
+ volatile bool stopSimulation = false;
43
+ void handle_sigint(int) { stopSimulation = true; }
44
+
45
+ // Called by $time in Verilog.
46
+ double sc_time_stamp() { return timeStamp; }
47
+
48
+ int main(int argc, char **argv) {
49
+ // Register graceful exit handler.
50
+ signal(SIGINT, handle_sigint);
51
+
52
+ Verilated::commandArgs(argc, argv);
53
+
54
+ // Construct the simulated module's C++ model.
55
+ auto &dut = *new CLASSNAME(V, TOP_MODULE)();
56
+ char *waveformFile = getenv("SAVE_WAVE");
57
+
58
+ char *periodStr = getenv("DEBUG_PERIOD");
59
+ unsigned debugPeriod = 0;
60
+ if (periodStr) {
61
+ debugPeriod = std::stoi(periodStr);
62
+ std::cout << "[driver] Setting debug period to " << debugPeriod
63
+ << std::endl;
64
+ }
65
+
66
+ #ifdef TRACE
67
+ VerilatedFstC *tfp = nullptr;
68
+ #endif
69
+
70
+ if (waveformFile) {
71
+ #ifdef TRACE
72
+ tfp = new VerilatedFstC();
73
+ Verilated::traceEverOn(true);
74
+ dut.trace(tfp, 99); // Trace 99 levels of hierarchy
75
+ tfp->open(waveformFile);
76
+ std::cout << "[driver] Writing trace to " << waveformFile << std::endl;
77
+ #else
78
+ std::cout
79
+ << "[driver] Warning: waveform file specified, but not a debug build"
80
+ << std::endl;
81
+ #endif
82
+ }
83
+
84
+ std::cout << "[driver] Starting simulation" << std::endl;
85
+
86
+ // TODO: Add max speed (cycles per second) option for small, interactive
87
+ // simulations to reduce waveform for debugging. Should this be a command line
88
+ // option or configurable over the cosim interface?
89
+
90
+ // Reset.
91
+ dut.rst = 1;
92
+ dut.clk = 0;
93
+
94
+ // TODO: Support ESI reset handshake in the future.
95
+ // Run for a few cycles with reset held.
96
+ for (timeStamp = 0; timeStamp < 8 && !Verilated::gotFinish(); timeStamp++) {
97
+ dut.eval();
98
+ #ifdef TRACE
99
+ if (tfp)
100
+ tfp->dump(timeStamp);
101
+ #endif
102
+ dut.clk = !dut.clk;
103
+ }
104
+
105
+ // Take simulation out of reset.
106
+ dut.rst = 0;
107
+
108
+ // Run for the specified number of cycles out of reset.
109
+ for (; !Verilated::gotFinish() && !stopSimulation; timeStamp++) {
110
+ dut.eval();
111
+ #ifdef TRACE
112
+ if (tfp)
113
+ tfp->dump(timeStamp);
114
+ #endif
115
+ dut.clk = !dut.clk;
116
+
117
+ if (debugPeriod)
118
+ std::this_thread::sleep_for(std::chrono::milliseconds(debugPeriod));
119
+ }
120
+
121
+ // Tell the simulator that we're going to exit. This flushes the output(s) and
122
+ // frees whatever memory may have been allocated.
123
+ dut.final();
124
+ #ifdef TRACE
125
+ if (tfp)
126
+ tfp->close();
127
+ #endif
128
+
129
+ std::cout << "[driver] Ending simulation at tick #" << timeStamp << std::endl;
130
+ return 0;
131
+ }
@@ -0,0 +1,74 @@
1
+ //===- driver.sv - ESI cosim testbench driver -----------------------------===//
2
+ //
3
+ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
+ // See https://llvm.org/LICENSE.txt for license information.
5
+ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
+ //
7
+ //===----------------------------------------------------------------------===//
8
+ //
9
+ // Contains the top module driver for an ESI cosimulation. It simply provides a
10
+ // clock and reset signal. In the future, the reset signal will become a reset
11
+ // handshake.
12
+ //
13
+ //===----------------------------------------------------------------------===//
14
+
15
+ `timescale 1ns / 100ps
16
+
17
+ `ifndef TOP_MODULE
18
+ `define TOP_MODULE ESI_Cosim_Top
19
+ `endif
20
+
21
+ // Allow reading environment variables to control waveform dumping.
22
+ import "DPI-C" function string getenv(input string env_name);
23
+
24
+ module driver();
25
+
26
+ // If the SAVE_WAVE environment variable is set, dump a VCD waveform to that
27
+ // filename.
28
+ initial begin
29
+ string save_wave = getenv("SAVE_WAVE");
30
+ if (save_wave != "") begin
31
+ $display("[driver] Saving waveform to %s", save_wave);
32
+ $dumpfile(save_wave);
33
+ $dumpvars(0, driver);
34
+ end
35
+ end
36
+
37
+ logic clk = 0;
38
+ logic rst = 0;
39
+
40
+ `TOP_MODULE top (
41
+ .clk(clk),
42
+ .rst(rst)
43
+ );
44
+
45
+ always begin
46
+ // A clock period is #4.
47
+ clk = ~clk;
48
+ #2;
49
+ end
50
+
51
+ initial begin
52
+ int cycles;
53
+
54
+ $display("[driver] Starting simulation");
55
+
56
+ rst = 1;
57
+ // Hold in reset for 4 cycles.
58
+ @(posedge clk);
59
+ @(posedge clk);
60
+ @(posedge clk);
61
+ @(posedge clk);
62
+ rst = 0;
63
+
64
+ if ($value$plusargs ("cycles=%d", cycles)) begin
65
+ int i;
66
+ for (i = 0; i < cycles; i++) begin
67
+ @(posedge clk);
68
+ end
69
+ $display("[driver] Ending simulation at tick #%0d", $time);
70
+ $finish();
71
+ end
72
+ end
73
+
74
+ endmodule