digsim-logic-simulator 0.8.0__py3-none-any.whl → 0.10.0__py3-none-any.whl

digsim/app/model/_model_shortcuts.py

@@ -77,10 +77,9 @@ class ModelShortcuts:
             shortcuts_dict[key] = component.name()
         return shortcuts_dict
 
-    def from_dict(self, model_dict):
+    def from_dict(self, shortcuts_dict):
         """Generate shortcuts from dict"""
         self.clear()
-        shortcuts_dict = model_dict.get("shortcuts")
         if shortcuts_dict is not None:
             for key, component_name in shortcuts_dict.items():
                 component = self._app_model.objects.circuit.get_component(component_name)

digsim/circuit/components/_yosys_component.py

@@ -10,8 +10,9 @@ import json
 
 import digsim.circuit.components._yosys_atoms
 from digsim.synth import Synthesis
-from digsim.utils import YosysNetlist
+from digsim.utils import YosysCell, YosysModule, YosysNetlist
 
+from ._static_level import GND, VDD
 from .atoms import Component, DigsimException, MultiComponent, PortMultiBitWire
 
 
@@ -29,6 +30,7 @@ class YosysComponent(MultiComponent):
         self._gates_comp = None
         self._net_comp = None
         self._netlist_module = None
+        self._netlist_nets = None
         self._setup_base()
 
         if nets:
@@ -47,13 +49,15 @@ class YosysComponent(MultiComponent):
         modules = netlist_object.get_modules()
         module_name = list(modules.keys())[0]
         self._netlist_module = netlist_object.get_modules()[module_name]
+        self._netlist_nets = self._netlist_module.get_nets()
+
         # Set Name
         self.set_name(module_name)
         self.set_display_name(module_name)
         # Add External Ports
-        for portname, port_dict in self._netlist_module.get_external_interface().items():
+        for portname, port_dict in self._netlist_module.ports.items():
             external_port = PortMultiBitWire(
-                self, portname, width=len(port_dict["nets"]), output=not port_dict["output"]
+                self, portname, width=len(port_dict.bits), output=port_dict.is_output
             )
             self.add_port(external_port)
         # Create component
@@ -64,18 +68,10 @@ class YosysComponent(MultiComponent):
         modules = netlist_object.get_modules()
         module_name = list(modules.keys())[0]
         reload_module = netlist_object.get_modules()[module_name]
+        reload_nets = reload_module.get_nets()
 
-        # Verify that new external interface is the same as the current
-        current_ext_if = self._netlist_module.get_external_interface()
-        new_ext_if = reload_module.get_external_interface()
-
-        if current_ext_if.keys() != new_ext_if.keys():
+        if not self._netlist_module.is_same_interface(reload_module):
             raise YosysComponentException("Yosys component interface differs")
-        for key, _ in current_ext_if.items():
-            if len(current_ext_if[key]["nets"]) != len(new_ext_if[key]["nets"]):
-                raise YosysComponentException("Yosys component interface differs")
-            if current_ext_if[key]["output"] != new_ext_if[key]["output"]:
-                raise YosysComponentException("Yosys component interface differs")
 
         # Disconnect ports
         self._disconnect_external_ports()
@@ -86,63 +82,79 @@ class YosysComponent(MultiComponent):
             self._net_comp.delete_all_ports()
         # Setup netlist
         self._netlist_module = reload_module
+        self._netlist_nets = reload_nets
         # Create component
         self._create_component()
 
     def _create_cells(self):
         """Create cells in component"""
         components_dict = {}
-        for cellname, cell in self._netlist_module.get_cells().items():
+        for cellname, cell in self._netlist_module.cells.items():
+            if cell.type == "$scopeinfo":
+                continue
             component_class = getattr(
-                digsim.circuit.components._yosys_atoms, cell.get_friendly_type()
+                digsim.circuit.components._yosys_atoms, cell.component_type()
             )
-            component = component_class(self._circuit, name=cell.get_friendly_name())
+            component = component_class(self._circuit, name=cell.component_name(cellname))
             self._gates_comp.add(component)
             components_dict[cellname] = component
+
+        vdd = VDD(self._circuit)
+        self._gates_comp.add(vdd)
+        components_dict["VDD"] = vdd
+        gnd = GND(self._circuit)
+        self._gates_comp.add(gnd)
+        components_dict["GND"] = gnd
+
         return components_dict
 
-    def _connect_cell_port(self, components_dict, src_cell, source_port):
-        """Connect cell ports"""
-        src_comp = components_dict[src_cell.name()]
-        src_comp_port = src_comp.port(source_port.name())
-        net = source_port.get_nets()[0]
-        for sink_port in source_port.get_sinks():
-            if sink_port.get_parent().get_type() == "module":
+    def _connect_sinks(self, components_dict, src_comp_port, sinks):
+        """Connect a source port to multiple sinks"""
+        for sink_port in sinks:
+            if isinstance(sink_port.parent, YosysModule):
                 # Connect cell output to module top
-                for dst_bit, sink_net in enumerate(sink_port.get_nets()):
-                    if net == sink_net:
-                        dst_port = self.port(sink_port.name()).get_bit(dst_bit)
-                        src_comp_port.wire = dst_port
+                dst_port = self.port(sink_port.name).get_bit(sink_port.bit_index)
+                src_comp_port.wire = dst_port
             else:
                 # Connect cell output to cell input
-                dst_comp = components_dict[sink_port.get_parent().name()]
-                src_comp_port.wire = dst_comp.port(sink_port.name())
+                dst_comp = components_dict[sink_port.parent_name]
+                src_comp_port.wire = dst_comp.port(sink_port.name)
 
     def _connect_cells(self, components_dict):
         """Connect all cells"""
-        for _, src_cell in self._netlist_module.get_cells().items():
-            for source_port in src_cell.get_source_ports():
-                self._connect_cell_port(components_dict, src_cell, source_port)
+        for net, source in self._netlist_nets.source.items():
+            if isinstance(source.parent, YosysModule):
+                # Only connect cells here
+                continue
+            if isinstance(source.parent, YosysCell):
+                src_comp = components_dict[source.parent_name]
+                self._connect_sinks(
+                    components_dict, src_comp.port(source.name), self._netlist_nets.sinks[net]
+                )
+
+        gnd_sinks = self._netlist_nets.sinks.get("0", [])
+        self._connect_sinks(components_dict, components_dict["GND"].port("O"), gnd_sinks)
+        vdd_sinks = self._netlist_nets.sinks.get("1", [])
+        self._connect_sinks(components_dict, components_dict["VDD"].port("O"), vdd_sinks)
 
     def _connect_external_input_port(self, components_dict, portname, port_dict):
-        """Conenct external input port"""
-        for bit_idx, net in enumerate(port_dict["nets"]):
-            for sink_port in self._netlist_module.get_sinks(net):
-                if sink_port.get_parent().get_type() == "module":
+        """Connect external input port"""
+        for bit_idx, net in enumerate(port_dict.bits):
+            for sink_port in self._netlist_nets.sinks[net]:
+                if isinstance(sink_port.parent, YosysModule):
                     # Connect module input to module output
-                    for dst_bit, sink_net in enumerate(sink_port.get_nets()):
-                        if net == sink_net:
-                            dst_port = self.port(sink_port.name()).get_bit(dst_bit)
-                            self.port(portname).get_bit(bit_idx).wire = dst_port
+                    dst_port = self.port(sink_port.name).get_bit(sink_port.bit_index)
+                    self.port(portname).get_bit(bit_idx).wire = dst_port
                 else:
                     # Connect module input to cell input
-                    dst_comp = components_dict[sink_port.get_parent().name()]
-                    self.port(portname).get_bit(bit_idx).wire = dst_comp.port(sink_port.name())
+                    self._connect_sinks(
+                        components_dict, self.port(portname).get_bit(bit_idx), [sink_port]
+                    )
 
     def _connect_external_input(self, components_dict):
         """Connect all external input ports"""
-        for portname, port_dict in self._netlist_module.get_external_interface().items():
-            if not port_dict["output"]:
+        for portname, port_dict in self._netlist_module.ports.items():
+            if port_dict.direction == "output":
                 continue
             self._connect_external_input_port(components_dict, portname, port_dict)
 
@@ -176,8 +188,7 @@ class YosysComponent(MultiComponent):
         else:
             raise YosysComponentException(f"Unknown file extension '{self._path}'")
 
-        yosys_netlist = YosysNetlist()
-        yosys_netlist.from_dict(netlist_dict)
+        yosys_netlist = YosysNetlist(**netlist_dict)
         modules = yosys_netlist.get_modules()
 
         if len(modules) > 1:

digsim/circuit/components/ic/74162.json

@@ -1,6 +1,6 @@
 
 {
-  "creator": "Yosys 0.53+101 (git sha1 2a25d9241, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)",
+  "creator": "Yosys 0.57 (git sha1 3aca86049, ccache clang++ 18.1.3 -O3 -flto -flto)",
   "modules": {
     "ttl_74162": {
       "attributes": {
@@ -821,7 +821,7 @@
         }
       },
       "netnames": {
-        "$abc$895$auto$opt_dff.cc:194:make_patterns_logic$32": {
+        "$abc$895$auto$opt_dff.cc:247:make_patterns_logic$32": {
           "hide_name": 1,
           "bits": [ 18 ],
           "attributes": {
@@ -1111,3 +1111,4 @@
     }
   }
 }
+

digsim/circuit/components/ic/7448.json

@@ -1,6 +1,6 @@
 
 {
-  "creator": "Yosys 0.53+101 (git sha1 2a25d9241, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)",
+  "creator": "Yosys 0.57 (git sha1 3aca86049, ccache clang++ 18.1.3 -O3 -flto -flto)",
   "modules": {
     "ic7448": {
       "attributes": {
@@ -76,8 +76,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 15 ]
           }
         },
@@ -114,8 +114,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 3 ],
-            "B": [ 4 ],
+            "A": [ 4 ],
+            "B": [ 3 ],
             "Y": [ 17 ]
           }
         },
@@ -170,8 +170,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 19 ]
           }
         },
@@ -376,8 +376,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 28 ]
           }
         },
@@ -526,8 +526,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 34 ]
           }
         },
@@ -600,8 +600,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 37 ]
           }
         },
@@ -895,3 +895,4 @@
     }
   }
 }
+

digsim/utils/__init__.py

@@ -3,4 +3,4 @@
 
 """All classes within digsim.utils namespace"""
 
-from ._yosys_netlist import YosysNetlist  # noqa: F401
+from ._yosys_netlist import YosysCell, YosysModule, YosysNetlist  # noqa: F401

digsim/utils/_yosys_netlist.py

@@ -5,268 +5,124 @@
 Module with classes to parse a yosys netlist
 """
 
+from __future__ import annotations
 
-class _NetlistPort:
-    """A class describing a port within a netlist"""
+from typing import Any, Optional, Union
 
-    def __init__(self, parent, name, net=None, is_source=None):
-        self._parent = parent
-        self._name = name
-        self._is_source = is_source
-        self._sinks = []
-        if net is None:
-            self._nets = []
-        else:
-            self._nets = [net]
-
-    def name(self):
-        """Return port name"""
-        return self._name
-
-    def get_parent(self):
-        """Return port parent"""
-        return self._parent
-
-    def is_source(self):
-        """Return true if port is a source (false for sink)"""
-        return self._is_source
-
-    def add_sinks(self, sinks):
-        """Add sinks to source port"""
-        self._sinks.extend(sinks)
-
-    def get_sinks(self):
-        """Get source port sinks"""
-        return self._sinks
-
-    def get_nets(self):
-        """Get port nets"""
-        return self._nets
-
-    def from_module_dict(self, port_dict, global_nets):
-        """Create xternal port from module dict"""
-        self._is_source = port_dict["direction"] == "input"
-        for net in port_dict["bits"]:
-            if net not in global_nets:
-                global_nets.append(net)
-            self._nets.append(net)
+from pydantic import Field
+from pydantic.dataclasses import dataclass
 
 
-class _NetlistBlock:
-    """Common base class for modules and cells"""
+@dataclass
+class NetPort:
+    parent: Union[YosysModule, YosysCell]
+    parent_name: str
+    name: str
+    bit_index: Optional[int] = None
 
-    def __init__(self, name, block_type=None):
-        self._name = name
-        self._ports = {}
-        self._nets = []
-        self._block_type = block_type
-        self._net_to_source_port = {}
-        self._net_to_sink_ports = {}
 
-    def name(self):
-        """Return name of block (cell or module)"""
-        return self._name
+@dataclass
+class Nets:
+    source: dict[int, NetPort] = Field(default_factory=dict)
+    sinks: dict[int, list[NetPort]] = Field(default_factory=dict)
 
-    def get_type(self):
-        """Get type"""
-        return self._block_type
 
-    def set_type(self, block_type):
-        """Set type"""
-        self._block_type = block_type
+@dataclass
+class YosysPort:
+    direction: str
+    bits: list[Union[int, str]]
 
-    def add_port(self, name, port):
-        """Add port to block (cell or module)"""
-        self._ports[name] = port
-        nets = port.get_nets()
-        if port.is_source():
-            for net in nets:
-                self._net_to_source_port[net] = port
-        else:
-            for net in nets:
-                if net not in self._net_to_sink_ports:
-                    self._net_to_sink_ports[net] = []
-                if port not in self._net_to_sink_ports[net]:
-                    self._net_to_sink_ports[net].append(port)
-
-    def get_nets(self):
-        """Get nets of block (cell or module)"""
-        return self._nets
-
-    def get_source_ports(self):
-        """Get source ports of block (cell or module)"""
-        ports = []
-        for _, port in self._net_to_source_port.items():
-            ports.append(port)
-        return ports
-
-    def get_source_port(self, net):
-        """Get source port of block (cell or module)"""
-        return self._net_to_source_port.get(net)
+    @property
+    def is_output(self):
+        return self.direction == "output"
 
-    def get_sink_ports(self, net):
-        """Get sink port of block (cell or module)"""
-        return self._net_to_sink_ports.get(net, [])
-
-
-class _NetlistCell(_NetlistBlock):
-    """A class holding a cell in a yosys netlist"""
+    def is_same(self, compare_port):
+        return (compare_port.direction == self.direction) and (
+            len(compare_port.bits) == len(self.bits)
+        )
 
-    def __init__(self, name):
-        super().__init__(name)
 
-    def get_friendly_name(self):
+@dataclass
+class YosysCell:
+    type: str
+    port_directions: dict[str, str] = Field(default_factory=dict)
+    connections: dict[str, list[Union[str, int]]] = Field(default_factory=dict)
+    hide_name: int = 0
+    parameters: dict[str, Any] = Field(default_factory=dict)
+    attributes: dict[str, Any] = Field(default_factory=dict)
+
+    def get_nets(self, name, nets):
+        for port_name, net_list in self.connections.items():
+            net = net_list[0]
+            port = NetPort(parent=self, parent_name=name, name=port_name)
+            if self.port_directions[port_name] == "input":
+                if net not in nets.sinks:
+                    nets.sinks[net] = []
+                nets.sinks[net].append(port)
+            else:
+                nets.source[net] = port
+
+    def component_name(self, name):
         """Return a friendly name for a netlist cell"""
-        return f"{self.name().split('$')[-1]}_{self.get_friendly_type()}"
+        return f"{name.split('$')[-1]}_{self.component_type()}"
 
-    def get_friendly_type(self):
+    def component_type(self):
         """Return a friendly type for a netlist cell"""
-        return f"_{self.get_type()[2:-1]}_"
-
-    def from_dict(self, cell_dict, global_nets):
-        """Create netlist cell from dict"""
-        self.set_type(cell_dict["type"])
-        for port_name, port_dir in cell_dict["port_directions"].items():
-            output = port_dir == "output"
-            port_net = cell_dict["connections"][port_name]
-            self._nets.extend(port_net)
-            for net in port_net:
-                if net not in global_nets:
-                    global_nets.append(net)
-                port = _NetlistPort(self, port_name, net, output)
-                self.add_port(port_name, port)
-
-
-class _NestlistModule(_NetlistBlock):
-    """A class holding a module in a yosys netlist"""
-
-    def __init__(self, name):
-        super().__init__(name, "module")
-        self._cells = {}
-        self._module_nets = []
-        self._ext_if = {}
-
-        static_cell = _NetlistCell("StaticLevel")
-        static_cell.from_dict(
-            {
-                "type": "$_StaticLevel_",
-                "port_directions": {"L": "output", "H": "output"},
-                "connections": {"L": ["0"], "H": ["1"]},
-            },
-            self._nets,
-        )
-        self._cells["StaticLevel"] = static_cell
-
-    def from_dict(self, module_dict):
-        """Create module from dict"""
-        for ext_port_name, port_dict in module_dict["ports"].items():
-            ext_port = _NetlistPort(self, ext_port_name)
-            ext_port.from_module_dict(port_dict, self._nets)
-            nets = ext_port.get_nets()
-            ext_port_dict = {"output": ext_port.is_source(), "nets": nets}
-            self._ext_if[ext_port_name] = ext_port_dict
-            self.add_port(ext_port_name, ext_port)
-
-        for cell_name, cell_dict in module_dict["cells"].items():
-            cell = _NetlistCell(cell_name)
-            cell.from_dict(cell_dict, self._nets)
-            if cell.get_type() == "$scopeinfo":
-                continue
-            self._cells[cell_name] = cell
-
-    def get_cells(self):
-        """Get cells dict"""
-        return self._cells
-
-    def get_external_interface(self):
-        """Get external interface dict"""
-        return self._ext_if
-
-    def get_source(self, net):
-        """Get source port for net"""
-        module_port = self.get_source_port(net)
-        if module_port is not None:
-            return module_port
-        for _, cell in self._cells.items():
-            cell_port = cell.get_source_port(net)
-            if cell_port is not None:
-                return cell_port
-        return None
-
-    def get_sinks(self, net):
-        """Get module sinks (input ports)"""
-        sink_ports = self.get_sink_ports(net)
-        for _, cell in self._cells.items():
-            cell_sink_ports = cell.get_sink_ports(net)
-            for port in cell_sink_ports:
-                if port not in sink_ports:
-                    sink_ports.append(port)
-        return sink_ports
-
-    def connect(self):
-        """Connect all nets within module"""
-        _source_port_dict = {}
-        _sink_ports_dict = {}
-        _cells_dict = {}
-
-        # Build net to cell dict
-        for _, cell in self._cells.items():
-            for cell_net in cell.get_nets():
-                if cell_net not in _cells_dict:
-                    _cells_dict[cell_net] = []
-                _cells_dict[cell_net].append(cell)
+        return f"_{self.type[2:-1]}_"
+
+
+@dataclass
+class YosysNetName:
+    bits: list[int]
+    attributes: dict[str, Any] = Field(default_factory=dict)
+    hide_name: int = 0
+
+
+@dataclass
+class YosysModule:
+    attributes: dict[str, Any] = Field(default_factory=dict)
+    parameter_default_values: dict[str, Any] = Field(default_factory=dict)
+    ports: dict[str, YosysPort] = Field(default_factory=dict)
+    cells: dict[str, YosysCell] = Field(default_factory=dict)
+    netnames: dict[str, YosysNetName] = Field(default_factory=dict)
+
+    def is_same_interface(self, netlist):
+        is_same = True
+        if len(netlist.ports) == len(self.ports):
+            for netlist_port_name, netlist_port in netlist.ports.items():
+                module_port = self.ports.get(netlist_port_name)
+                if module_port is None or not module_port.is_same(netlist_port):
+                    # Port does not exist or has a different bitwidth
+                    is_same = False
+                    break
+        else:
+            # The number of ports does not match
+            is_same = False
+        return is_same
 
-        # Build net to ports dict
-        for net in self._nets:
-            # Module
-            port = self.get_source_port(net)
-            if port is not None:
-                _source_port_dict[net] = port
-            sink_ports = self.get_sink_ports(net)
-            # Cells
-            for cell in _cells_dict.get(net, []):
-                port = cell.get_source_port(net)
-                if port is not None:
-                    _source_port_dict[net] = port
-                cell_sink_ports = cell.get_sink_ports(net)
-                sink_ports.extend(cell_sink_ports)
-            _sink_ports_dict[net] = sink_ports
+    def get_nets(self):
+        nets = Nets()
 
-        # Connect
-        for net in self._nets:
-            source_port = _source_port_dict[net]
-            sink_ports = _sink_ports_dict[net]
-            source_port.add_sinks(sink_ports)
+        for port_name, port_item in self.ports.items():
+            for bit_index, net in enumerate(port_item.bits):
+                port = NetPort(parent=self, parent_name="top", name=port_name, bit_index=bit_index)
+                if port_item.is_output:
+                    if net not in nets.sinks:
+                        nets.sinks[net] = []
+                    nets.sinks[net].append(port)
+                else:
+                    nets.source[net] = port
 
-        # Connect module nets
-        for module_net in self._module_nets:
-            nets = module_net.get_nets()
-            ports = []
-            for net in nets:
-                port = _source_port_dict[net]
-                ports.append(port)
-            module_net.set_ports(ports)
+        for cell_name, cell in self.cells.items():
+            cell.get_nets(cell_name, nets)
 
-    def get_module_nets(self):
-        """Get the nets for this module"""
-        return self._module_nets
+        return nets
 
 
+@dataclass
 class YosysNetlist:
-    """A class holding the content of a yosys netlist"""
-
-    def __init__(self):
-        self._modules = {}
+    creator: Optional[str] = None
+    modules: dict[str, YosysModule] = Field(default_factory=dict)
 
     def get_modules(self):
-        """Get modules dict"""
-        return self._modules
-
-    def from_dict(self, netlist_dict):
-        """Parse netlist from dict"""
-        for module_name, module_dict in netlist_dict["modules"].items():
-            module = _NestlistModule(module_name)
-            module.from_dict(module_dict)
-            self._modules[module_name] = module
-        for _, module in self._modules.items():
-            module.connect()
+        return self.modules

{digsim_logic_simulator-0.8.0.dist-info → digsim_logic_simulator-0.10.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: digsim-logic-simulator
-Version: 0.8.0
+Version: 0.10.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>
@@ -22,7 +22,7 @@ Requires-Dist: pyside6==6.9.1
 Requires-Dist: pexpect==4.9.0
 Requires-Dist: pydantic==2.11.7
 Requires-Dist: qtawesome==1.4.0
-Requires-Dist: yowasp-yosys==0.55.0.0.post944
+Requires-Dist: yowasp-yosys==0.57.0.0.post986
 Dynamic: license-file
 
 # DigSim - Interactive Digital Logic Simulator

{digsim_logic_simulator-0.8.0.dist-info → digsim_logic_simulator-0.10.0.dist-info}/RECORD

@@ -54,7 +54,7 @@ digsim/app/model/_model_components.py,sha256=Q2iztl7MlWv_7vaa7me-dp-gOx6-7Tg3LZm
 digsim/app/model/_model_new_wire.py,sha256=5HnF5-gtKtB1Tp6ZIF7QuNo5zEHmsUpnBEmj6ZllLiA,1810
 digsim/app/model/_model_objects.py,sha256=lqOjNIygIHT6Dq_PPa-D0B5elC49dB0KshF0ATzJZ0s,5217
 digsim/app/model/_model_settings.py,sha256=FewI3hm1iwbjPwdN3IeixuINPtamDORrTh1ANGRNwX8,1035
-digsim/app/model/_model_shortcuts.py,sha256=TT4osN7-dMEgKXWHW9cJ0XILIIkUfRqBBfx6rvYT2JI,2488
+digsim/app/model/_model_shortcuts.py,sha256=xrUgs2Y18mSVun3sxzVscYTZ6n5DJTTZOnFhs4Jt_0M,2439
 digsim/app/settings/__init__.py,sha256=0tkoBSYeJFFiUI8c_FqvqqyM4-_SU9Xq7mXCwiew5Oo,308
 digsim/app/settings/_component_settings.py,sha256=88D9OuEcFIlaqZozomWHSYrl7opz4jZW2e8xGuUyTpg,16287
 digsim/app/settings/_gui_settings.py,sha256=sDi2POUsHvS7_4SO5qsTu_nN48HsTN4UfGPzdmECs9w,2764
@@ -83,23 +83,23 @@ digsim/circuit/components/_seven_segment.py,sha256=UxxjGLuIirVB2Px09XlL8_zjgE7F8
 digsim/circuit/components/_static_level.py,sha256=2Assm1cmAfryVZ3KTQ1uGY8Q6eRrBipdwLITewXfIHg,677
 digsim/circuit/components/_static_value.py,sha256=vfRPS_F9mKOXpHJxzs0JQKXqcj0o6d-090zbyZaECA4,1236
 digsim/circuit/components/_yosys_atoms.py,sha256=NeH8XjjpoACHBfQRqR5RJxWorZhSjGk0t73cJOviSZw,37599
-digsim/circuit/components/_yosys_component.py,sha256=XDNSAfM6Qvhe6G0-M1uiY2NQ-A6oPSQX4kcB_ccvSWg,8810
+digsim/circuit/components/_yosys_component.py,sha256=LkYneNSvzQMn61RzlHk3aSkl9tF6JjibknfwmLeWCFk,8792
 digsim/circuit/components/atoms/__init__.py,sha256=NU45pfJcSrdwZA-SVQeORlaznl_0BciY4VN3vVSnD8o,498
 digsim/circuit/components/atoms/_component.py,sha256=DpMS1yOWWgk11Y9ae0PfuOJdlJsrzgrzuYrgsN62dbQ,8815
 digsim/circuit/components/atoms/_digsim_exception.py,sha256=Y5mBve15zZbduqNNAyf7WzqDk4NtvUL_g2vYy5kBQ3U,173
 digsim/circuit/components/atoms/_port.py,sha256=yT1TqmKPVlw8G_0r_6dErcqIkXCqB8z0pE5oL6Bnxzo,12596
-digsim/circuit/components/ic/74162.json,sha256=XY-qHubOw3P7xeuV1ZZDTD-XcDBwAovTZ1Ic-rTnYqY,26694
-digsim/circuit/components/ic/7448.json,sha256=WnVrq6nr0L_ywg2cJlrqg3gpv0l1Pha5yfNza-lE9S4,21186
+digsim/circuit/components/ic/74162.json,sha256=RAeSva6TVuwfKHsvU9HC-ZVfRVrCkIsQUz_jcANT_fE,26693
+digsim/circuit/components/ic/7448.json,sha256=hKMXhPqW-JBTF6rdz9u5HC_hY9cBRpJtMkLP7uOQXIo,21185
 digsim/storage_model/__init__.py,sha256=lubmO9_BCUtEahyW1yE7f3aGHngEevGIwf_0LeOB7Y8,289
 digsim/storage_model/_app.py,sha256=Aer9s_mUBKSydsyeWYvVPHX2XF5ZGPuXq8z4PoXu8lA,1353
 digsim/storage_model/_circuit.py,sha256=NnaHLwqb9gAhqAxeZ1RkHHvoS_YJwixlz0xs-zmIrQU,3596
 digsim/synth/__init__.py,sha256=jhBHLOHf-vNa94Zg5q5dGcf0fgQTModfjUKtmUSffiw,180
 digsim/synth/__main__.py,sha256=wZWAzWsisoxA7hfqkKtu3H066uWyFajgPro2MEGlKbs,2173
 digsim/synth/_synthesis.py,sha256=ug9vSeTyZrvRCboNLL7dDIFVpGqH_ibr5fhOZJHpqUs,4271
-digsim/utils/__init__.py,sha256=Az_zmbORYMzmptuA2_xfn5jDxbCPRSMlVuntr0sYexU,167
-digsim/utils/_yosys_netlist.py,sha256=ElnqPUsOO5zjTuf6UFSyEH3UabNlhxiLpwgACcX74rk,8635
-digsim_logic_simulator-0.8.0.dist-info/licenses/LICENSE.md,sha256=FrvohZfyfpH4xrvKdXiQ5hD7dUB7w4DcsRA3p-pOmLw,1693
-digsim_logic_simulator-0.8.0.dist-info/METADATA,sha256=CGio3nKIsVeQLBUhfl3N6LOZjxH9Z0VnB2mrgl7GC8w,4557
-digsim_logic_simulator-0.8.0.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
-digsim_logic_simulator-0.8.0.dist-info/top_level.txt,sha256=qpCMzQKADZHVqZIoQgFrv3qJ3u7PPU73gTCXQglqLa8,7
-digsim_logic_simulator-0.8.0.dist-info/RECORD,,
+digsim/utils/__init__.py,sha256=MT9TNcpa7fNAqtBsmCcceKMrUSU_v9xeJ6Nox_TL7Lo,191
+digsim/utils/_yosys_netlist.py,sha256=Lcuo9seKcDu4O-NdBpJUpExvTT7Rx1STCBtF0xT8Nkc,3843
+digsim_logic_simulator-0.10.0.dist-info/licenses/LICENSE.md,sha256=FrvohZfyfpH4xrvKdXiQ5hD7dUB7w4DcsRA3p-pOmLw,1693
+digsim_logic_simulator-0.10.0.dist-info/METADATA,sha256=Sjx2LJyb7CSKNkJVmT17qGyOmKOCtaFmeyKBdi6ip9U,4558
+digsim_logic_simulator-0.10.0.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
+digsim_logic_simulator-0.10.0.dist-info/top_level.txt,sha256=qpCMzQKADZHVqZIoQgFrv3qJ3u7PPU73gTCXQglqLa8,7
+digsim_logic_simulator-0.10.0.dist-info/RECORD,,