digsim-logic-simulator 0.7.0__py3-none-any.whl → 0.9.0__py3-none-any.whl

digsim/utils/_yosys_netlist.py

@@ -5,266 +5,119 @@
 Module with classes to parse a yosys netlist
 """
 
+from __future__ import annotations
 
-class _NetlistPort:
-    """A class describing a port within a netlist"""
+from typing import Any, Optional, Union
 
-    def __init__(self, parent, name, net=None, is_source=None):
-        self._parent = parent
-        self._name = name
-        self._is_source = is_source
-        self._sinks = []
-        if net is None:
-            self._nets = []
-        else:
-            self._nets = [net]
+from pydantic import Field
+from pydantic.dataclasses import dataclass
 
-    def name(self):
-        """Return port name"""
-        return self._name
 
-    def get_parent(self):
-        """Return port parent"""
-        return self._parent
+@dataclass
+class NetPort:
+    parent: Union[YosysModule, YosysCell]
+    parent_name: str
+    name: str
+    bit_index: Optional[int] = None
 
-    def is_source(self):
-        """Return true if port is a source (false for sink)"""
-        return self._is_source
 
-    def add_sinks(self, sinks):
-        """Add sinks to source port"""
-        self._sinks.extend(sinks)
+@dataclass
+class Nets:
+    source: dict[int, NetPort] = Field(default_factory=dict)
+    sinks: dict[int, list[NetPort]] = Field(default_factory=dict)
 
-    def get_sinks(self):
-        """Get source port sinks"""
-        return self._sinks
 
-    def get_nets(self):
-        """Get port nets"""
-        return self._nets
-
-    def from_module_dict(self, port_dict, global_nets):
-        """Create xternal port from module dict"""
-        self._is_source = port_dict["direction"] == "input"
-        for net in port_dict["bits"]:
-            if net not in global_nets:
-                global_nets.append(net)
-            self._nets.append(net)
-
-
-class _NetlistBlock:
-    """Common base class for modules and cells"""
-
-    def __init__(self, name, block_type=None):
-        self._name = name
-        self._ports = {}
-        self._nets = []
-        self._block_type = block_type
-        self._net_to_source_port = {}
-        self._net_to_sink_ports = {}
-
-    def name(self):
-        """Return name of block (cell or module)"""
-        return self._name
-
-    def get_type(self):
-        """Get type"""
-        return self._block_type
-
-    def set_type(self, block_type):
-        """Set type"""
-        self._block_type = block_type
-
-    def add_port(self, name, port):
-        """Add port to block (cell or module)"""
-        self._ports[name] = port
-        nets = port.get_nets()
-        if port.is_source():
-            for net in nets:
-                self._net_to_source_port[net] = port
-        else:
-            for net in nets:
-                if net not in self._net_to_sink_ports:
-                    self._net_to_sink_ports[net] = []
-                if port not in self._net_to_sink_ports[net]:
-                    self._net_to_sink_ports[net].append(port)
-
-    def get_nets(self):
-        """Get nets of block (cell or module)"""
-        return self._nets
-
-    def get_source_ports(self):
-        """Get source ports of block (cell or module)"""
-        ports = []
-        for _, port in self._net_to_source_port.items():
-            ports.append(port)
-        return ports
-
-    def get_source_port(self, net):
-        """Get source port of block (cell or module)"""
-        return self._net_to_source_port.get(net)
-
-    def get_sink_ports(self, net):
-        """Get sink port of block (cell or module)"""
-        return self._net_to_sink_ports.get(net, [])
+@dataclass
+class YosysPort:
+    direction: str
+    bits: list[Union[int, str]]
 
+    @property
+    def is_output(self):
+        return self.direction == "output"
 
-class _NetlistCell(_NetlistBlock):
-    """A class holding a cell in a yosys netlist"""
+    def is_same(self, compare_port):
+        return (compare_port.direction == self.direction) and (
+            len(compare_port.bits) == len(self.bits)
+        )
 
-    def __init__(self, name):
-        super().__init__(name)
 
-    def get_friendly_name(self):
+@dataclass
+class YosysCell:
+    type: str
+    port_directions: dict[str, str] = Field(default_factory=dict)
+    connections: dict[str, list[Union[str, int]]] = Field(default_factory=dict)
+    hide_name: int = 0
+    parameters: dict[str, Any] = Field(default_factory=dict)
+    attributes: dict[str, Any] = Field(default_factory=dict)
+
+    def get_nets(self, name, nets):
+        for port_name, net_list in self.connections.items():
+            net = net_list[0]
+            port = NetPort(parent=self, parent_name=name, name=port_name)
+            if self.port_directions[port_name] == "input":
+                if net not in nets.sinks:
+                    nets.sinks[net] = []
+                nets.sinks[net].append(port)
+            else:
+                nets.source[net] = port
+
+    def component_name(self, name):
         """Return a friendly name for a netlist cell"""
-        return f"{self.name().split('$')[-1]}_{self.get_friendly_type()}"
+        return f"{name.split('$')[-1]}_{self.component_type()}"
 
-    def get_friendly_type(self):
+    def component_type(self):
         """Return a friendly type for a netlist cell"""
-        return f"_{self.get_type()[2:-1]}_"
-
-    def from_dict(self, cell_dict, global_nets):
-        """Create netlist cell from dict"""
-        self.set_type(cell_dict["type"])
-        for port_name, port_dir in cell_dict["port_directions"].items():
-            output = port_dir == "output"
-            port_net = cell_dict["connections"][port_name]
-            self._nets.extend(port_net)
-            for net in port_net:
-                if net not in global_nets:
-                    global_nets.append(net)
-                port = _NetlistPort(self, port_name, net, output)
-                self.add_port(port_name, port)
-
-
-class _NestlistModule(_NetlistBlock):
-    """A class holding a module in a yosys netlist"""
-
-    def __init__(self, name):
-        super().__init__(name, "module")
-        self._cells = {}
-        self._module_nets = []
-        self._ext_if = {}
-
-        static_cell = _NetlistCell("StaticLevel")
-        static_cell.from_dict(
-            {
-                "type": "$_StaticLevel_",
-                "port_directions": {"L": "output", "H": "output"},
-                "connections": {"L": ["0"], "H": ["1"]},
-            },
-            self._nets,
-        )
-        self._cells["StaticLevel"] = static_cell
+        return f"_{self.type[2:-1]}_"
 
-    def from_dict(self, module_dict):
-        """Create module from dict"""
-        for ext_port_name, port_dict in module_dict["ports"].items():
-            ext_port = _NetlistPort(self, ext_port_name)
-            ext_port.from_module_dict(port_dict, self._nets)
-            nets = ext_port.get_nets()
-            ext_port_dict = {"output": ext_port.is_source(), "nets": nets}
-            self._ext_if[ext_port_name] = ext_port_dict
-            self.add_port(ext_port_name, ext_port)
 
-        for cell_name, cell_dict in module_dict["cells"].items():
-            cell = _NetlistCell(cell_name)
-            cell.from_dict(cell_dict, self._nets)
-            self._cells[cell_name] = cell
+@dataclass
+class YosysNetName:
+    bits: list[int]
+    attributes: dict[str, Any] = Field(default_factory=dict)
+    hide_name: int = 0
 
-    def get_cells(self):
-        """Get cells dict"""
-        return self._cells
 
-    def get_external_interface(self):
-        """Get external interface dict"""
-        return self._ext_if
+@dataclass
+class YosysModule:
+    attributes: dict[str, Any] = Field(default_factory=dict)
+    parameter_default_values: dict[str, Any] = Field(default_factory=dict)
+    ports: dict[str, YosysPort] = Field(default_factory=dict)
+    cells: dict[str, YosysCell] = Field(default_factory=dict)
+    netnames: dict[str, YosysNetName] = Field(default_factory=dict)
 
-    def get_source(self, net):
-        """Get source port for net"""
-        module_port = self.get_source_port(net)
-        if module_port is not None:
-            return module_port
-        for _, cell in self._cells.items():
-            cell_port = cell.get_source_port(net)
-            if cell_port is not None:
-                return cell_port
-        return None
+    def is_same_interface(self, netlist):
+        is_same = True
+        for netlist_port_name, netlist_port in netlist.ports.items():
+            module_port = self.ports.get(netlist_port_name)
+            if module_port is None or not module_port.is_same(netlist_port):
+                is_same = False
+                break
+        return is_same
 
-    def get_sinks(self, net):
-        """Get module sinks (input ports)"""
-        sink_ports = self.get_sink_ports(net)
-        for _, cell in self._cells.items():
-            cell_sink_ports = cell.get_sink_ports(net)
-            for port in cell_sink_ports:
-                if port not in sink_ports:
-                    sink_ports.append(port)
-        return sink_ports
-
-    def connect(self):
-        """Connect all nets within module"""
-        _source_port_dict = {}
-        _sink_ports_dict = {}
-        _cells_dict = {}
-
-        # Build net to cell dict
-        for _, cell in self._cells.items():
-            for cell_net in cell.get_nets():
-                if cell_net not in _cells_dict:
-                    _cells_dict[cell_net] = []
-                _cells_dict[cell_net].append(cell)
-
-        # Build net to ports dict
-        for net in self._nets:
-            # Module
-            port = self.get_source_port(net)
-            if port is not None:
-                _source_port_dict[net] = port
-            sink_ports = self.get_sink_ports(net)
-            # Cells
-            for cell in _cells_dict.get(net, []):
-                port = cell.get_source_port(net)
-                if port is not None:
-                    _source_port_dict[net] = port
-                cell_sink_ports = cell.get_sink_ports(net)
-                sink_ports.extend(cell_sink_ports)
-            _sink_ports_dict[net] = sink_ports
+    def get_nets(self):
+        nets = Nets()
 
-        # Connect
-        for net in self._nets:
-            source_port = _source_port_dict[net]
-            sink_ports = _sink_ports_dict[net]
-            source_port.add_sinks(sink_ports)
+        for port_name, port_item in self.ports.items():
+            for bit_index, net in enumerate(port_item.bits):
+                port = NetPort(parent=self, parent_name="top", name=port_name, bit_index=bit_index)
+                if port_item.is_output:
+                    if net not in nets.sinks:
+                        nets.sinks[net] = []
+                    nets.sinks[net].append(port)
+                else:
+                    nets.source[net] = port
 
-        # Connect module nets
-        for module_net in self._module_nets:
-            nets = module_net.get_nets()
-            ports = []
-            for net in nets:
-                port = _source_port_dict[net]
-                ports.append(port)
-            module_net.set_ports(ports)
+        for cell_name, cell in self.cells.items():
+            cell.get_nets(cell_name, nets)
 
-    def get_module_nets(self):
-        """Get the nets for this module"""
-        return self._module_nets
+        return nets
 
 
+@dataclass
 class YosysNetlist:
-    """A class holding the content of a yosys netlist"""
-
-    def __init__(self):
-        self._modules = {}
+    creator: Optional[str] = None
+    modules: dict[str, YosysModule] = Field(default_factory=dict)
 
     def get_modules(self):
-        """Get modules dict"""
-        return self._modules
-
-    def from_dict(self, netlist_dict):
-        """Parse netlist from dict"""
-        for module_name, module_dict in netlist_dict["modules"].items():
-            module = _NestlistModule(module_name)
-            module.from_dict(module_dict)
-            self._modules[module_name] = module
-        for _, module in self._modules.items():
-            module.connect()
+        return self.modules

{digsim_logic_simulator-0.7.0.dist-info → digsim_logic_simulator-0.9.0.dist-info}/METADATA

@@ -1,42 +1,9 @@
 Metadata-Version: 2.4
 Name: digsim-logic-simulator
-Version: 0.7.0
+Version: 0.9.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>
-License: The Clear BSD License
-        
-        Copyright (c) 2023-2024, Fredrik Andersson
-        All rights reserved.
-        
-        Redistribution and use in source and binary forms, with or without
-        modification, are permitted provided that the following conditions are met:
-        
-        * Redistributions of source code must retain the above copyright notice, this
-          list of conditions and the following disclaimer.
-        
-        * Redistributions in binary form must reproduce the above copyright notice,
-          this list of conditions and the following disclaimer in the documentation
-          and/or other materials provided with the distribution.
-        
-        * Neither the name of the copyright holder nor the names of its
-          contributors may be used to endorse or promote products derived from
-          this software without specific prior written permission.
-        
-        NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS
-        LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-        "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-        THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-        ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-        LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-        CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-        GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-        HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-        LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-        OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-        
-        -------------------------------------------------------------------------------
-        
 Project-URL: homepage, https://github.com/freand76/digsim
 Keywords: educational,simulation,digital
 Classifier: Development Status :: 5 - Production/Stable
@@ -50,12 +17,12 @@ Classifier: Programming Language :: Python :: 3 :: Only
 Requires-Python: >=3.9
 Description-Content-Type: text/markdown
 License-File: LICENSE.md
-Requires-Dist: pyvcd>=0.4.1
-Requires-Dist: pyside6>=6.9.0
+Requires-Dist: pyvcd==0.4.1
+Requires-Dist: pyside6==6.9.1
 Requires-Dist: pexpect==4.9.0
-Requires-Dist: pydantic==2.11.4
+Requires-Dist: pydantic==2.11.7
 Requires-Dist: qtawesome==1.4.0
-Requires-Dist: yowasp-yosys==0.53.0.0.post912
+Requires-Dist: yowasp-yosys==0.57.0.0.post986
 Dynamic: license-file
 
 # DigSim - Interactive Digital Logic Simulator

{digsim_logic_simulator-0.7.0.dist-info → digsim_logic_simulator-0.9.0.dist-info}/RECORD

@@ -1,7 +1,7 @@
 digsim/__init__.py,sha256=UB-i1HtNR6rIX4_SClZp-lM4njGa7_1sbMvd14NuyAs,149
 digsim/app/__main__.py,sha256=iECz0kvEQ0R4fGzH6KAOxyDfoyvwrRLo7JmT0jMx39s,1368
 digsim/app/gui/__init__.py,sha256=-HnN8a-AcDcovbCHf1a_R-sQtW2_tQXnPJ3izyKLOjw,165
-digsim/app/gui/_circuit_area.py,sha256=w2K0n3ubbLvwiZHs2NyErUoNly0_TWFTf-XXsCtxpVY,16366
+digsim/app/gui/_circuit_area.py,sha256=rbqP957eVAuYBvtg5anybOrvnGc6TSe9dB_0rRsHSDI,16366
 digsim/app/gui/_component_selection.py,sha256=C-TeBruf8sGdEnGATtLm6jTesIqf-0AnKRBRLrtL_18,6388
 digsim/app/gui/_main_window.py,sha256=X0AIh3m1ySaldgYr3MHddRSqVkNdWl_qNJOIdnv2mNA,5275
 digsim/app/gui/_top_bar.py,sha256=HWGiWTKjYz3yRJ4K1tbMyVxhTC-Y6LEiREr6nHMAhKE,13067
@@ -17,7 +17,7 @@ digsim/app/gui_objects/_dip_switch_object.py,sha256=6SmqoyF3MuUphLJA4tlyff4JXJBx
 digsim/app/gui_objects/_gui_note_object.py,sha256=sMakGjdR0truGBzaR2GaFZZoDg99v76Bs5DD6ea3cjA,2604
 digsim/app/gui_objects/_gui_object_factory.py,sha256=wfe0M4ZNSd5mK_0fi6ZhzHddFxkm_t4tku3OZir2VzU,2465
 digsim/app/gui_objects/_hexdigit_object.py,sha256=cCxxpcSRLXRFNLIfrY_AUBGOSVIjRjO3HAuOv7wXGkI,1930
-digsim/app/gui_objects/_image_objects.py,sha256=KQgWaiEoqbtqWib-pCoo-qs-J3GvRlVQFzjLNEBx-JQ,7553
+digsim/app/gui_objects/_image_objects.py,sha256=hOFgkpp0Ar0btncVXp7Jors7hXQQENc1FqzJGS1m_G0,7613
 digsim/app/gui_objects/_label_object.py,sha256=6CnISeYEmmef28T6yBYJ1z-a_3nTtyl4p-EU-pEzVK0,3570
 digsim/app/gui_objects/_logic_analyzer_object.py,sha256=B3WpFrTu9LDF0S_ol0VVS4vOIDqw_e08wmEX7fBjD98,2671
 digsim/app/gui_objects/_seven_segment_object.py,sha256=EaNRxmM_IA-JkLHVVHXwSCd8jV9JAXTmdXMuXOidio4,4227
@@ -60,8 +60,8 @@ digsim/app/settings/_component_settings.py,sha256=88D9OuEcFIlaqZozomWHSYrl7opz4j
 digsim/app/settings/_gui_settings.py,sha256=sDi2POUsHvS7_4SO5qsTu_nN48HsTN4UfGPzdmECs9w,2764
 digsim/app/settings/_shortcut_dialog.py,sha256=JTm7aawG2ar_DvWhBT8ZzgWsq9gLEJ6pJ_-eHUMPh-c,1524
 digsim/circuit/__init__.py,sha256=yGyhcdnlcpht_hyR2az_A4c7-bO_NkT2lBIDFvtI010,216
-digsim/circuit/_circuit.py,sha256=UNJBM2MyTXPWWEPXe4T4Z9Qc6vsm9We_Rk7mEfV9yIA,10023
-digsim/circuit/_waves_writer.py,sha256=hh-hwNrT9c0jDLLxYw0anvwomJXVJK5iIbGVjcQddG0,1645
+digsim/circuit/_circuit.py,sha256=r_QFKhB13p9hLbrKUN0RtR1o2sqc-UNemdiz-La8cGY,10956
+digsim/circuit/_waves_writer.py,sha256=ZedBa2TbWuq-zDc1MQyANmQOMDGGzNMSh4nKPuqXCkA,2092
 digsim/circuit/components/__init__.py,sha256=j-xNFbXJ15rSJLhDg7E-SlKvxn6Uy7Zl42YDUkZBFZo,1267
 digsim/circuit/components/_bus_bits.py,sha256=mHWkwAHtkEq88pOEQ0b5ndFZvum794j7kUkTAWHUCdc,1916
 digsim/circuit/components/_button.py,sha256=Q8drjQ2kNFCfgK-7UzlmNHP47bOpGa9_t16pDtjhL4s,1028
@@ -72,7 +72,7 @@ digsim/circuit/components/_flip_flops.py,sha256=eOB1hpSfK7vlpcOQzHqILpAzfwsqQPob
 digsim/circuit/components/_gates.py,sha256=K_aFT4GTo4JF_zoaNYiCRZfZEx4vEibMHZSCDImfPHQ,7167
 digsim/circuit/components/_hexdigit.py,sha256=MQlmEnQkQnuH6rGc-FB68mOctjVY8QyAR5FCOHYNCns,2259
 digsim/circuit/components/_ic.py,sha256=Rs8Z_PuhKo3peK9pwdbvlGNK8_w6evSdXYNdrjWB3-8,917
-digsim/circuit/components/_label_wire.py,sha256=5xcPNWt8GtQEUk_BDJXWHQ3RfH62bAFQpiyeJlppOpA,5116
+digsim/circuit/components/_label_wire.py,sha256=wAAvq-o1ygsX5br6O9KvsPtQyU5C2FdMRUJP_WWlXSw,5164
 digsim/circuit/components/_led.py,sha256=hR_iclDWZua8duNy9BQcTBuhKkIh3g5ahpfkHQ1LYSA,452
 digsim/circuit/components/_logic_analyzer.py,sha256=K6sUfN23lUfQ5GHQFrxvR8fgfWKLy29Cj0K7dZzW_cE,1809
 digsim/circuit/components/_mem64kbyte.py,sha256=tqex3qFxa7jk841f87inNB4UIY9E5z1SleqAL82eCUY,1482
@@ -83,23 +83,23 @@ digsim/circuit/components/_seven_segment.py,sha256=UxxjGLuIirVB2Px09XlL8_zjgE7F8
 digsim/circuit/components/_static_level.py,sha256=2Assm1cmAfryVZ3KTQ1uGY8Q6eRrBipdwLITewXfIHg,677
 digsim/circuit/components/_static_value.py,sha256=vfRPS_F9mKOXpHJxzs0JQKXqcj0o6d-090zbyZaECA4,1236
 digsim/circuit/components/_yosys_atoms.py,sha256=NeH8XjjpoACHBfQRqR5RJxWorZhSjGk0t73cJOviSZw,37599
-digsim/circuit/components/_yosys_component.py,sha256=XDNSAfM6Qvhe6G0-M1uiY2NQ-A6oPSQX4kcB_ccvSWg,8810
-digsim/circuit/components/atoms/__init__.py,sha256=kPr-ZKYPiW8NgEvKooMyLYc4DpfMurkALqWcKLhuK28,483
-digsim/circuit/components/atoms/_component.py,sha256=pnPzWmJYvgcdYt0TFTq12M88mz-esZBg1E7VtlZ5WK8,8287
+digsim/circuit/components/_yosys_component.py,sha256=LkYneNSvzQMn61RzlHk3aSkl9tF6JjibknfwmLeWCFk,8792
+digsim/circuit/components/atoms/__init__.py,sha256=NU45pfJcSrdwZA-SVQeORlaznl_0BciY4VN3vVSnD8o,498
+digsim/circuit/components/atoms/_component.py,sha256=DpMS1yOWWgk11Y9ae0PfuOJdlJsrzgrzuYrgsN62dbQ,8815
 digsim/circuit/components/atoms/_digsim_exception.py,sha256=Y5mBve15zZbduqNNAyf7WzqDk4NtvUL_g2vYy5kBQ3U,173
-digsim/circuit/components/atoms/_port.py,sha256=BzfCBSQT34AMH10PyAj-eg0UqQpvFJz01fd3HmCwHhE,11688
-digsim/circuit/components/ic/74162.json,sha256=BtLDDhNP4jYQD2EZ2nBHfUMRbuPztR54luLEpWl7j-o,26632
-digsim/circuit/components/ic/7448.json,sha256=7p9l6l_QSw6DtphZcGgBMMP0PyMB5DYglciMhqCKp04,21211
+digsim/circuit/components/atoms/_port.py,sha256=yT1TqmKPVlw8G_0r_6dErcqIkXCqB8z0pE5oL6Bnxzo,12596
+digsim/circuit/components/ic/74162.json,sha256=RAeSva6TVuwfKHsvU9HC-ZVfRVrCkIsQUz_jcANT_fE,26693
+digsim/circuit/components/ic/7448.json,sha256=hKMXhPqW-JBTF6rdz9u5HC_hY9cBRpJtMkLP7uOQXIo,21185
 digsim/storage_model/__init__.py,sha256=lubmO9_BCUtEahyW1yE7f3aGHngEevGIwf_0LeOB7Y8,289
 digsim/storage_model/_app.py,sha256=Aer9s_mUBKSydsyeWYvVPHX2XF5ZGPuXq8z4PoXu8lA,1353
 digsim/storage_model/_circuit.py,sha256=NnaHLwqb9gAhqAxeZ1RkHHvoS_YJwixlz0xs-zmIrQU,3596
 digsim/synth/__init__.py,sha256=jhBHLOHf-vNa94Zg5q5dGcf0fgQTModfjUKtmUSffiw,180
 digsim/synth/__main__.py,sha256=wZWAzWsisoxA7hfqkKtu3H066uWyFajgPro2MEGlKbs,2173
 digsim/synth/_synthesis.py,sha256=ug9vSeTyZrvRCboNLL7dDIFVpGqH_ibr5fhOZJHpqUs,4271
-digsim/utils/__init__.py,sha256=Az_zmbORYMzmptuA2_xfn5jDxbCPRSMlVuntr0sYexU,167
-digsim/utils/_yosys_netlist.py,sha256=FevsHPSKoBk8SSBzvSGkJeTFOiZajjbWCHjZUZwfF4g,8562
-digsim_logic_simulator-0.7.0.dist-info/licenses/LICENSE.md,sha256=FrvohZfyfpH4xrvKdXiQ5hD7dUB7w4DcsRA3p-pOmLw,1693
-digsim_logic_simulator-0.7.0.dist-info/METADATA,sha256=B9bPM0Q8X16INltjcNg_SstiiZ63eCEPxX8c3OJHyPI,6516
-digsim_logic_simulator-0.7.0.dist-info/WHEEL,sha256=0CuiUZ_p9E4cD6NyLD6UG80LBXYyiSYZOKDm5lp32xk,91
-digsim_logic_simulator-0.7.0.dist-info/top_level.txt,sha256=qpCMzQKADZHVqZIoQgFrv3qJ3u7PPU73gTCXQglqLa8,7
-digsim_logic_simulator-0.7.0.dist-info/RECORD,,
+digsim/utils/__init__.py,sha256=MT9TNcpa7fNAqtBsmCcceKMrUSU_v9xeJ6Nox_TL7Lo,191
+digsim/utils/_yosys_netlist.py,sha256=TnEQc27NxPD96uGAF_wiijsZsX59vmDqzNP9rkMnLyc,3612
+digsim_logic_simulator-0.9.0.dist-info/licenses/LICENSE.md,sha256=FrvohZfyfpH4xrvKdXiQ5hD7dUB7w4DcsRA3p-pOmLw,1693
+digsim_logic_simulator-0.9.0.dist-info/METADATA,sha256=5NVelguEoPG3GlO78OlDNwfzX-NWC5Zqt1w8BD5yIVA,4557
+digsim_logic_simulator-0.9.0.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
+digsim_logic_simulator-0.9.0.dist-info/top_level.txt,sha256=qpCMzQKADZHVqZIoQgFrv3qJ3u7PPU73gTCXQglqLa8,7
+digsim_logic_simulator-0.9.0.dist-info/RECORD,,

{digsim_logic_simulator-0.7.0.dist-info → digsim_logic_simulator-0.9.0.dist-info}/WHEEL

@@ -1,5 +1,5 @@
 Wheel-Version: 1.0
-Generator: setuptools (80.3.1)
+Generator: setuptools (80.9.0)
 Root-Is-Purelib: true
 Tag: py3-none-any