digsim-logic-simulator 0.6.0__py3-none-any.whl → 0.8.0__py3-none-any.whl
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- digsim/app/gui/_circuit_area.py +2 -2
- digsim/app/gui/_top_bar.py +1 -1
- digsim/app/gui_objects/_component_object.py +1 -1
- digsim/app/gui_objects/_hexdigit_object.py +1 -1
- digsim/app/gui_objects/_image_objects.py +4 -2
- digsim/circuit/_circuit.py +60 -41
- digsim/circuit/_waves_writer.py +19 -8
- digsim/circuit/components/_label_wire.py +3 -3
- digsim/circuit/components/atoms/__init__.py +2 -1
- digsim/circuit/components/atoms/_component.py +40 -37
- digsim/circuit/components/atoms/_port.py +70 -65
- digsim/circuit/components/ic/74162.json +86 -85
- digsim/circuit/components/ic/7448.json +62 -61
- digsim/utils/_yosys_netlist.py +3 -1
- {digsim_logic_simulator-0.6.0.dist-info → digsim_logic_simulator-0.8.0.dist-info}/METADATA +10 -41
- {digsim_logic_simulator-0.6.0.dist-info → digsim_logic_simulator-0.8.0.dist-info}/RECORD +19 -19
- {digsim_logic_simulator-0.6.0.dist-info → digsim_logic_simulator-0.8.0.dist-info}/WHEEL +1 -1
- {digsim_logic_simulator-0.6.0.dist-info → digsim_logic_simulator-0.8.0.dist-info/licenses}/LICENSE.md +0 -0
- {digsim_logic_simulator-0.6.0.dist-info → digsim_logic_simulator-0.8.0.dist-info}/top_level.txt +0 -0
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1073
1074
|
},
|
|
1074
1075
|
"Load_bar": {
|
|
1075
1076
|
"hide_name": 0,
|
|
1076
1077
|
"bits": [ 3 ],
|
|
1077
1078
|
"attributes": {
|
|
1078
|
-
"src": "
|
|
1079
|
+
"src": "verilog/74xx/74162.v:6.9-6.17"
|
|
1079
1080
|
}
|
|
1080
1081
|
},
|
|
1081
1082
|
"Q": {
|
|
1082
1083
|
"hide_name": 0,
|
|
1083
1084
|
"bits": [ 12, 13, 14, 15 ],
|
|
1084
1085
|
"attributes": {
|
|
1085
|
-
"src": "
|
|
1086
|
+
"src": "verilog/74xx/74162.v:12.22-12.23"
|
|
1086
1087
|
}
|
|
1087
1088
|
},
|
|
1088
1089
|
"Q_current": {
|
|
1089
1090
|
"hide_name": 0,
|
|
1090
1091
|
"bits": [ 12, 13, 14, 15 ],
|
|
1091
1092
|
"attributes": {
|
|
1092
|
-
"src": "
|
|
1093
|
+
"src": "verilog/74xx/74162.v:17.17-17.26"
|
|
1093
1094
|
}
|
|
1094
1095
|
},
|
|
1095
1096
|
"RCO": {
|
|
1096
1097
|
"hide_name": 0,
|
|
1097
1098
|
"bits": [ 11 ],
|
|
1098
1099
|
"attributes": {
|
|
1099
|
-
"src": "
|
|
1100
|
+
"src": "verilog/74xx/74162.v:11.10-11.13"
|
|
1100
1101
|
}
|
|
1101
1102
|
},
|
|
1102
1103
|
"RCO_current": {
|
|
1103
1104
|
"hide_name": 0,
|
|
1104
1105
|
"bits": [ 11 ],
|
|
1105
1106
|
"attributes": {
|
|
1106
|
-
"src": "
|
|
1107
|
+
"src": "verilog/74xx/74162.v:16.6-16.17"
|
|
1107
1108
|
}
|
|
1108
1109
|
}
|
|
1109
1110
|
}
|