digsim-logic-simulator 0.4.0__py3-none-any.whl → 0.6.0__py3-none-any.whl

digsim/app/gui_objects/_component_object.py

@@ -9,6 +9,8 @@ from PySide6.QtCore import QPoint, QRect, QSize, Qt
 from PySide6.QtGui import QFont, QFontMetrics, QPen
 from PySide6.QtWidgets import QGraphicsItem, QGraphicsRectItem
 
+from digsim.storage_model import GuiPositionDataClass
+
 from ._component_context_menu import ComponentContextMenu
 from ._component_port_item import PortGraphicsItem
 
@@ -365,6 +367,7 @@ class ComponentObject(QGraphicsRectItem):
         """Set zlevel"""
         self.setZValue(level)
 
-    def to_dict(self):
-        """Return position as dict"""
-        return {"x": int(self._save_pos.x()), "y": int(self._save_pos.y()), "z": self.zlevel}
+    def to_gui_dataclass(self):
+        return GuiPositionDataClass(
+            x=int(self._save_pos.x()), y=int(self._save_pos.y()), z=int(self.zlevel)
+        )

digsim/app/model/_model.py

@@ -3,7 +3,6 @@
 
 """An application model for a GUI simulated circuit"""
 
-import json
 import queue
 import time
 from pathlib import Path
@@ -12,6 +11,7 @@ from PySide6.QtCore import QThread, Signal
 
 from digsim.app.gui_objects import ComponentObject
 from digsim.circuit.components.atoms import Component
+from digsim.storage_model import AppFileDataClass
 
 from ._model_objects import ModelObjects
 from ._model_settings import ModelSettings
@@ -155,28 +155,27 @@ class AppModel(QThread):
     def save_circuit(self, path):
         """Save the circuit with GUI information"""
         circuit_folder = str(Path(path).parent)
-        circuit_dict = self.objects.circuit_to_dict(circuit_folder)
-        shortcuts_dict = self.shortcuts.to_dict()
-        circuit_dict.update(shortcuts_dict)
-        settings_dict = self.settings.to_dict()
-        circuit_dict.update(settings_dict)
-        json_object = json.dumps(circuit_dict, indent=4)
-        with open(path, mode="w", encoding="utf-8") as json_file:
-            json_file.write(json_object)
+        model_dataclass = self.objects.circuit_to_model(circuit_folder)
+        appfile_dataclass = AppFileDataClass(
+            circuit=model_dataclass.circuit,
+            gui=model_dataclass.gui,
+            shortcuts=self.shortcuts.to_dict(),
+            settings=self.settings.get_all(),
+        )
+        appfile_dataclass.save(path)
         self._changed = False
         self.sig_control_notify.emit()
 
     def load_circuit(self, path):
         """Load a circuit with GUI information"""
         self._model_clear()
-        with open(path, mode="r", encoding="utf-8") as json_file:
-            circuit_dict = json.load(json_file)
+        app_file_dc = AppFileDataClass.load(path)
         circuit_folder = str(Path(path).parent)
         if len(circuit_folder) == 0:
             circuit_folder = "."
-        exception_str_list = self.objects.dict_to_circuit(circuit_dict, circuit_folder)
-        self.shortcuts.from_dict(circuit_dict)
-        self.settings.from_dict(circuit_dict)
+        exception_str_list = self.objects.model_to_circuit(app_file_dc, circuit_folder)
+        self.shortcuts.from_dict(app_file_dc.shortcuts)
+        self.settings.from_dict(app_file_dc.settings)
         self.model_init()
         self._changed = False
         self.objects.reset_undo_stack()

digsim/app/model/_model_components.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
 """Handle component objects in the model"""
@@ -7,6 +7,7 @@ import digsim.circuit.components
 from digsim.app.gui_objects import ComponentObject
 from digsim.circuit.components import Buzzer
 from digsim.circuit.components.atoms import CallbackComponent
+from digsim.storage_model import GuiPositionDataClass
 
 
 class ModelComponents:
@@ -149,20 +150,16 @@ class ModelComponents:
         self._circuit.delete_component(component_object.component)
         self._app_model.sig_delete_component.emit(component_object)
 
-    def create_from_dict(self, circuit_dict):
+    def add_gui_positions(self, gui_dc_dict):
         """Create model components from circuit_dict"""
         for comp in self._circuit.get_toplevel_components():
-            gui_dict = circuit_dict.get("gui", {})
-            component_dict = gui_dict.get(comp.name(), {})
-            x = component_dict.get("x", 100)
-            y = component_dict.get("y", 100)
-            z = component_dict.get("z", 0)
-            component_object = self._add_object(comp, x, y)
-            component_object.zlevel = z
-
-    def get_circuit_dict(self):
-        """Create model components dict"""
-        model_components_dict = {"gui": {}}
+            gui_dc = gui_dc_dict.get(comp.name(), GuiPositionDataClass())
+            component_object = self._add_object(comp, gui_dc.x, gui_dc.y)
+            component_object.zlevel = gui_dc.z
+
+    def get_gui_dict(self):
+        """Return gui dict from component objects"""
+        gui_dict = {}
         for comp, comp_object in self.get_dict().items():
-            model_components_dict["gui"][comp.name()] = comp_object.to_dict()
-        return model_components_dict
+            gui_dict[comp.name()] = comp_object.to_gui_dataclass()
+        return gui_dict

digsim/app/model/_model_objects.py

@@ -5,6 +5,7 @@
 
 from digsim.circuit import Circuit
 from digsim.circuit.components.atoms import DigsimException
+from digsim.storage_model import AppFileDataClass, ModelDataClass
 
 from ._model_components import ModelComponents
 from ._model_new_wire import NewWire
@@ -72,32 +73,37 @@ class ModelObjects:
             self._app_model.model_changed()
         self._app_model.sig_delete_wires.emit()
 
-    def circuit_to_dict(self, circuit_folder):
-        """Convert circuit and objects to dict"""
-        circuit_dict = self.circuit.to_dict(circuit_folder)
-        model_components_dict = self.components.get_circuit_dict()
-        circuit_dict.update(model_components_dict)
-        return circuit_dict
+    def model_to_circuit(self, model_dc, circuit_folder):
+        if isinstance(model_dc, AppFileDataClass):
+            # Loaded model
+            dc = ModelDataClass.from_app_file_dc(model_dc)
+        else:
+            dc = model_dc
 
-    def dict_to_circuit(self, circuit_dict, circuit_folder):
-        """Convert dict to circuit and objects"""
-        exception_str_list = []
         try:
-            exception_str_list = self.circuit.from_dict(
-                circuit_dict, circuit_folder, component_exceptions=False, connect_exceptions=False
+            # Create circuit
+            exception_str_list = self.circuit.from_dataclass(
+                dc.circuit,
+                circuit_folder,
+                component_exceptions=False,
+                connect_exceptions=False,
             )
+            # Add component positions
+            self.components.add_gui_positions(dc.gui)
         except DigsimException as exc:
             self.sig_error.emit(f"Circuit error: {str(exc)}")
             return exception_str_list
-
-        # Create GUI components
-        self.components.create_from_dict(circuit_dict)
-
         return exception_str_list
 
-    def _restore_state(self, state):
+    def circuit_to_model(self, circuit_folder):
+        model_dc = ModelDataClass(
+            circuit=self.circuit.to_dataclass(circuit_folder), gui=self.components.get_gui_dict()
+        )
+        return model_dc
+
+    def _restore_state(self, model_dc):
         self.clear()
-        exception_str_list = self.dict_to_circuit(state, "/")
+        exception_str_list = self.model_to_circuit(model_dc, None)
         self._app_model.model_init()
         self._app_model.model_changed()
         if len(exception_str_list) > 0:
@@ -111,7 +117,7 @@ class ModelObjects:
 
     def push_undo_state(self, clear_redo_stack=True):
         """Push undo state to stack"""
-        self._undo_stack.append(self.circuit_to_dict("/"))
+        self._undo_stack.append(self.circuit_to_model("/"))
         if clear_redo_stack:
             self._redo_stack = []
             self._app_model.sig_control_notify.emit()
@@ -124,14 +130,14 @@ class ModelObjects:
 
     def push_redo_state(self):
         """Push redo state to stack"""
-        self._redo_stack.append(self.circuit_to_dict("/"))
+        self._redo_stack.append(self.circuit_to_model("/"))
 
     def undo(self):
         """Undo to last saved state"""
         if len(self._undo_stack) > 0:
             self.push_redo_state()
-            state = self._undo_stack.pop()
-            self._restore_state(state)
+            model_dc = self._undo_stack.pop()
+            self._restore_state(model_dc)
             self._app_model.sig_control_notify.emit()
             self._app_model.sig_synchronize_gui.emit()
 
@@ -139,8 +145,8 @@ class ModelObjects:
         """Undo to last saved state"""
         if len(self._redo_stack) > 0:
             self.push_undo_state(clear_redo_stack=False)
-            state = self._redo_stack.pop()
-            self._restore_state(state)
+            model_dc = self._redo_stack.pop()
+            self._restore_state(model_dc)
             self._app_model.sig_control_notify.emit()
             self._app_model.sig_synchronize_gui.emit()
 

digsim/app/model/_model_settings.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
 """Handle settings in the model"""
@@ -25,10 +25,6 @@ class ModelSettings:
         """Return settings dict"""
         return self._settings
 
-    def to_dict(self):
-        """Return settings dict to save"""
-        return {"settings": self._settings}
-
     def from_dict(self, circuit_dict):
         """Get settings from circuit dict"""
         for key, data in circuit_dict.get("settings", {}).items():

digsim/app/model/_model_shortcuts.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
 """Handle shortcuts in the model"""
@@ -72,9 +72,9 @@ class ModelShortcuts:
 
     def to_dict(self):
         """Generate dict from shortcuts"""
-        shortcuts_dict = {"shortcuts": {}}
+        shortcuts_dict = {}
         for key, component in self._shortcut_component.items():
-            shortcuts_dict["shortcuts"][key] = component.name()
+            shortcuts_dict[key] = component.name()
         return shortcuts_dict
 
     def from_dict(self, model_dict):

digsim/app/settings/_component_settings.py

@@ -358,9 +358,9 @@ class ComponentSettingsDialog(QDialog):
                 widget = ComponentSettingsCheckBoxWidthBool(
                     self, parameter, parameter_dict, self._settings
                 )
-            elif parameter_dict["type"] == int:
+            elif parameter_dict["type"] == "int":
                 widget = ComponentSettingsSlider(self, parameter, parameter_dict, self._settings)
-            elif parameter_dict["type"] == str:
+            elif parameter_dict["type"] == "str":
                 single_line = parameter_dict.get("single_line", False)
                 if single_line:
                     widget = ComponentSettingSingleLineText(
@@ -368,7 +368,7 @@ class ComponentSettingsDialog(QDialog):
                     )
                 else:
                     widget = ComponentSettingText(self, parameter, parameter_dict, self._settings)
-            elif parameter_dict["type"] == bool:
+            elif parameter_dict["type"] == "bool":
                 widget = ComponentSettingsCheckBox(self, parameter, parameter_dict, self._settings)
             elif parameter_dict["type"] == "intrange":
                 widget = ComponentSettingsIntRangeSlider(
@@ -382,7 +382,7 @@ class ComponentSettingsDialog(QDialog):
                 widget = ComponentSettingsNameSelector(
                     self, parameter, parameter_dict, self._settings
                 )
-            elif parameter_dict["type"] == list:
+            elif parameter_dict["type"] == "list":
                 widget = ComponentSettingsListSelector(
                     self, parameter, parameter_dict, self._settings
                 )

digsim/circuit/_circuit.py

@@ -5,11 +5,12 @@
 Module that handles the circuit simulation of components
 """
 
-import json
 import os
 
+from digsim.storage_model import CircuitDataClass, CircuitFileDataClass
+
 from ._waves_writer import WavesWriter
-from .components.atoms import Component, DigsimException
+from .components.atoms import DigsimException
 
 
 class CircuitError(DigsimException):
@@ -70,6 +71,11 @@ class Circuit:
         else:
             self._vcd = None
 
+    @property
+    def name(self):
+        """Get the circuit name"""
+        return self._name
+
     @property
     def time_ns(self):
         """Get the current simulation time (ns)"""
@@ -243,65 +249,24 @@ class Circuit:
             return comp
         raise CircuitError(f"Component '{component_name}' not found")
 
-    def _connect_from_dict(self, source, dest):
-        source_component_name = source.split(".")[0]
-        source_port_name = source.split(".")[1]
-        dest_component_name = dest.split(".")[0]
-        dest_port_name = dest.split(".")[1]
-
-        source_component = self.get_component(source_component_name)
-        dest_componment = self.get_component(dest_component_name)
-        source_component.port(source_port_name).wire = dest_componment.port(dest_port_name)
-
-    def to_dict(self, folder=None):
+    def to_dataclass(self, folder=None):
         """Generate dict from circuit, used when storing circuit"""
         if self._name is None:
             raise CircuitError("Circuit must have a name")
-
         self._folder = folder
-        components_list = []
-        for comp in self.get_toplevel_components():
-            components_list.append(comp.to_dict())
+        return CircuitDataClass.from_circuit(self)
 
-        connection_list = []
-        for comp in self.get_toplevel_components():
-            for port in comp.ports:
-                port_conn_list = port.to_dict_list()
-                connection_list.extend(port_conn_list)
-
-        circuit_dict = {
-            "circuit": {
-                "name": self._name,
-                "components": components_list,
-                "wires": connection_list,
-            }
-        }
-
-        return circuit_dict
-
-    def from_dict(
-        self, circuit_dict, folder=None, component_exceptions=True, connect_exceptions=True
+    def from_dataclass(
+        self, circuit_dc, folder=None, component_exceptions=True, connect_exceptions=True
     ):
         """Clear circuit and add components from dict"""
         self._folder = folder
         self.clear()
-        if "circuit" not in circuit_dict:
-            raise CircuitError("No 'circuit' in JSON")
-        json_circuit = circuit_dict["circuit"]
-        if "name" not in json_circuit:
-            raise CircuitError("No 'circuit/name' in JSON")
-        self._name = json_circuit["name"]
-        if "components" not in json_circuit:
-            raise CircuitError("No 'circuit/components' in JSON")
-        json_components = json_circuit["components"]
-        if "wires" not in json_circuit:
-            raise CircuitError("No 'circuit/connections' in JSON")
-        json_connections = json_circuit["wires"]
 
         exception_str_list = []
-        for json_component in json_components:
+        for component in circuit_dc.components:
             try:
-                Component.from_dict(self, json_component)
+                component.create(self)
             except DigsimException as exc:
                 if component_exceptions:
                     raise exc
@@ -310,9 +275,9 @@ class Circuit:
                 if component_exceptions:
                     raise exc
                 exception_str_list.append(f"{str(exc.__class__.__name__)}:{str(exc)}")
-        for json_connection in json_connections:
+        for wire in circuit_dc.wires:
             try:
-                self._connect_from_dict(json_connection["src"], json_connection["dst"])
+                wire.connect(self)
             except DigsimException as exc:
                 if connect_exceptions:
                     raise exc
@@ -322,15 +287,10 @@ class Circuit:
 
     def to_json_file(self, filename):
         """Store circuit in json file"""
-        circuit_dict = self.to_dict()
-        json_object = json.dumps(circuit_dict, indent=4)
-
-        with open(filename, mode="w", encoding="utf-8") as json_file:
-            json_file.write(json_object)
+        circuitfile_dc = CircuitFileDataClass(circuit=self.to_dataclass())
+        circuitfile_dc.save(filename)
 
     def from_json_file(self, filename, folder=None):
         """Load circuit from json file"""
-        self._folder = folder
-        with open(filename, mode="r", encoding="utf-8") as json_file:
-            circuit_dict = json.load(json_file)
-            self.from_dict(circuit_dict, folder)
+        file_dc = CircuitFileDataClass.load(filename)
+        self.from_dataclass(file_dc.circuit, folder)

digsim/circuit/components/_bus_bits.py

@@ -29,7 +29,7 @@ class Bus2Wires(Component):
     def get_parameters(cls):
         return {
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 2,
                 "max": 32,
                 "default": 2,
@@ -59,7 +59,7 @@ class Wires2Bus(Component):
     def get_parameters(cls):
         return {
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 2,
                 "max": 32,
                 "default": 2,

digsim/circuit/components/_buzzer.py

@@ -36,7 +36,7 @@ class Buzzer(CallbackComponent):
     def get_parameters(cls):
         return {
             "tone": {
-                "type": list,
+                "type": "list",
                 "items": ["A", "B", "C", "D", "E", "F", "G"],
                 "default": "A",
                 "description": "Buzzer tone",

digsim/circuit/components/_clock.py

@@ -44,7 +44,7 @@ class Clock(CallbackComponent):
     def get_parameters(cls):
         return {
             "frequency": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 50,
                 "default": 1,

digsim/circuit/components/_dip_switch.py

@@ -64,7 +64,7 @@ class DipSwitch(CallbackComponent):
     def get_parameters(cls):
         return {
             "bits": {
-                "type": int,
+                "type": "int",
                 "min": 2,
                 "max": 8,
                 "default": 8,

digsim/circuit/components/_gates.py

@@ -44,7 +44,7 @@ class ConfigPortsComponent(Component):
     def get_parameters(cls):
         return {
             "ports": {
-                "type": int,
+                "type": "int",
                 "min": 2,
                 "max": 8,
                 "default": 2,
@@ -161,17 +161,17 @@ class DFF(Component):
     def get_parameters(cls):
         return {
             "async_reset": {
-                "type": bool,
+                "type": "bool",
                 "default": False,
                 "description": "Use asynchronous reset",
             },
             "clock_enable": {
-                "type": bool,
+                "type": "bool",
                 "default": False,
                 "description": "Use clock enable",
             },
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 32,
                 "default": 1,
@@ -215,7 +215,7 @@ class MUX(Component):
                 "description": "Number of input ports",
             },
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 32,
                 "default": 1,

digsim/circuit/components/_hexdigit.py

@@ -68,14 +68,14 @@ class HexDigit(CallbackComponent):
     def get_parameters(cls):
         return {
             "digits": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 8,
                 "default": 1,
                 "description": "Number of digits",
             },
             "dot": {
-                "type": bool,
+                "type": "bool",
                 "default": False,
                 "description": "Use decimal dot",
             },

digsim/circuit/components/_label_wire.py

@@ -106,14 +106,14 @@ class LabelWireIn(Component):
 
         return {
             "label": {
-                "type": str,
+                "type": "str",
                 "single_line": True,
                 "default": "WireLabel",
                 "description": "Label name",
                 "invalid_list": label_list,
             },
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 32,
                 "default": 1,
@@ -160,7 +160,7 @@ class LabelWireOut(Component):
 
         return {
             "label": {
-                "type": list,
+                "type": "list",
                 "items": label_list,
                 "description": "Select label",
             }

digsim/circuit/components/_logic_analyzer.py

@@ -50,7 +50,7 @@ class LogicAnalyzer(CallbackComponent):
     def get_parameters(cls):
         return {
             "sample_rate": {
-                "type": int,
+                "type": "int",
                 "min": 10,
                 "max": 100,
                 "default": 20,

digsim/circuit/components/_note.py

@@ -17,7 +17,7 @@ class Note(Component):
     def get_parameters(cls):
         return {
             "text": {
-                "type": str,
+                "type": "str",
                 "default": "Write something here...",
                 "description": "Note text",
                 "reconfigurable": True,

digsim/circuit/components/_static_value.py

@@ -35,7 +35,7 @@ class StaticValue(Component):
                 "reconfigurable": True,
             },
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 16,
                 "default": 1,

digsim/circuit/components/atoms/_component.py

@@ -5,7 +5,6 @@
 
 import abc
 import copy
-import importlib
 
 from ._digsim_exception import DigsimException
 
@@ -166,44 +165,6 @@ class Component(abc.ABC):
             comp_str += f"\n - O:{port.name()}={port.value}"
         return comp_str
 
-    def to_dict(self):
-        """Return the component information as a dict, used when storing a circuit"""
-        component_dict = {
-            "name": self.name(),
-            "display_name": self.display_name(),
-        }
-
-        module_split = type(self).__module__.split(".")
-        type_str = ""
-        for module in module_split:
-            if not module.startswith("_"):
-                type_str += f"{module}."
-        type_str += type(self).__name__
-        component_dict["type"] = type_str
-        component_dict["settings"] = self.settings_to_dict()
-        return component_dict
-
-    @classmethod
-    def from_dict(cls, circuit, json_component):
-        """Factory: Create a component from a dict"""
-        component_name = json_component["name"]
-        component_type = json_component["type"]
-        component_settings = json_component.get("settings", {})
-        if "path" in component_settings:
-            component_settings["path"] = circuit.load_path(component_settings["path"])
-
-        display_name = json_component.get("display_name")
-        py_module_name = ".".join(component_type.split(".")[0:-1])
-        py_class_name = component_type.split(".")[-1]
-
-        module = importlib.import_module(py_module_name)
-        class_ = getattr(module, py_class_name)
-        component = class_(circuit=circuit, **component_settings)
-        component.set_name(component_name)
-        if display_name is not None:
-            component.set_display_name(display_name)
-        return component
-
     @property
     def has_action(self):
         """Return True if this component is interactive"""

digsim/circuit/components/atoms/_port.py

@@ -31,6 +31,11 @@ class Port(abc.ABC):
         self._edge_detect_value = "X"
         self.update_wires("X")
 
+    @property
+    def wired_ports(self):
+        """Get wires from thisport"""
+        return self._wired_ports
+
     @property
     def value(self):
         """Get the value of the port, can be "X" """
@@ -174,20 +179,6 @@ class Port(abc.ABC):
     def __str__(self):
         return f"{self._parent.name()}:{self._name}={self.value}"
 
-    def to_dict_list(self):
-        """Output port connections as a dict, used when storing a circuit"""
-        port_conn_list = []
-        for port in self._wired_ports:
-            # Only add port on top-level components
-            if port.parent().is_toplevel():
-                port_conn_list.append(
-                    {
-                        "src": f"{self.parent().name()}.{self.name()}",
-                        "dst": f"{port.parent().name()}.{port.name()}",
-                    }
-                )
-        return port_conn_list
-
 
 class PortWire(Port):
     """

digsim/storage_model/__init__.py

@@ -0,0 +1,7 @@
+# Copyright (c) Fredrik Andersson, 2024
+# All rights reserved
+
+"""All classes within digsim.storage_model namespace"""
+
+from ._app import AppFileDataClass, GuiPositionDataClass, ModelDataClass
+from ._circuit import CircuitDataClass, CircuitFileDataClass, ComponentDataClass, WireDataClass

digsim/storage_model/_app.py

@@ -0,0 +1,53 @@
+# Copyright (c) Fredrik Andersson, 2023-2024
+# All rights reserved
+
+"""
+Module that handles the dataclasses for application
+"""
+
+from __future__ import annotations
+
+import json
+from dataclasses import asdict
+from typing import Any
+
+from pydantic import Field
+from pydantic.dataclasses import dataclass
+
+from ._circuit import CircuitDataClass
+
+
+@dataclass
+class GuiPositionDataClass:
+    x: int = 100
+    y: int = 100
+    z: int = 0
+
+
+@dataclass
+class AppFileDataClass:
+    circuit: CircuitDataClass
+    gui: dict[str, GuiPositionDataClass] = Field(default_factory=dict)
+    shortcuts: dict[str, str] = Field(default_factory=dict)
+    settings: dict[str, Any] = Field(default_factory=dict)
+
+    @staticmethod
+    def load(filename):
+        with open(filename, mode="r", encoding="utf-8") as json_file:
+            app_filedata_class = AppFileDataClass(**json.load(json_file))
+        return app_filedata_class
+
+    def save(self, filename):
+        json_object = json.dumps(asdict(self), indent=4)
+        with open(filename, mode="w", encoding="utf-8") as json_file:
+            json_file.write(json_object)
+
+
+@dataclass
+class ModelDataClass:
+    circuit: CircuitDataClass
+    gui: dict[str, GuiPositionDataClass]
+
+    @staticmethod
+    def from_app_file_dc(app_file_dc):
+        return ModelDataClass(circuit=app_file_dc.circuit, gui=app_file_dc.gui)

digsim/storage_model/_circuit.py

@@ -0,0 +1,118 @@
+# Copyright (c) Fredrik Andersson, 2023-2024
+# All rights reserved
+
+"""
+Module that handles the dataclasses for circuit load/save
+"""
+
+from __future__ import annotations
+
+import importlib
+import json
+from dataclasses import asdict
+
+from pydantic import Field
+from pydantic.dataclasses import dataclass
+
+
+@dataclass
+class WireDataClass:
+    src: str
+    dst: str
+
+    def connect(self, circuit):
+        src_comp = circuit.get_component(self.src.split(".")[0])
+        dst_comp = circuit.get_component(self.dst.split(".")[0])
+        src_comp.port(self.src.split(".")[1]).wire = dst_comp.port(self.dst.split(".")[1])
+
+    @classmethod
+    def list_from_port(cls, src_port):
+        wires = []
+        for port in src_port.wired_ports:
+            # Only add port on top-level components
+            if port.parent().is_toplevel():
+                wires.append(
+                    WireDataClass(
+                        src=f"{src_port.parent().name()}.{src_port.name()}",
+                        dst=f"{port.parent().name()}.{port.name()}",
+                    )
+                )
+        return wires
+
+
+@dataclass
+class ComponentDataClass:
+    """Component data class"""
+
+    name: str
+    type: str
+    display_name: str = Field(default="")
+    settings: dict = Field(default_factory=dict)
+
+    def create(self, circuit):
+        """Factory: Create a component from a dict"""
+        if "path" in self.settings:
+            self.settings["path"] = circuit.load_path(self.settings["path"])
+
+        py_module_name = ".".join(self.type.split(".")[0:-1])
+        py_class_name = self.type.split(".")[-1]
+
+        module = importlib.import_module(py_module_name)
+        class_ = getattr(module, py_class_name)
+        component = class_(circuit=circuit, **self.settings)
+        component.set_name(self.name)
+        if self.display_name is not None:
+            component.set_display_name(self.display_name)
+        return component
+
+    @staticmethod
+    def from_component(component):
+        """Return the component information as a dict, used when storing a circuit"""
+        module_split = type(component).__module__.split(".")
+        type_str = ""
+        for module in module_split:
+            if not module.startswith("_"):
+                type_str += f"{module}."
+        type_str += type(component).__name__
+
+        return ComponentDataClass(
+            name=component.name(),
+            display_name=component.display_name(),
+            type=type_str,
+            settings=component.settings_to_dict(),
+        )
+
+
+@dataclass
+class CircuitDataClass:
+    name: str = "unnamed"
+    components: list[ComponentDataClass] = Field(default_factory=list)
+    wires: list[WireDataClass] = Field(default_factory=list)
+
+    @staticmethod
+    def from_circuit(circuit):
+        dc = CircuitDataClass(name=circuit.name)
+        for comp in circuit.get_toplevel_components():
+            dc.components.append(ComponentDataClass.from_component(comp))
+
+        for comp in circuit.get_toplevel_components():
+            for port in comp.ports:
+                dc.wires.extend(WireDataClass.list_from_port(port))
+
+        return dc
+
+
+@dataclass
+class CircuitFileDataClass:
+    circuit: CircuitDataClass
+
+    @staticmethod
+    def load(filename):
+        with open(filename, mode="r", encoding="utf-8") as json_file:
+            dc = CircuitFileDataClass(**json.load(json_file))
+        return dc
+
+    def save(self, filename):
+        json_object = json.dumps(asdict(self), indent=4)
+        with open(filename, mode="w", encoding="utf-8") as json_file:
+            json_file.write(json_object)

{digsim_logic_simulator-0.4.0.dist-info → digsim_logic_simulator-0.6.0.dist-info}/LICENSE.md

@@ -1,6 +1,6 @@
 The Clear BSD License
 
-Copyright (c) 2023, Fredrik Andersson
+Copyright (c) 2023-2024, Fredrik Andersson
 All rights reserved.
 
 Redistribution and use in source and binary forms, with or without

{digsim_logic_simulator-0.4.0.dist-info → digsim_logic_simulator-0.6.0.dist-info}/METADATA

@@ -1,12 +1,12 @@
 Metadata-Version: 2.1
 Name: digsim-logic-simulator
-Version: 0.4.0
+Version: 0.6.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>
 License: The Clear BSD License
         
-        Copyright (c) 2023, Fredrik Andersson
+        Copyright (c) 2023-2024, Fredrik Andersson
         All rights reserved.
         
         Redistribution and use in source and binary forms, with or without
@@ -41,20 +41,20 @@ Project-URL: homepage, https://github.com/freand76/digsim
 Keywords: educational,simulation,digital
 Classifier: Development Status :: 5 - Production/Stable
 Classifier: Programming Language :: Python :: 3
-Classifier: Programming Language :: Python :: 3.8
 Classifier: Programming Language :: Python :: 3.9
 Classifier: Programming Language :: Python :: 3.10
 Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3 :: Only
-Requires-Python: >=3.8
+Requires-Python: >=3.9
 Description-Content-Type: text/markdown
 License-File: LICENSE.md
-Requires-Dist: pyvcd >=0.3.0
-Requires-Dist: pyside6 >=6.6.0
-Requires-Dist: pexpect ==4.8.0
+Requires-Dist: pyvcd >=0.4.0
+Requires-Dist: pyside6 <6.8,>=6.7.3
+Requires-Dist: pexpect ==4.9.0
+Requires-Dist: pydantic ==2.9.2
 Requires-Dist: qtawesome
-Requires-Dist: yowasp-yosys ==0.36.0.8.post620
+Requires-Dist: yowasp-yosys ==0.45.0.0.post775
 
 # DigSim - Interactive Digital Logic Simulator
 
@@ -135,6 +135,11 @@ Then the following package must be installed:
 > gtkwave sr.vcd
 ```
 
+### Examples of writing pytest/python test benches for synthesized verilog code
+```
+> pytest examples/pytest_tb
+```
+
 ## Yosys synthesis helper tool
 
 ```

{digsim_logic_simulator-0.4.0.dist-info → digsim_logic_simulator-0.6.0.dist-info}/RECORD

@@ -11,7 +11,7 @@ digsim/app/gui_objects/__init__.py,sha256=DV7hnqz4Xcwk_-BiKrPxB31c7k-R4Oemmo_KOU
 digsim/app/gui_objects/_bus_bit_object.py,sha256=Q8oW-bAGLRAvR2-8PxyHL4M68FLKFgNpDiL4E7BPUOQ,3059
 digsim/app/gui_objects/_buzzer_object.py,sha256=p_7O361t98K6BIUxK6gHdfcSn2wUVXTRfnf7oQXSIK4,3352
 digsim/app/gui_objects/_component_context_menu.py,sha256=57M23M8Xb4t8eN8l9GQQ4AUBYZlEBjE0_a4d71yCDos,2821
-digsim/app/gui_objects/_component_object.py,sha256=NIszLF61tjwyKYzQQby6BXP3rU7d1cj5VxZp-SY6LgY,13078
+digsim/app/gui_objects/_component_object.py,sha256=7fIvnMfew7cwyfk9m6nMnha6df5NEH67bc2-K5lg7lE,13142
 digsim/app/gui_objects/_component_port_item.py,sha256=Rxl952_3BCqM2H7TJDfbSTlalfFicDStrjqMUKEtdns,2089
 digsim/app/gui_objects/_dip_switch_object.py,sha256=6SmqoyF3MuUphLJA4tlyff4JXJBxJLWmt3ZEferFtf4,3576
 digsim/app/gui_objects/_gui_note_object.py,sha256=sMakGjdR0truGBzaR2GaFZZoDg99v76Bs5DD6ea3cjA,2604
@@ -49,54 +49,57 @@ digsim/app/gui_objects/images/YOSYS.png,sha256=etTO9jadU0amxQG7ySRjD6fME4HjrEEqX
 digsim/app/gui_objects/images/ZERO.png,sha256=hXnZgEVO3T_zN5CiFhu6cIXr19LAu6SdvX-sIOq06E4,3459
 digsim/app/images/app_icon.png,sha256=OfPoYA4o4Af79DTqQxSNLca0FdXRHEYteBK-xCQFEAw,16041
 digsim/app/model/__init__.py,sha256=atbReJBH_qTVZqsKLvF3p9eZWxkglFi6cvt7fEGo0bo,159
-digsim/app/model/_model.py,sha256=7zkn3i2YSFp-lhhsxGxyac0wv-PkjbZrjgKNz933iLc,6506
-digsim/app/model/_model_components.py,sha256=8x96YmkeHEaBYaB5i88G_Zf9MHcc05g8Go_YEBJ3R_o,6500
+digsim/app/model/_model.py,sha256=JE9-iJMxzgcY0r-4s708gDtA-aadw_hFSuERjKNZlfE,6421
+digsim/app/model/_model_components.py,sha256=Q2iztl7MlWv_7vaa7me-dp-gOx6-7Tg3LZmTUQNBPrw,6371
 digsim/app/model/_model_new_wire.py,sha256=5HnF5-gtKtB1Tp6ZIF7QuNo5zEHmsUpnBEmj6ZllLiA,1810
-digsim/app/model/_model_objects.py,sha256=M3UxXqjqVg1PIDe96_3SH0L_BJGQEIvODa0XyUI7q4g,5040
-digsim/app/model/_model_settings.py,sha256=3nKzdhaSwYogC10-IFyNzbCsvXbmy9lrZ7hb_yRCyLg,1141
-digsim/app/model/_model_shortcuts.py,sha256=ovZ2uJC0rRYaLgf6UStPd4P33CiphvRmIOYx6c7M89M,2511
+digsim/app/model/_model_objects.py,sha256=lqOjNIygIHT6Dq_PPa-D0B5elC49dB0KshF0ATzJZ0s,5217
+digsim/app/model/_model_settings.py,sha256=FewI3hm1iwbjPwdN3IeixuINPtamDORrTh1ANGRNwX8,1035
+digsim/app/model/_model_shortcuts.py,sha256=TT4osN7-dMEgKXWHW9cJ0XILIIkUfRqBBfx6rvYT2JI,2488
 digsim/app/settings/__init__.py,sha256=0tkoBSYeJFFiUI8c_FqvqqyM4-_SU9Xq7mXCwiew5Oo,308
-digsim/app/settings/_component_settings.py,sha256=3kOh_q0I01h9yUHLcoDkGcgJtfO64zemToyH7fIGwZo,16279
+digsim/app/settings/_component_settings.py,sha256=88D9OuEcFIlaqZozomWHSYrl7opz4jZW2e8xGuUyTpg,16287
 digsim/app/settings/_gui_settings.py,sha256=sDi2POUsHvS7_4SO5qsTu_nN48HsTN4UfGPzdmECs9w,2764
 digsim/app/settings/_shortcut_dialog.py,sha256=JTm7aawG2ar_DvWhBT8ZzgWsq9gLEJ6pJ_-eHUMPh-c,1524
 digsim/circuit/__init__.py,sha256=yGyhcdnlcpht_hyR2az_A4c7-bO_NkT2lBIDFvtI010,216
-digsim/circuit/_circuit.py,sha256=hj0D6NMnAi39USIyZsBp6Nd8ktrqpjNW9cO3JVd1Wbw,11748
+digsim/circuit/_circuit.py,sha256=UNJBM2MyTXPWWEPXe4T4Z9Qc6vsm9We_Rk7mEfV9yIA,10023
 digsim/circuit/_waves_writer.py,sha256=hh-hwNrT9c0jDLLxYw0anvwomJXVJK5iIbGVjcQddG0,1645
 digsim/circuit/components/__init__.py,sha256=j-xNFbXJ15rSJLhDg7E-SlKvxn6Uy7Zl42YDUkZBFZo,1267
-digsim/circuit/components/_bus_bits.py,sha256=0AvvteRnG4SpW_l-0e-cgBG85VxYlbfdVQFvQVSp88Y,1912
+digsim/circuit/components/_bus_bits.py,sha256=mHWkwAHtkEq88pOEQ0b5ndFZvum794j7kUkTAWHUCdc,1916
 digsim/circuit/components/_button.py,sha256=Q8drjQ2kNFCfgK-7UzlmNHP47bOpGa9_t16pDtjhL4s,1028
-digsim/circuit/components/_buzzer.py,sha256=bJXMfJyZo66ZiUs_4qT5MyNEHof5ZCI0cIBrdeFdTfA,1123
-digsim/circuit/components/_clock.py,sha256=Mw2R6tHmPAS5-ueiFkZPwYmgPMAg_slAOWiMDimiWGQ,1485
-digsim/circuit/components/_dip_switch.py,sha256=55IfnZrQr-Ru_ncWvFdDeiGwfC8dc1xqmF4ReQBI-TI,1805
+digsim/circuit/components/_buzzer.py,sha256=vArzQVe0yFjtqMxIx2BIvjRA-m-aipPUHVlgwbwpCXM,1125
+digsim/circuit/components/_clock.py,sha256=Kks82_Ni_XJYvrgLFvPsAagbUnmH9QutGuwm1puM0B0,1487
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 digsim/circuit/components/_flip_flops.py,sha256=eOB1hpSfK7vlpcOQzHqILpAzfwsqQPobC-_ebDxGVLw,2942
-digsim/circuit/components/_gates.py,sha256=QcsNUINdtLQyLt1pcXTmCks9x2mi1-db7VVLNZTIYZ4,7157
-digsim/circuit/components/_hexdigit.py,sha256=9ir8EGEB10mQbpDa5Jxff4EIdLzQ1_dw-KB_vBamcEA,2255
+digsim/circuit/components/_gates.py,sha256=K_aFT4GTo4JF_zoaNYiCRZfZEx4vEibMHZSCDImfPHQ,7167
+digsim/circuit/components/_hexdigit.py,sha256=MQlmEnQkQnuH6rGc-FB68mOctjVY8QyAR5FCOHYNCns,2259
 digsim/circuit/components/_ic.py,sha256=Rs8Z_PuhKo3peK9pwdbvlGNK8_w6evSdXYNdrjWB3-8,917
-digsim/circuit/components/_label_wire.py,sha256=cd4FFERz_PngKGfbK3YwOQcHmCbasiX-JH73TvkT-wU,5110
+digsim/circuit/components/_label_wire.py,sha256=5xcPNWt8GtQEUk_BDJXWHQ3RfH62bAFQpiyeJlppOpA,5116
 digsim/circuit/components/_led.py,sha256=hR_iclDWZua8duNy9BQcTBuhKkIh3g5ahpfkHQ1LYSA,452
-digsim/circuit/components/_logic_analyzer.py,sha256=MHkXGmQuXnDVJonxVkeZy9JOVmsapdT3voi6tsdZcbQ,1807
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 digsim/circuit/components/_mem64kbyte.py,sha256=tqex3qFxa7jk841f87inNB4UIY9E5z1SleqAL82eCUY,1482
 digsim/circuit/components/_memstdout.py,sha256=sCYkKH8XuWhB7-14VQOy7TkTgq-g0UDbhiI1HmM4HW8,1255
-digsim/circuit/components/_note.py,sha256=4o4bRw_7smKc_FGrVkhPwwIqC_500Vj_w8TrNtK1A8s,602
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 digsim/circuit/components/_on_off_switch.py,sha256=b2h_EClKRbOQTBpQYrOLRXzdps8da64lO9Nd7fp1RSY,1200
 digsim/circuit/components/_seven_segment.py,sha256=UxxjGLuIirVB2Px09XlL8_zjgE7F89cY6z2SMS5FcPU,797
 digsim/circuit/components/_static_level.py,sha256=2Assm1cmAfryVZ3KTQ1uGY8Q6eRrBipdwLITewXfIHg,677
-digsim/circuit/components/_static_value.py,sha256=HNTsvjx0dsK8o4-tBLux3v57RZ425CcnpNmVS5B2CHw,1234
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 digsim/circuit/components/_yosys_atoms.py,sha256=NeH8XjjpoACHBfQRqR5RJxWorZhSjGk0t73cJOviSZw,37599
 digsim/circuit/components/_yosys_component.py,sha256=XDNSAfM6Qvhe6G0-M1uiY2NQ-A6oPSQX4kcB_ccvSWg,8810
 digsim/circuit/components/atoms/__init__.py,sha256=kPr-ZKYPiW8NgEvKooMyLYc4DpfMurkALqWcKLhuK28,483
-digsim/circuit/components/atoms/_component.py,sha256=x0e2NUi9ozV4keuT10tsK9MqwBF8Vg1uInvadoS4DiE,9824
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 digsim/circuit/components/atoms/_digsim_exception.py,sha256=Y5mBve15zZbduqNNAyf7WzqDk4NtvUL_g2vYy5kBQ3U,173
-digsim/circuit/components/atoms/_port.py,sha256=VYtKglAPJxaXG7ucTRNay_GS4aVX02gsqlJecNs1xlM,12119
+digsim/circuit/components/atoms/_port.py,sha256=BzfCBSQT34AMH10PyAj-eg0UqQpvFJz01fd3HmCwHhE,11688
 digsim/circuit/components/ic/74162.json,sha256=BtLDDhNP4jYQD2EZ2nBHfUMRbuPztR54luLEpWl7j-o,26632
 digsim/circuit/components/ic/7448.json,sha256=7p9l6l_QSw6DtphZcGgBMMP0PyMB5DYglciMhqCKp04,21211
+digsim/storage_model/__init__.py,sha256=lubmO9_BCUtEahyW1yE7f3aGHngEevGIwf_0LeOB7Y8,289
+digsim/storage_model/_app.py,sha256=Aer9s_mUBKSydsyeWYvVPHX2XF5ZGPuXq8z4PoXu8lA,1353
+digsim/storage_model/_circuit.py,sha256=NnaHLwqb9gAhqAxeZ1RkHHvoS_YJwixlz0xs-zmIrQU,3596
 digsim/synth/__init__.py,sha256=jhBHLOHf-vNa94Zg5q5dGcf0fgQTModfjUKtmUSffiw,180
 digsim/synth/__main__.py,sha256=wZWAzWsisoxA7hfqkKtu3H066uWyFajgPro2MEGlKbs,2173
 digsim/synth/_synthesis.py,sha256=ug9vSeTyZrvRCboNLL7dDIFVpGqH_ibr5fhOZJHpqUs,4271
 digsim/utils/__init__.py,sha256=Az_zmbORYMzmptuA2_xfn5jDxbCPRSMlVuntr0sYexU,167
 digsim/utils/_yosys_netlist.py,sha256=g-7hkVgGOYJUQbKv8wBqHMHqj44utuGHGbtaRb-qG60,8562
-digsim_logic_simulator-0.4.0.dist-info/LICENSE.md,sha256=nx2x6ryeruncSHeHtF33WLjt5JARcm5rLdZuK_c8hL0,1688
-digsim_logic_simulator-0.4.0.dist-info/METADATA,sha256=l5jm-fI-iCGARKme6DBniaEXzUe73czseQVFwPuApg8,6336
-digsim_logic_simulator-0.4.0.dist-info/WHEEL,sha256=GJ7t_kWBFywbagK5eo9IoUwLW6oyOeTKmQ-9iHFVNxQ,92
-digsim_logic_simulator-0.4.0.dist-info/top_level.txt,sha256=qpCMzQKADZHVqZIoQgFrv3qJ3u7PPU73gTCXQglqLa8,7
-digsim_logic_simulator-0.4.0.dist-info/RECORD,,
+digsim_logic_simulator-0.6.0.dist-info/LICENSE.md,sha256=FrvohZfyfpH4xrvKdXiQ5hD7dUB7w4DcsRA3p-pOmLw,1693
+digsim_logic_simulator-0.6.0.dist-info/METADATA,sha256=-Gakjy1u6-q6HFTAz49L5u2HuH5Vw3EwxvUlnc2JfdA,6445
+digsim_logic_simulator-0.6.0.dist-info/WHEEL,sha256=GV9aMThwP_4oNCtvEC2ec3qUYutgWeAzklro_0m4WJQ,91
+digsim_logic_simulator-0.6.0.dist-info/top_level.txt,sha256=qpCMzQKADZHVqZIoQgFrv3qJ3u7PPU73gTCXQglqLa8,7
+digsim_logic_simulator-0.6.0.dist-info/RECORD,,

{digsim_logic_simulator-0.4.0.dist-info → digsim_logic_simulator-0.6.0.dist-info}/WHEEL

@@ -1,5 +1,5 @@
 Wheel-Version: 1.0
-Generator: bdist_wheel (0.43.0)
+Generator: setuptools (75.1.0)
 Root-Is-Purelib: true
 Tag: py3-none-any