digsim-logic-simulator 0.12.0__py3-none-any.whl → 0.14.0__py3-none-any.whl

digsim/circuit/components/atoms/_port.py

@@ -6,10 +6,14 @@
 from __future__ import annotations
 
 import abc
+from typing import Literal, Optional, Union
 
 from ._digsim_exception import DigsimException
 
 
+VALUE_TYPE = Union[int, Literal["X"]]
+
+
 class PortConnectionError(DigsimException):
     """Exception for illegal connections"""
 
@@ -23,8 +27,8 @@ class Port(abc.ABC):
         self._width: int = width  # The bit-width of this port
         self._output: bool = output  # Is this port an output port
         self._wired_ports: list[Port] = []  # The ports that this port drives
-        self._value: int | str | None = None  # The value of this port
-        self._edge_detect_value: int | str | None = "X"  # Last edge detect value
+        self._value: VALUE_TYPE = "X"  # The value of this port
+        self._edge_detect_value: VALUE_TYPE = "X"  # Last edge detect value
         self.init()  # Initialize the port
 
     def init(self):
@@ -39,12 +43,12 @@ class Port(abc.ABC):
         return self._wired_ports
 
     @property
-    def value(self) -> int | str | None:
+    def value(self) -> VALUE_TYPE:
         """Get the value of the port, can be "X" """
         return self._value
 
     @value.setter
-    def value(self, value: int | str | None):
+    def value(self, value: VALUE_TYPE):
         """Set the value of the port"""
         self.set_value(value)
 
@@ -60,7 +64,7 @@ class Port(abc.ABC):
             driver = self.get_driver()
             if driver is not None:
                 driver.disconnect(self)
-            for port in self._wired_ports:
+            for port in self._wired_ports[:]:
                 self.disconnect(port)
         self._width = width
 
@@ -98,7 +102,7 @@ class Port(abc.ABC):
         """Get parent component"""
         return self._parent
 
-    def update_wires(self, value: int | str | None):
+    def update_wires(self, value: VALUE_TYPE):
         """Update connected wires (and self._value) with value"""
         if self._value == value:
             return
@@ -106,11 +110,21 @@ class Port(abc.ABC):
         for port in self._wired_ports:
             port.value = self._value
 
-    def get_wired_ports_recursive(self) -> list[Port]:
-        """Get all connected ports (recursive)"""
-        all_wired_ports = [self]
-        for port in self._wired_ports:
-            all_wired_ports.extend(port.get_wired_ports_recursive())
+    def get_wired_ports_recursive(self, processed_ports: Optional[set] = None) -> list[Port]:
+        """Get all connected ports (iterative), avoiding duplicates."""
+        if processed_ports is None:
+            processed_ports = set()
+
+        all_wired_ports = []
+        ports_to_process = [self]
+
+        while ports_to_process:
+            port = ports_to_process.pop()
+            if port in processed_ports:
+                continue
+            processed_ports.add(port)
+            all_wired_ports.append(port)
+            ports_to_process.extend(port.wired_ports)
         return all_wired_ports
 
     def is_output(self) -> bool:
@@ -144,7 +158,7 @@ class Port(abc.ABC):
         return falling_edge
 
     @abc.abstractmethod
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         """Set value on port"""
 
     @abc.abstractmethod
@@ -195,7 +209,7 @@ class PortWire(Port):
         super().__init__(parent, name, width, output)
         self._port_driver: Port | None = None  # The port that drives this port
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         if value != self.value:
             self.update_wires(value)
 
@@ -221,7 +235,7 @@ class PortIn(PortWire):
     def __init__(self, parent, name: str, width: int = 1):
         super().__init__(parent, name, width, output=False)
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         super().set_value(value)
         self.parent().update()
 
@@ -246,16 +260,16 @@ class PortOutDelta(Port):
         """Set port propagation delay"""
         self._delay_ns = delay_ns
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         self.parent().add_event(self, value, self._delay_ns)
 
-    def update_port(self, value: int | str | None):
+    def update_port(self, value: VALUE_TYPE):
         """Update the port output and the connected wires"""
         self.update_wires(value)
         if self._update_parent:
             self.parent().update()
 
-    def delta_cycle(self, value: int | str | None):
+    def delta_cycle(self, value: VALUE_TYPE):
         """Handle the delta cycle event from the circuit"""
         self.update_port(value)
 
@@ -282,11 +296,11 @@ class PortOutImmediate(PortOutDelta):
     def __init__(self, parent, name: str, width: int = 1):
         super().__init__(parent, name, width)
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         self.parent().add_event(self, value, 0)
         super().update_port(value)
 
-    def delta_cycle(self, value: int | str | None):
+    def delta_cycle(self, value: VALUE_TYPE):
         """
         Do nothing here, the event is just used to updates waves in Circuit class
         """
@@ -303,7 +317,7 @@ class PortWireBit(PortWire):
         super().__init__(parent, name, 1, output)
         self._parent_port = parent_port
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         super().set_value(value)
         self._parent_port.update_value_from_bits()
 
@@ -333,17 +347,20 @@ class PortMultiBitWire(Port):
         for bit in self._bits:
             bit.init()
 
-    def set_value(self, value: int | str | None):
-        if value is None or isinstance(value, str):
+    def set_value(self, value: VALUE_TYPE):
+        if isinstance(value, str):
             return
         for bit_id, bit in enumerate(self._bits):
             bit_val = (value >> bit_id) & 1
             bit.value = bit_val
 
-    def get_wired_ports_recursive(self) -> list[Port]:
-        all_wired_ports = super().get_wired_ports_recursive()
+    def get_wired_ports_recursive(self, processed_ports: Optional[set] = None) -> list[Port]:
+        if processed_ports is None:
+            processed_ports = set()
+
+        all_wired_ports = super().get_wired_ports_recursive(processed_ports)
         for bit in self._bits:
-            all_wired_ports.extend(bit.get_wired_ports_recursive())
+            all_wired_ports.extend(bit.get_wired_ports_recursive(processed_ports))
         return all_wired_ports
 
     def set_driver(self, port: Port | None):
@@ -364,18 +381,17 @@ class PortMultiBitWire(Port):
 
     def update_value_from_bits(self):
         """Update the port with the value of the bits"""
-        for bit in self._bits:
+        value = 0
+        for bit_id, bit in enumerate(self._bits):
             if bit.value == "X":
                 self.update_wires("X")
                 return
-        value = 0
-        for bit_id, bit in enumerate(self._bits):
             value = value | (bit.value << bit_id)
         self.update_wires(value)
         # Send event just to update waves
         self.parent().add_event(self, value, 0)
 
-    def delta_cycle(self, value: int | str | None):
+    def delta_cycle(self, value: VALUE_TYPE):
         """
         Do nothing here, the event passed in 'update_value_from_bits'
         is just used to updates waves in Circuit class

digsim/storage_model/_app.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023-2024
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """
@@ -33,8 +33,13 @@ class AppFileDataClass:
 
     @staticmethod
     def load(filename):
-        with open(filename, mode="r", encoding="utf-8") as json_file:
-            app_filedata_class = AppFileDataClass(**json.load(json_file))
+        try:
+            with open(filename, mode="r", encoding="utf-8") as json_file:
+                app_filedata_class = AppFileDataClass(**json.load(json_file))
+        except json.JSONDecodeError as exc:
+            raise ValueError(f"Malformed JSON file: {filename} - {exc}") from exc
+        except FileNotFoundError as exc:
+            raise FileNotFoundError(f"File not found: {filename}") from exc
         return app_filedata_class
 
     def save(self, filename):

digsim/storage_model/_circuit.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023-2024
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """
@@ -21,9 +21,11 @@ class WireDataClass:
     dst: str
 
     def connect(self, circuit):
-        src_comp = circuit.get_component(self.src.split(".")[0])
-        dst_comp = circuit.get_component(self.dst.split(".")[0])
-        src_comp.port(self.src.split(".")[1]).wire = dst_comp.port(self.dst.split(".")[1])
+        src_comp_name, src_port_name = self.src.split(".")
+        dst_comp_name, dst_port_name = self.dst.split(".")
+        src_comp = circuit.get_component(src_comp_name)
+        dst_comp = circuit.get_component(dst_comp_name)
+        src_comp.port(src_port_name).wire = dst_comp.port(dst_port_name)
 
     @classmethod
     def list_from_port(cls, src_port):
@@ -92,10 +94,11 @@ class CircuitDataClass:
     @staticmethod
     def from_circuit(circuit):
         dc = CircuitDataClass(name=circuit.name)
-        for comp in circuit.get_toplevel_components():
+        toplevel_components = circuit.get_toplevel_components()
+        for comp in toplevel_components:
             dc.components.append(ComponentDataClass.from_component(comp))
 
-        for comp in circuit.get_toplevel_components():
+        for comp in toplevel_components:
             for port in comp.ports:
                 dc.wires.extend(WireDataClass.list_from_port(port))
 
@@ -108,8 +111,13 @@ class CircuitFileDataClass:
 
     @staticmethod
     def load(filename):
-        with open(filename, mode="r", encoding="utf-8") as json_file:
-            dc = CircuitFileDataClass(**json.load(json_file))
+        try:
+            with open(filename, mode="r", encoding="utf-8") as json_file:
+                dc = CircuitFileDataClass(**json.load(json_file))
+        except json.JSONDecodeError as exc:
+            raise ValueError(f"Malformed JSON file: {filename} - {exc}") from exc
+        except FileNotFoundError as exc:
+            raise FileNotFoundError(f"File not found: {filename}") from exc
         return dc
 
     def save(self, filename):

digsim/synth/__init__.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """All classes within digsim.synth namespace"""

digsim/synth/__main__.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """The main class module of the digsim.synth namespace"""
@@ -45,7 +45,7 @@ if __name__ == "__main__":
     subparser = parser.add_subparsers(required=True)
     synth_parser = subparser.add_parser("synth")
     synth_parser.add_argument(
-        "--input-files", "-i", type=str, nargs="*", required=True, help="The verilog input files"
+        "--input-files", "-i", type=str, nargs="+", required=True, help="The verilog input files"
     )
     synth_parser.add_argument(
         "--output-file", "-o", type=str, required=True, help="The json output file"
@@ -59,7 +59,7 @@ if __name__ == "__main__":
     synth_parser.set_defaults(func=_synth_modules)
     list_parser = subparser.add_parser("list")
     list_parser.add_argument(
-        "--input-files", "-i", type=str, nargs="*", required=True, help="The verilog input files"
+        "--input-files", "-i", type=str, nargs="+", required=True, help="The verilog input files"
     )
     list_parser.set_defaults(func=_list_modules)
     arguments = parser.parse_args()

digsim/synth/_synthesis.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """Helper module for yosys synthesis"""
@@ -116,7 +116,7 @@ class Synthesis:
         script += "proc; flatten; "
         script += "memory_dff; "
         script += "proc; opt; techmap; opt; "
-        script += f"synth -top {self._verilog_top_module}; "
+        script += f"synth -noabc -top {self._verilog_top_module}; "
 
         pexp = self._pexpect_spawn_yosys()
         self._pexpect_wait_for_prompt(pexp)
@@ -137,7 +137,10 @@ class Synthesis:
     def synth_to_dict(self, silent=False):
         """Execute yosys with generated synthesis script and return python dict"""
         yosys_json = self.synth_to_json(silent)
-        netlist_dict = json.loads(yosys_json)
+        try:
+            netlist_dict = json.loads(yosys_json)
+        except json.JSONDecodeError as exc:
+            raise SynthesisException(f"Malformed JSON output from Yosys: {exc}") from exc
         return netlist_dict
 
     def synth_to_json_file(self, filename, silent=False):

digsim/utils/__init__.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """All classes within digsim.utils namespace"""

digsim/utils/_yosys_netlist.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """
@@ -7,12 +7,15 @@ Module with classes to parse a yosys netlist
 
 from __future__ import annotations
 
-from typing import Any, Optional, Union
+from typing import Any, Literal, Optional, Union
 
 from pydantic import Field
 from pydantic.dataclasses import dataclass
 
 
+BIT_TYPE = list[Union[int, Literal["X"], Literal["0"], Literal["1"]]]
+
+
 @dataclass
 class NetPort:
     parent: Union[YosysModule, YosysCell]
@@ -30,7 +33,7 @@ class Nets:
 @dataclass
 class YosysPort:
     direction: str
-    bits: list[Union[int, str]]
+    bits: BIT_TYPE
 
     @property
     def is_output(self):
@@ -46,13 +49,16 @@ class YosysPort:
 class YosysCell:
     type: str
     port_directions: dict[str, str] = Field(default_factory=dict)
-    connections: dict[str, list[Union[str, int]]] = Field(default_factory=dict)
+    connections: dict[str, BIT_TYPE] = Field(default_factory=dict)
     hide_name: int = 0
     parameters: dict[str, Any] = Field(default_factory=dict)
     attributes: dict[str, Any] = Field(default_factory=dict)
 
     def get_nets(self, name, nets):
         for port_name, net_list in self.connections.items():
+            if not net_list:
+                # Handle empty net_list, e.g., by skipping or raising an error
+                continue
             net = net_list[0]
             port = NetPort(parent=self, parent_name=name, name=port_name)
             if self.port_directions[port_name] == "input":

{digsim_logic_simulator-0.12.0.dist-info → digsim_logic_simulator-0.14.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: digsim-logic-simulator
-Version: 0.12.0
+Version: 0.14.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>
@@ -8,21 +8,20 @@ Project-URL: homepage, https://github.com/freand76/digsim
 Keywords: educational,simulation,digital
 Classifier: Development Status :: 5 - Production/Stable
 Classifier: Programming Language :: Python :: 3
-Classifier: Programming Language :: Python :: 3.9
 Classifier: Programming Language :: Python :: 3.10
 Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3.13
 Classifier: Programming Language :: Python :: 3 :: Only
-Requires-Python: >=3.9
+Requires-Python: >=3.10
 Description-Content-Type: text/markdown
 License-File: LICENSE.md
 Requires-Dist: pyvcd==0.4.1
 Requires-Dist: pyside6==6.9.1
 Requires-Dist: pexpect==4.9.0
-Requires-Dist: pydantic==2.11.7
+Requires-Dist: pydantic==2.12.3
 Requires-Dist: qtawesome==1.4.0
-Requires-Dist: yowasp-yosys==0.57.0.0.post986
+Requires-Dist: yowasp-yosys==0.58.0.0.post1010
 Dynamic: license-file
 
 # DigSim - Interactive Digital Logic Simulator

digsim_logic_simulator-0.14.0.dist-info/RECORD

@@ -0,0 +1,105 @@
+digsim/__init__.py,sha256=cPP3o3Poil_rxQh3syOJd0MuqU4sPnudjaesG18GF8E,154
+digsim/app/__main__.py,sha256=0Cw_kzox6oDRO2cOS4Q6_g6TlThpUTfJNnaAfaJXxsg,1516
+digsim/app/gui/__init__.py,sha256=jLV8w5SIh4PadWA3UDnLk2strI3_xEIfQEt5Sb62YUc,170
+digsim/app/gui/_circuit_area.py,sha256=zwQ2tVujriY2DdQI4Jy7anebh0Ul5od99HDDphZQTdo,16590
+digsim/app/gui/_component_selection.py,sha256=LTVSA3xd85jqULn6GfrBnmfDeP_iYlj4_UjKUd_4FHQ,6590
+digsim/app/gui/_main_window.py,sha256=4lTQLYNGg_PNJlGSJqaQKZ7RbpUq71x9O0FUKnP-rAo,5275
+digsim/app/gui/_top_bar.py,sha256=JSP-aF5oFZ-1uHA5SNyRThpHLs9YVnTPA65h2EhxCN4,13067
+digsim/app/gui/_utils.py,sha256=GMPIucfMQhXGwX91CGmeoRpxS8qwOfDLUI76fPJWk0I,665
+digsim/app/gui/_warning_dialog.py,sha256=N9G2wyQTyiqMnTtbExMzHgdbCBA0epfhNWY4GVF6xH8,1496
+digsim/app/gui_objects/__init__.py,sha256=VYR64j5VX8yavCXoPGtPMS4mJpJR6NSRxvXPuSdxFX0,248
+digsim/app/gui_objects/_bus_bit_object.py,sha256=qKZg1SLds9LNq3DUTR7dtM_3gosrfhENopKd0gpqTMY,3059
+digsim/app/gui_objects/_buzzer_object.py,sha256=f-Kgrf5r5iUZMHXy2kmzxDDA0ROMPAPNJbguMSrdEu4,3294
+digsim/app/gui_objects/_component_context_menu.py,sha256=pPhvNYO5lR6J61_NKJt5HPBRiypSuMAIcbcWoZU4DIA,2824
+digsim/app/gui_objects/_component_object.py,sha256=ntD34AEqaJovzDYMrlxOrdyjqprPU_urWUbznnBQNTM,13323
+digsim/app/gui_objects/_component_port_item.py,sha256=_28fqR0MAvKiD51qK7P1K-DSgHzg3r1SGydr0Og2ZbU,2046
+digsim/app/gui_objects/_dip_switch_object.py,sha256=8-YJdkcg0UXxbkxmyq4Ep4ZezZOkxCw6tfQ5Yq3mOlE,3636
+digsim/app/gui_objects/_gui_note_object.py,sha256=qPB0OBq6jxKlqH8yoV2wchDFqrJdjB3AP993hDj1Kcs,2592
+digsim/app/gui_objects/_gui_object_factory.py,sha256=T9TeQVh-DHbOwnn2BtwI0gxnubgp0vUmT36O0b1grLk,2466
+digsim/app/gui_objects/_hexdigit_object.py,sha256=0psnY8dMVZwGmoQeETbhgwilJOyjF8eqx2zaVwdWqVY,1935
+digsim/app/gui_objects/_image_objects.py,sha256=WsWesxfRbGO1cSbXD7nikw7E-gx8A-af458Q52xk0dU,7677
+digsim/app/gui_objects/_label_object.py,sha256=DrmgWW5ACJksd2P3lUUog7CRBj7RWzCkTfvhb6LQCxM,3585
+digsim/app/gui_objects/_logic_analyzer_object.py,sha256=WK-EsthfXzfDDnGA8-wgq_7RhuKwdyQ_KWdXitov-Zk,3078
+digsim/app/gui_objects/_seven_segment_object.py,sha256=KpCOQNmSQ5EX_WRbTACawfNo5fCZ4aWyZTcU_5yy6r0,4370
+digsim/app/gui_objects/_shortcut_objects.py,sha256=8gKAAlv0AlBowDp726EsDBxj1KSwSJne74_bqz0jh08,2747
+digsim/app/gui_objects/_yosys_object.py,sha256=iq8Zmw4tV_sJuULcKEu7mvvK_m19m2ymypLqCawnCyI,958
+digsim/app/gui_objects/images/AND.png,sha256=d53gEcxIlfqmW-Q4Za3n5i_NmSEcjJqlbh8XxoSdR3o,12062
+digsim/app/gui_objects/images/Analyzer.png,sha256=1OrkKsL6ktxKI12KzNJT7rgEi2X-jAqp6vrVuVthErY,1591
+digsim/app/gui_objects/images/BUF.png,sha256=fd8DqEM3aht4cjoWuqsbHlTiQaFa9ddibe3iel1WYLo,12819
+digsim/app/gui_objects/images/Buzzer.png,sha256=sdAQehr03pEpQXrm2RTqUqDpUI15WU1ohFf4fB90uvI,5856
+digsim/app/gui_objects/images/Clock.png,sha256=NAsu1IKb2tiZ_oFs3C7t7Wzc3xzq-1PBLVm7NcT9whQ,3117
+digsim/app/gui_objects/images/DFF.png,sha256=OalrTM4XbMouEeB0xXg8nPy3gZzMxwnvgtF149XsTl0,9038
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+digsim/app/gui_objects/images/FlipFlop.png,sha256=PLCMrH0CBXU6jgDTPpGsgEAqmgNN3c5hvU1sjZzOU40,4452
+digsim/app/gui_objects/images/IC.png,sha256=7YoAkD_5CrTIdmArjD_HjZyT9odAYuCwufDDpVC3Jsw,5493
+digsim/app/gui_objects/images/LED_OFF.png,sha256=bk-X-R-l8CvdD-xat0zI5pc9S1t6j0Ewx4G_vMt1sRE,7075
+digsim/app/gui_objects/images/LED_ON.png,sha256=YSYDNx8zjFoqEy9kuognaL8eL0acuVHV7b4ArlK_ol4,9389
+digsim/app/gui_objects/images/MUX.png,sha256=d8Q0qUJIRCdFQbxAg_sc4MJG3F6QRTbCT4ysgkCm6DE,1912
+digsim/app/gui_objects/images/NAND.png,sha256=W-dZPNg2Qh0M-FkA8Gbblh42EvMKtBI37IenZKDIbLE,11718
+digsim/app/gui_objects/images/NOR.png,sha256=eFaignMSIiUPJnc8VkIQ9Yg1iF6qVjrM9sA50EGqp9g,15091
+digsim/app/gui_objects/images/NOT.png,sha256=V1QoUHpBbEX2Tish4DIe_wImAVj-M9DL5QrNIKNo-nQ,12593
+digsim/app/gui_objects/images/ONE.png,sha256=ftnpl7_gMTLc08k08Ka_QfnLv5H1u5AhPitZNPe_42E,1212
+digsim/app/gui_objects/images/OR.png,sha256=54lsnUphLRwY9ioOOqAsRW0KRVTNOHZOPBKosXUTAOc,14870
+digsim/app/gui_objects/images/PB.png,sha256=bhnhD-Ood9hSBFr-aia2iCPT_Q7VYBaEq076sqU3DBY,8468
+digsim/app/gui_objects/images/Switch_OFF.png,sha256=ta11PvVIajT2gugj_SPK3mLn9_WaluqAK3t4aks9a-8,4752
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