digsim-logic-simulator 0.12.0__py3-none-any.whl → 0.13.0__py3-none-any.whl

digsim/app/settings/_component_settings.py

@@ -271,7 +271,7 @@ class ComponentSettingsCheckBoxWidthBool(ComponentSettingsBase):
             checkbox = QCheckBox(f"bit{checkbox_id}")
             checkbox.setChecked(True)
             checkbox.stateChanged.connect(self._update)
-            self.layout().addWidget(checkbox, checkbox_id % 8, checkbox_id / 8, 1, 1)
+            self.layout().addWidget(checkbox, checkbox_id % 8, checkbox_id // 8, 1, 1)
             self._bit_checkboxes.append(checkbox)
         disable_all = QPushButton("Disable All")
         disable_all.clicked.connect(self._disable_all)

digsim/app/settings/_shortcut_dialog.py

@@ -20,12 +20,11 @@ class ShortcutDialog(QDialog):
         self.layout().addWidget(QLabel("Select shortcut key for component"))
         self._key_selector = QComboBox(parent)
         for key in "1234567890":
-            shortcut_key = str(key)
-            shortcut_string = shortcut_key
-            shortcut_component = app_model.shortcuts.get_component(shortcut_key)
+            shortcut_string = key
+            shortcut_component = app_model.shortcuts.get_component(key)
             if shortcut_component is not None:
                 shortcut_string += f" - {shortcut_component.name()}"
-            self._key_selector.addItem(shortcut_string, userData=shortcut_key)
+            self._key_selector.addItem(shortcut_string, userData=key)
         self.layout().addWidget(self._key_selector)
         self.buttonBox = QDialogButtonBox(QDialogButtonBox.Ok | QDialogButtonBox.Cancel)
         self.buttonBox.accepted.connect(self.accept)

digsim/circuit/_circuit.py

@@ -7,13 +7,14 @@ Module that handles the circuit simulation of components
 
 from __future__ import annotations
 
-import os
+import heapq
+import pathlib
 from typing import Tuple
 
 from digsim.storage_model import CircuitDataClass, CircuitFileDataClass
 
 from ._waves_writer import WavesWriter
-from .components.atoms import Component, DigsimException, PortOutDelta
+from .components.atoms import VALUE_TYPE, Component, DigsimException, PortOutDelta
 
 
 class CircuitError(DigsimException):
@@ -26,10 +27,10 @@ class CircuitEvent:
     delta events in the simulation.
     """
 
-    def __init__(self, time_ns: int, port: PortOutDelta, value: int | str | None):
+    def __init__(self, time_ns: int, port: PortOutDelta, value: VALUE_TYPE):
         self._time_ns: int = time_ns
         self._port: PortOutDelta = port
-        self._value: int | str | None = value
+        self._value: VALUE_TYPE = value
 
     @property
     def time_ns(self) -> int:
@@ -42,7 +43,7 @@ class CircuitEvent:
         return self._port
 
     @property
-    def value(self) -> int | str | None:
+    def value(self) -> VALUE_TYPE:
         """Get the delta cycle value of this event"""
         return self._value
 
@@ -50,7 +51,7 @@ class CircuitEvent:
         """Return True if the in the event is the same as"""
         return port == self._port
 
-    def update(self, time_ns: int, value: int | str | None):
+    def update(self, time_ns: int, value: VALUE_TYPE):
         """Update the event with a new time (ns) and a new value"""
         self._time_ns = time_ns
         self._value = value
@@ -58,6 +59,14 @@ class CircuitEvent:
     def __lt__(self, other) -> bool:
         return other.time_ns > self.time_ns
 
+    def __eq__(self, other) -> bool:
+        return (
+            isinstance(other, CircuitEvent)
+            and self._port == other._port
+            and self._time_ns == other._time_ns
+            and self._value == other._value
+        )
+
 
 class Circuit:
     """Class thay handles the circuit simulation"""
@@ -65,6 +74,7 @@ class Circuit:
     def __init__(self, name: str | None = None, vcd: str | None = None):
         self._components: dict[str, Component] = {}
         self._circuit_events: list[CircuitEvent] = []
+        self._events_by_port: dict[PortOutDelta, CircuitEvent] = {}
         self._name: str | None = name
         self._time_ns: int = 0
         self._folder: str | None = None
@@ -86,10 +96,7 @@ class Circuit:
     @property
     def components(self) -> list[Component]:
         """Get the components in this circuit"""
-        comp_array = []
-        for _, comp in self._components.items():
-            comp_array.append(comp)
-        return comp_array
+        return list(self._components.values())
 
     def load_path(self, path) -> str:
         """Get the load path relative to the circuit path"""
@@ -100,7 +107,9 @@ class Circuit:
     def store_path(self, path) -> str:
         """Get the store path relative to the circuit path"""
         if self._folder is not None:
-            return os.path.relpath(path, self._folder)
+            return str(
+                pathlib.Path(path).resolve().absolute().relative_to(pathlib.Path(self._folder))
+            )
         return path
 
     def delete_component(self, component: Component):
@@ -110,16 +119,13 @@ class Circuit:
 
     def get_toplevel_components(self) -> list[Component]:
         """Get toplevel components in the circuit"""
-        toplevel_components = []
-        for _, comp in self._components.items():
-            if comp.is_toplevel():
-                toplevel_components.append(comp)
-        return toplevel_components
+        return [comp for comp in self._components.values() if comp.is_toplevel()]
 
     def init(self):
         """Initialize circuit and components (and ports)"""
         self._time_ns = 0
         self._circuit_events = []
+        self._events_by_port = {}
         if self._vcd is not None:
             self._vcd_init()
         for _, comp in self._components.items():
@@ -175,22 +181,32 @@ class Circuit:
         Process one simulation event
         Return False if ther are now events of if the stop_time has passed
         """
-        if len(self._circuit_events) == 0:
-            return False, False
-        self._circuit_events.sort()
-        if stop_time_ns is None or self._circuit_events[0].time_ns > stop_time_ns:
-            return False, False
-        event = self._circuit_events.pop(0)
-        # print(
-        #     f"Execute event {event.port.path()}.{event.port.name()}"
-        #     " {event.time_ns} {event.value}"
-        # )
-        self._time_ns = event.time_ns
-        event.port.delta_cycle(event.value)
-        toplevel = event.port.parent().is_toplevel()
-        if self._vcd is not None:
-            self._vcd.write(event.port, self._time_ns)
-        return True, toplevel
+        while self._circuit_events:
+            event = heapq.heappop(self._circuit_events)
+
+            # Check if this is the latest event for this port
+            if event != self._events_by_port.get(event.port):
+                # This is a stale event, ignore it
+                continue
+
+            if stop_time_ns is not None and event.time_ns > stop_time_ns:
+                # Put the event back if it's after the stop time
+                heapq.heappush(self._circuit_events, event)
+                return False, False
+
+            del self._events_by_port[event.port]
+            # print(
+            #     f"Execute event {event.port.path()}.{event.port.name()}"
+            #     f" {event.time_ns} {event.value}"
+            # )
+            self._time_ns = event.time_ns
+            event.port.delta_cycle(event.value)
+            toplevel = event.port.parent().is_toplevel()
+            if self._vcd is not None:
+                self._vcd.write(event.port, self._time_ns)
+            return True, toplevel
+
+        return False, False
 
     def _is_toplevel_event(self) -> bool:
         if len(self._circuit_events) == 0:
@@ -231,15 +247,13 @@ class Circuit:
         if stop_time_ns >= self._time_ns:
             self.run(ns=stop_time_ns - self._time_ns)
 
-    def add_event(self, port: PortOutDelta, value: int | str | None, propagation_delay_ns: int):
+    def add_event(self, port: PortOutDelta, value: VALUE_TYPE, propagation_delay_ns: int):
         """Add delta cycle event, this will also write values to .vcd file"""
         event_time_ns = self._time_ns + propagation_delay_ns
         # print(f"Add event {port.parent().name()}:{port.name()} => {value}")
-        for event in self._circuit_events:
-            if event.is_same_event(port):
-                event.update(event_time_ns, value)
-                return
-        self._circuit_events.append(CircuitEvent(event_time_ns, port, value))
+        event = CircuitEvent(event_time_ns, port, value)
+        self._events_by_port[port] = event
+        heapq.heappush(self._circuit_events, event)
 
     def add_component(self, component: Component):
         """Add component to circuit"""

digsim/circuit/components/_button.py

@@ -3,21 +3,17 @@
 
 """A PushButton component"""
 
-import logging
-
 from .atoms import CallbackComponent, PortOutImmediate
 
 
 class PushButton(CallbackComponent):
     """PushButton component class"""
 
-    def __init__(self, circuit, name=None, inverted=False):
+    def __init__(self, circuit, name=None):
         super().__init__(circuit, name)
         portout = PortOutImmediate(self, "O")
         self.add_port(portout)
         portout.update_parent(True)
-        if inverted:
-            logging.warning("Setting 'inverted' has been removed")
 
     def default_state(self):
         self.release()

digsim/circuit/components/_yosys_component.py

@@ -26,7 +26,7 @@ class YosysComponent(MultiComponent):
     def __init__(self, circuit, path=None, name=None, nets=True):
         super().__init__(circuit, name)
         self._circuit = circuit
-        self._path = path
+        self._path = str(path)
         self._gates_comp = None
         self._net_comp = None
         self._netlist_module = None

digsim/circuit/components/atoms/__init__.py

@@ -11,6 +11,7 @@ from ._component import (  # noqa: F401
 )
 from ._digsim_exception import DigsimException  # noqa: F401
 from ._port import (  # noqa: F401
+    VALUE_TYPE,
     Port,
     PortConnectionError,
     PortIn,

digsim/circuit/components/atoms/_component.py

@@ -63,10 +63,20 @@ class Component(abc.ABC):
         self._ports = []
 
     def path(self) -> str:
-        """Get component path"""
-        if self._parent is not None:
-            return f"{self._parent.path()}.{self.name()}"
-        return f"{self.name()}"
+        """Get component path (iterative)"""
+        path_parts = []
+        current_component = self
+        while current_component is not None:
+            name = current_component.name()
+            if not isinstance(name, str):
+                raise TypeError(
+                    f"Component name is not a string: "
+                    f"{name} ({type(name)}), "
+                    f"component: {current_component.__class__.__name__}"
+                )
+            path_parts.append(name)
+            current_component = current_component._parent
+        return ".".join(reversed(path_parts))
 
     @property
     def ports(self):

digsim/circuit/components/atoms/_port.py

@@ -6,10 +6,14 @@
 from __future__ import annotations
 
 import abc
+from typing import Literal, Optional, Union
 
 from ._digsim_exception import DigsimException
 
 
+VALUE_TYPE = Union[int, Literal["X"]]
+
+
 class PortConnectionError(DigsimException):
     """Exception for illegal connections"""
 
@@ -23,8 +27,8 @@ class Port(abc.ABC):
         self._width: int = width  # The bit-width of this port
         self._output: bool = output  # Is this port an output port
         self._wired_ports: list[Port] = []  # The ports that this port drives
-        self._value: int | str | None = None  # The value of this port
-        self._edge_detect_value: int | str | None = "X"  # Last edge detect value
+        self._value: VALUE_TYPE = "X"  # The value of this port
+        self._edge_detect_value: VALUE_TYPE = "X"  # Last edge detect value
         self.init()  # Initialize the port
 
     def init(self):
@@ -39,12 +43,12 @@ class Port(abc.ABC):
         return self._wired_ports
 
     @property
-    def value(self) -> int | str | None:
+    def value(self) -> VALUE_TYPE:
         """Get the value of the port, can be "X" """
         return self._value
 
     @value.setter
-    def value(self, value: int | str | None):
+    def value(self, value: VALUE_TYPE):
         """Set the value of the port"""
         self.set_value(value)
 
@@ -60,7 +64,7 @@ class Port(abc.ABC):
             driver = self.get_driver()
             if driver is not None:
                 driver.disconnect(self)
-            for port in self._wired_ports:
+            for port in self._wired_ports[:]:
                 self.disconnect(port)
         self._width = width
 
@@ -98,7 +102,7 @@ class Port(abc.ABC):
         """Get parent component"""
         return self._parent
 
-    def update_wires(self, value: int | str | None):
+    def update_wires(self, value: VALUE_TYPE):
         """Update connected wires (and self._value) with value"""
         if self._value == value:
             return
@@ -106,11 +110,21 @@ class Port(abc.ABC):
         for port in self._wired_ports:
             port.value = self._value
 
-    def get_wired_ports_recursive(self) -> list[Port]:
-        """Get all connected ports (recursive)"""
-        all_wired_ports = [self]
-        for port in self._wired_ports:
-            all_wired_ports.extend(port.get_wired_ports_recursive())
+    def get_wired_ports_recursive(self, processed_ports: Optional[set] = None) -> list[Port]:
+        """Get all connected ports (iterative), avoiding duplicates."""
+        if processed_ports is None:
+            processed_ports = set()
+
+        all_wired_ports = []
+        ports_to_process = [self]
+
+        while ports_to_process:
+            port = ports_to_process.pop()
+            if port in processed_ports:
+                continue
+            processed_ports.add(port)
+            all_wired_ports.append(port)
+            ports_to_process.extend(port.wired_ports)
         return all_wired_ports
 
     def is_output(self) -> bool:
@@ -144,7 +158,7 @@ class Port(abc.ABC):
         return falling_edge
 
     @abc.abstractmethod
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         """Set value on port"""
 
     @abc.abstractmethod
@@ -195,7 +209,7 @@ class PortWire(Port):
         super().__init__(parent, name, width, output)
         self._port_driver: Port | None = None  # The port that drives this port
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         if value != self.value:
             self.update_wires(value)
 
@@ -221,7 +235,7 @@ class PortIn(PortWire):
     def __init__(self, parent, name: str, width: int = 1):
         super().__init__(parent, name, width, output=False)
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         super().set_value(value)
         self.parent().update()
 
@@ -246,16 +260,16 @@ class PortOutDelta(Port):
         """Set port propagation delay"""
         self._delay_ns = delay_ns
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         self.parent().add_event(self, value, self._delay_ns)
 
-    def update_port(self, value: int | str | None):
+    def update_port(self, value: VALUE_TYPE):
         """Update the port output and the connected wires"""
         self.update_wires(value)
         if self._update_parent:
             self.parent().update()
 
-    def delta_cycle(self, value: int | str | None):
+    def delta_cycle(self, value: VALUE_TYPE):
         """Handle the delta cycle event from the circuit"""
         self.update_port(value)
 
@@ -282,11 +296,11 @@ class PortOutImmediate(PortOutDelta):
     def __init__(self, parent, name: str, width: int = 1):
         super().__init__(parent, name, width)
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         self.parent().add_event(self, value, 0)
         super().update_port(value)
 
-    def delta_cycle(self, value: int | str | None):
+    def delta_cycle(self, value: VALUE_TYPE):
         """
         Do nothing here, the event is just used to updates waves in Circuit class
         """
@@ -303,7 +317,7 @@ class PortWireBit(PortWire):
         super().__init__(parent, name, 1, output)
         self._parent_port = parent_port
 
-    def set_value(self, value: int | str | None):
+    def set_value(self, value: VALUE_TYPE):
         super().set_value(value)
         self._parent_port.update_value_from_bits()
 
@@ -333,17 +347,20 @@ class PortMultiBitWire(Port):
         for bit in self._bits:
             bit.init()
 
-    def set_value(self, value: int | str | None):
-        if value is None or isinstance(value, str):
+    def set_value(self, value: VALUE_TYPE):
+        if isinstance(value, str):
             return
         for bit_id, bit in enumerate(self._bits):
             bit_val = (value >> bit_id) & 1
             bit.value = bit_val
 
-    def get_wired_ports_recursive(self) -> list[Port]:
-        all_wired_ports = super().get_wired_ports_recursive()
+    def get_wired_ports_recursive(self, processed_ports: Optional[set] = None) -> list[Port]:
+        if processed_ports is None:
+            processed_ports = set()
+
+        all_wired_ports = super().get_wired_ports_recursive(processed_ports)
         for bit in self._bits:
-            all_wired_ports.extend(bit.get_wired_ports_recursive())
+            all_wired_ports.extend(bit.get_wired_ports_recursive(processed_ports))
         return all_wired_ports
 
     def set_driver(self, port: Port | None):
@@ -364,18 +381,17 @@ class PortMultiBitWire(Port):
 
     def update_value_from_bits(self):
         """Update the port with the value of the bits"""
-        for bit in self._bits:
+        value = 0
+        for bit_id, bit in enumerate(self._bits):
             if bit.value == "X":
                 self.update_wires("X")
                 return
-        value = 0
-        for bit_id, bit in enumerate(self._bits):
             value = value | (bit.value << bit_id)
         self.update_wires(value)
         # Send event just to update waves
         self.parent().add_event(self, value, 0)
 
-    def delta_cycle(self, value: int | str | None):
+    def delta_cycle(self, value: VALUE_TYPE):
         """
         Do nothing here, the event passed in 'update_value_from_bits'
         is just used to updates waves in Circuit class

digsim/storage_model/_app.py

@@ -33,8 +33,13 @@ class AppFileDataClass:
 
     @staticmethod
     def load(filename):
-        with open(filename, mode="r", encoding="utf-8") as json_file:
-            app_filedata_class = AppFileDataClass(**json.load(json_file))
+        try:
+            with open(filename, mode="r", encoding="utf-8") as json_file:
+                app_filedata_class = AppFileDataClass(**json.load(json_file))
+        except json.JSONDecodeError as exc:
+            raise ValueError(f"Malformed JSON file: {filename} - {exc}") from exc
+        except FileNotFoundError as exc:
+            raise FileNotFoundError(f"File not found: {filename}") from exc
         return app_filedata_class
 
     def save(self, filename):

digsim/storage_model/_circuit.py

@@ -21,9 +21,11 @@ class WireDataClass:
     dst: str
 
     def connect(self, circuit):
-        src_comp = circuit.get_component(self.src.split(".")[0])
-        dst_comp = circuit.get_component(self.dst.split(".")[0])
-        src_comp.port(self.src.split(".")[1]).wire = dst_comp.port(self.dst.split(".")[1])
+        src_comp_name, src_port_name = self.src.split(".")
+        dst_comp_name, dst_port_name = self.dst.split(".")
+        src_comp = circuit.get_component(src_comp_name)
+        dst_comp = circuit.get_component(dst_comp_name)
+        src_comp.port(src_port_name).wire = dst_comp.port(dst_port_name)
 
     @classmethod
     def list_from_port(cls, src_port):
@@ -92,10 +94,11 @@ class CircuitDataClass:
     @staticmethod
     def from_circuit(circuit):
         dc = CircuitDataClass(name=circuit.name)
-        for comp in circuit.get_toplevel_components():
+        toplevel_components = circuit.get_toplevel_components()
+        for comp in toplevel_components:
             dc.components.append(ComponentDataClass.from_component(comp))
 
-        for comp in circuit.get_toplevel_components():
+        for comp in toplevel_components:
             for port in comp.ports:
                 dc.wires.extend(WireDataClass.list_from_port(port))
 
@@ -108,8 +111,13 @@ class CircuitFileDataClass:
 
     @staticmethod
     def load(filename):
-        with open(filename, mode="r", encoding="utf-8") as json_file:
-            dc = CircuitFileDataClass(**json.load(json_file))
+        try:
+            with open(filename, mode="r", encoding="utf-8") as json_file:
+                dc = CircuitFileDataClass(**json.load(json_file))
+        except json.JSONDecodeError as exc:
+            raise ValueError(f"Malformed JSON file: {filename} - {exc}") from exc
+        except FileNotFoundError as exc:
+            raise FileNotFoundError(f"File not found: {filename}") from exc
         return dc
 
     def save(self, filename):

digsim/synth/__main__.py

@@ -45,7 +45,7 @@ if __name__ == "__main__":
     subparser = parser.add_subparsers(required=True)
     synth_parser = subparser.add_parser("synth")
     synth_parser.add_argument(
-        "--input-files", "-i", type=str, nargs="*", required=True, help="The verilog input files"
+        "--input-files", "-i", type=str, nargs="+", required=True, help="The verilog input files"
     )
     synth_parser.add_argument(
         "--output-file", "-o", type=str, required=True, help="The json output file"
@@ -59,7 +59,7 @@ if __name__ == "__main__":
     synth_parser.set_defaults(func=_synth_modules)
     list_parser = subparser.add_parser("list")
     list_parser.add_argument(
-        "--input-files", "-i", type=str, nargs="*", required=True, help="The verilog input files"
+        "--input-files", "-i", type=str, nargs="+", required=True, help="The verilog input files"
     )
     list_parser.set_defaults(func=_list_modules)
     arguments = parser.parse_args()

digsim/synth/_synthesis.py

@@ -137,7 +137,10 @@ class Synthesis:
     def synth_to_dict(self, silent=False):
         """Execute yosys with generated synthesis script and return python dict"""
         yosys_json = self.synth_to_json(silent)
-        netlist_dict = json.loads(yosys_json)
+        try:
+            netlist_dict = json.loads(yosys_json)
+        except json.JSONDecodeError as exc:
+            raise SynthesisException(f"Malformed JSON output from Yosys: {exc}") from exc
         return netlist_dict
 
     def synth_to_json_file(self, filename, silent=False):

digsim/utils/_yosys_netlist.py

@@ -7,12 +7,15 @@ Module with classes to parse a yosys netlist
 
 from __future__ import annotations
 
-from typing import Any, Optional, Union
+from typing import Any, Literal, Optional, Union
 
 from pydantic import Field
 from pydantic.dataclasses import dataclass
 
 
+BIT_TYPE = list[Union[int, Literal["X"], Literal["0"], Literal["1"]]]
+
+
 @dataclass
 class NetPort:
     parent: Union[YosysModule, YosysCell]
@@ -30,7 +33,7 @@ class Nets:
 @dataclass
 class YosysPort:
     direction: str
-    bits: list[Union[int, str]]
+    bits: BIT_TYPE
 
     @property
     def is_output(self):
@@ -46,13 +49,16 @@ class YosysPort:
 class YosysCell:
     type: str
     port_directions: dict[str, str] = Field(default_factory=dict)
-    connections: dict[str, list[Union[str, int]]] = Field(default_factory=dict)
+    connections: dict[str, BIT_TYPE] = Field(default_factory=dict)
     hide_name: int = 0
     parameters: dict[str, Any] = Field(default_factory=dict)
     attributes: dict[str, Any] = Field(default_factory=dict)
 
     def get_nets(self, name, nets):
         for port_name, net_list in self.connections.items():
+            if not net_list:
+                # Handle empty net_list, e.g., by skipping or raising an error
+                continue
             net = net_list[0]
             port = NetPort(parent=self, parent_name=name, name=port_name)
             if self.port_directions[port_name] == "input":

{digsim_logic_simulator-0.12.0.dist-info → digsim_logic_simulator-0.13.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: digsim-logic-simulator
-Version: 0.12.0
+Version: 0.13.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>