digsim-logic-simulator 0.0.1__py3-none-any.whl → 0.1.0__py3-none-any.whl

digsim/app/__main__.py

@@ -4,8 +4,8 @@
 """ The main class module of the digsim.app namespace """
 
 import argparse
-import os
 import sys
+from pathlib import Path
 
 from PySide6.QtCore import Qt
 from PySide6.QtGui import QIcon, QPainter, QPixmap
@@ -17,7 +17,8 @@ from digsim.app.model import AppModel
 
 if __name__ == "__main__":
     app = QApplication(sys.argv)
-    image_path = f"{os.path.dirname(__file__)}/images/app_icon.png"
+    main_path = Path(__file__).parent
+    image_path = main_path / "images/app_icon.png"
     image_pixmap = QPixmap(image_path)
     size = max(image_pixmap.size().height(), image_pixmap.size().width())
     icon_pixmap = QPixmap(size, size)

digsim/app/gui/_top_bar.py

@@ -6,7 +6,7 @@
 # pylint: disable=too-few-public-methods
 # pylint: disable=too-many-instance-attributes
 
-import os
+from pathlib import Path
 
 import qtawesome as qta
 
@@ -182,7 +182,7 @@ class VcdControlWidget(QFrame):
 
     def _start_vcd(self, filename):
         self._vcd_filename = filename
-        display_filename = os.path.basename(self._vcd_filename)
+        display_filename = Path(self._vcd_filename).name
         self._filename_widget.set_filename(display_filename)
         self._enable_buttons(True)
         # Close old vcd (if any)

digsim/app/gui_objects/_image_objects.py

@@ -5,7 +5,7 @@
 
 # pylint: disable=too-many-arguments
 
-import os
+from pathlib import Path
 
 from PySide6.QtCore import QPoint, Qt
 from PySide6.QtGui import QFont, QPen, QPixmap
@@ -45,11 +45,9 @@ class ImageObject(ComponentObject):
     def _get_pixmaps(cls):
         """Load the pixmap at first use"""
         if cls.ACTIVE_IMAGE_FILENAME is not None and cls._pixmap_active is None:
-            cls._pixmap_active = QPixmap(
-                f"{os.path.dirname(__file__)}/{cls.ACTIVE_IMAGE_FILENAME}"
-            )
+            cls._pixmap_active = QPixmap(Path(__file__).parent / cls.ACTIVE_IMAGE_FILENAME)
         if cls.IMAGE_FILENAME is not None and cls._pixmap is None:
-            cls._pixmap = QPixmap(f"{os.path.dirname(__file__)}/{cls.IMAGE_FILENAME}")
+            cls._pixmap = QPixmap(Path(__file__).parent / cls.IMAGE_FILENAME)
 
     def paint_component(self, painter):
         self.paint_component_base(painter)

digsim/app/gui_objects/_yosys_object.py

@@ -5,6 +5,8 @@
 
 from PySide6.QtGui import QAction
 
+from digsim.circuit.components.atoms import DigsimException
+
 from ._image_objects import ImageObject
 
 
@@ -23,5 +25,8 @@ class YosysObject(ImageObject):
         reloadAction.triggered.connect(self._reload)
 
     def _reload(self):
-        self.component.reload_file()
+        try:
+            self.component.reload_file()
+        except DigsimException as exc:
+            self._app_model.sig_warning_log.emit("Reload Yosys Warning", str(exc))
         self._app_model.model_reset()

digsim/app/model/_model.py

@@ -6,9 +6,9 @@
 # pylint: disable=too-many-instance-attributes
 
 import json
-import os
 import queue
 import time
+from pathlib import Path
 
 from PySide6.QtCore import QThread, Signal
 
@@ -156,7 +156,7 @@ class AppModel(QThread):
 
     def save_circuit(self, path):
         """Save the circuit with GUI information"""
-        circuit_folder = os.path.dirname(path)
+        circuit_folder = str(Path(path).parent)
         circuit_dict = self.objects.circuit_to_dict(circuit_folder)
         shortcuts_dict = self.shortcuts.to_dict()
         circuit_dict.update(shortcuts_dict)
@@ -173,7 +173,7 @@ class AppModel(QThread):
         self._model_clear()
         with open(path, mode="r", encoding="utf-8") as json_file:
             circuit_dict = json.load(json_file)
-        circuit_folder = os.path.dirname(path)
+        circuit_folder = str(Path(path).parent)
         if len(circuit_folder) == 0:
             circuit_folder = "."
         exception_str_list = self.objects.dict_to_circuit(circuit_dict, circuit_folder)

digsim/circuit/components/_button.py

@@ -3,6 +3,8 @@
 
 """ A PushButton component """
 
+import logging
+
 from .atoms import CallbackComponent, PortOutImmediate
 
 
@@ -14,24 +16,19 @@ class PushButton(CallbackComponent):
         portout = PortOutImmediate(self, "O")
         self.add_port(portout)
         portout.update_parent(True)
-        self.parameter_set("inverted", inverted)
+        if inverted:
+            logging.warning("Setting 'inverted' has been removed")
 
     def default_state(self):
         self.release()
 
     def push(self):
         """Push pushbutton"""
-        if self.parameter_get("inverted"):
-            self.O.value = 0
-        else:
-            self.O.value = 1
+        self.O.value = 1
 
     def release(self):
         """Release pushbutton"""
-        if self.parameter_get("inverted"):
-            self.O.value = 1
-        else:
-            self.O.value = 0
+        self.O.value = 0
 
     def reconfigure(self):
         self.release()
@@ -49,14 +46,3 @@ class PushButton(CallbackComponent):
 
     def onrelease(self):
         self.release()
-
-    @classmethod
-    def get_parameters(cls):
-        return {
-            "inverted": {
-                "type": bool,
-                "default": False,
-                "description": "Button output is inverted",
-                "reconfigurable": True,
-            },
-        }

digsim/circuit/components/_gates.py

@@ -231,18 +231,18 @@ class SR(MultiComponent):
 
     def __init__(self, circuit, name=None):
         super().__init__(circuit, name)
-        _nands = NAND(circuit)
-        _nandr = NAND(circuit)
+        _nands = NOR(circuit)
+        _nandr = NOR(circuit)
         self.add(_nands)
         self.add(_nandr)
         _nands.Y.wire = _nandr.A
         _nandr.Y.wire = _nands.B
-        self.add_port(PortWire(self, "nS"))
-        self.add_port(PortWire(self, "nR"))
+        self.add_port(PortWire(self, "S"))
+        self.add_port(PortWire(self, "R"))
         self.add_port(PortWire(self, "Q"))
         self.add_port(PortWire(self, "nQ"))
 
-        self.nS.wire = _nands.A
-        self.nR.wire = _nandr.B
-        _nands.Y.wire = self.Q
-        _nandr.Y.wire = self.nQ
+        self.S.wire = _nands.A
+        self.R.wire = _nandr.B
+        _nands.Y.wire = self.nQ
+        _nandr.Y.wire = self.Q

digsim/circuit/components/_hexdigit.py

@@ -30,7 +30,7 @@ class HexDigit(CallbackComponent):
 
     def __init__(self, circuit, name=None, digits=1, dot=True):
         super().__init__(circuit, name)
-        self.add_port(PortIn(self, "val", width=(4 * digits)))
+        self.add_port(PortIn(self, "val", width=4 * digits))
         self.parameter_set("digits", digits)
         self.parameter_set("dot", dot)
         if dot:

digsim/circuit/components/_ic.py

@@ -4,7 +4,7 @@
 """
 Module for creating a yosys component in the ic folder
 """
-import os
+from pathlib import Path
 
 from ._yosys_component import YosysComponent
 
@@ -20,7 +20,7 @@ class IntegratedCircuit(YosysComponent):
     @classmethod
     def folder(cls):
         """Get predefined IC folder"""
-        return f"{os.path.dirname(__file__)}/ic"
+        return str(Path(__file__).parent / "ic")
 
     def settings_to_dict(self):
         return {"ic_name": self.parameter_get("ic_name")}

digsim/circuit/components/_on_off_switch.py

@@ -3,6 +3,8 @@
 
 """ An On/Off Switch  component """
 
+import logging
+
 from .atoms import CallbackComponent, PortOutDelta
 
 
@@ -14,17 +16,18 @@ class OnOffSwitch(CallbackComponent):
         portout = PortOutDelta(self, "O", delay_ns=0)
         self.add_port(portout)
         portout.update_parent(True)
-        self.parameter_set("start_on", start_on)
-        self._on = start_on
+        self._on = False
+        if start_on:
+            logging.warning("Setting 'start_on' has been removed")
 
-    def _set(self, set_on):
-        if set_on:
-            self.turn_on()
-        else:
-            self.turn_off()
+    def _set(self, state):
+        self._on = state
+        self.O.value = 1 if state else 0
 
     def default_state(self):
-        self._set(self.parameter_get("start_on"))
+        self._set(False)
+
+        self.turn_off()
 
     def turn_on(self):
         """Turn on the switch"""
@@ -33,8 +36,7 @@ class OnOffSwitch(CallbackComponent):
 
     def turn_off(self):
         """Turn off the switch"""
-        self.O.value = 0
-        self._on = False
+        self._set(False)
 
     def toggle(self):
         """Toggle the switch"""
@@ -50,14 +52,3 @@ class OnOffSwitch(CallbackComponent):
     @property
     def active(self):
         return self._on
-
-    @classmethod
-    def get_parameters(cls):
-        return {
-            "start_on": {
-                "type": bool,
-                "default": False,
-                "description": "Switch on after reset",
-                "reconfigurable": True,
-            },
-        }

digsim/circuit/components/_yosys_atoms.py

@@ -39,7 +39,7 @@ class ClassNameParameterComponent(Component):
             return 0
         if level in ["P", "1"]:
             return 1
-        raise Exception(f"Unknown value ä{level}'")
+        raise ValueError(f"Unknown value ä{level}'")
 
 
 class _BUF_(Component):

digsim/circuit/components/_yosys_component.py

@@ -10,8 +10,8 @@ from a yosys json netlist.
 # pylint: disable=too-many-instance-attributes
 
 import json
-import os
 import tempfile
+from pathlib import Path
 
 import digsim.circuit.components._yosys_atoms
 from digsim.synth import Synthesis
@@ -171,8 +171,8 @@ class YosysComponent(MultiComponent):
         with tempfile.NamedTemporaryFile(delete=False) as tmp_file:
             filename = tmp_file.name
         synthesis = Synthesis(self._path, filename, toplevel)
-        if not synthesis.execute():
-            raise YosysComponentException("Yosys synthesis error")
+        if not synthesis.execute(silent=True):
+            raise YosysComponentException(f"Yosys synthesis error {self._path}")
         return filename
 
     def _load_netlist_dict(self):
@@ -190,7 +190,7 @@ class YosysComponent(MultiComponent):
             netlist_dict = json.load(json_file)
 
         if unlink_file:
-            os.unlink(filename)
+            Path(filename).unlink()
 
         yosys_netlist = YosysNetlist()
         yosys_netlist.from_dict(netlist_dict)

digsim/synth/__init__.py

@@ -3,4 +3,4 @@
 
 """ All classes within digsim.synth namespace """
 
-from ._synthesis import Synthesis  # noqa: F401
+from ._synthesis import Synthesis, SynthesisException  # noqa: F401

digsim/synth/_synthesis.py

@@ -3,12 +3,14 @@
 
 """Helper module for yosys synthesis"""
 
-import os
 import subprocess
 import tempfile
+from pathlib import Path
 
+from digsim.circuit.components.atoms import DigsimException
 
-class SynthesisException(Exception):
+
+class SynthesisException(DigsimException):
     """Exception class for yosys synthesis"""
 
 
@@ -30,20 +32,34 @@ class Synthesis:
             stream.write("ls\n")
             stream.flush()
 
+        success = False
         with subprocess.Popen(
             ["yosys", script_file], stdout=subprocess.PIPE, stdin=None
         ) as process:
             modules = []
             ls_output_found = False
+            modules_done = False
             while process.poll() is None:
                 line = process.stdout.readline().decode("utf-8").rstrip()
+                if modules_done:
+                    continue
                 if "modules:" in line:
                     ls_output_found = True
-                if ls_output_found and "$abstract" in line:
+                    continue
+                if ls_output_found:
+                    if len(line) == 0:
+                        modules_done = True
+                        continue
                     modules.append(line.replace("$abstract\\", "").strip())
-            if process.returncode != 0:
-                raise SynthesisException("Yosys execution failed...")
-        os.unlink(script_file)
+            success = process.returncode == 0
+        Path(script_file).unlink()
+        if not success:
+            files_str = ""
+            for verilog_file in verilog_files:
+                if len(files_str) > 0:
+                    files_str += ", "
+                files_str += Path(verilog_file).name
+            raise SynthesisException(f"Yosys error for {files_str}")
         return modules
 
     def __init__(self, verilog_files, json_output_file, verilog_top_module):
@@ -83,7 +99,7 @@ class Synthesis:
                 if not silent:
                     print("Yosys: ", line)
             success = process.returncode == 0
-        os.unlink(script_file)
+        Path(script_file).unlink()
         return success
 
     def get_log(self):

{digsim_logic_simulator-0.0.1.dist-info → digsim_logic_simulator-0.1.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: digsim-logic-simulator
-Version: 0.0.1
+Version: 0.1.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>
@@ -57,6 +57,8 @@ Requires-Dist: qtawesome
 # DigSim - Interactive Digital Logic Simulator
 
 ![Python Version from PEP 621 TOML](https://img.shields.io/python/required-version-toml?tomlFilePath=https%3A%2F%2Fraw.githubusercontent.com%2Ffreand76%2Fdigsim%2Fmain%2Fpyproject.toml)
+![PyPI - Version](https://img.shields.io/pypi/v/digsim-logic-simulator)
+![PyPI - Downloads](https://img.shields.io/pypi/dm/digsim-logic-simulator)
 
 <p align="center">
   <img alt="The DigSim Application" src="https://raw.githubusercontent.com/freand76/digsim/af1bf95eb16d1af19f26159a4c1e1b88565703d7/docs/images/screenshot_digsim_app.png" width=85%>
@@ -83,7 +85,12 @@ and even if it is slower than many other simulators it is not entirely useless.
 
 ## Quickstart
 
-### Install
+### Install from PyPi
+```
+pip3 install digsim-logic-simulator
+```
+
+### Install from GitHub
 ```
 > git clone https://github.com/freand76/digsim.git
 > cd digsim
@@ -110,12 +117,12 @@ Then the following package must be installed:
 > apt install libxcb-cursor0
 ```
 
-### Start with example circuit
+### Start with example circuit (example circuits are available in the github repository)
 ```
 > python3 -m digsim.app --load example_circuits/counter_yosys_netlist.circuit
 ```
 
-### Run example
+### Run example (examples are available in the github repository)
 ```
 > python3 examples/example_sr.py
 ```
@@ -133,6 +140,10 @@ Then the following package must be installed:
 > python3 -m digsim.synth synth -i <verilog file 1> <optional verilog file 2> -o <output_file.json> -t <verilog top_module>
 ```
 
+## Documentation
+
+[Documentation](https://github.com/freand76/digsim/blob/main/docs/documentation.md) on GitHub
+
 ## Star History
 
 [![Star History Chart](https://api.star-history.com/svg?repos=freand76/digsim&type=Date)](https://star-history.com/#freand76/digsim&Date)

{digsim_logic_simulator-0.0.1.dist-info → digsim_logic_simulator-0.1.0.dist-info}/RECORD

@@ -1,10 +1,10 @@
 digsim/__init__.py,sha256=FDN6JCbGIBP21Zdf_ZNRryiJ6zQLIlTGTZk-Zj4zwpI,151
-digsim/app/__main__.py,sha256=J2o90H-WRyCwrhzKZv82QFS9-wuwoilmA7HHT4rmbpI,1334
+digsim/app/__main__.py,sha256=EYeDrLJR6XC-fRNOhnrDSCDqv60LcO7wY638w3pdHPk,1370
 digsim/app/gui/__init__.py,sha256=UXHtaunKWrrd4QTIna6DAF4rCMqFsBFmodDBj4YB6EI,167
 digsim/app/gui/_circuit_area.py,sha256=iEGINxE-IwmqwVsFMJvqZ2cmauEqf4vo8W83JxIMI_k,16482
 digsim/app/gui/_component_selection.py,sha256=BKBAp46pajiqQo1efpdIB7tczHSUkTiL6aMXfYTlzms,6425
 digsim/app/gui/_main_window.py,sha256=E4pX-5g6ZBLIZv-MpB92wHP2_QSOVcQvjL6ug2X2dHg,5312
-digsim/app/gui/_top_bar.py,sha256=odmRo187nWLt_fvZLJv4tjIDBeq0jmzShZKULs9-Ws4,13142
+digsim/app/gui/_top_bar.py,sha256=YEKJ-ucDDHH4fcHL9GS6jJ8teDhEKuTRaCAN1qTO8Rc,13150
 digsim/app/gui/_utils.py,sha256=SSbe4B-trgZpaerPZilAaZYeqMOlFZMuufTth8KyOAg,660
 digsim/app/gui/_warning_dialog.py,sha256=XINQRNeLtWDFueYXMjTJU6UvIwQ1W1F3lbigp7aPH1Y,1533
 digsim/app/gui_objects/__init__.py,sha256=qNA190htBAVOQr01oxE7NnAo_A6gtPGuKD3yuNfy8hk,266
@@ -17,12 +17,12 @@ digsim/app/gui_objects/_dip_switch_object.py,sha256=_4zkRzEWtv0NwTpjol0nqZhbmgVr
 digsim/app/gui_objects/_gui_note_object.py,sha256=RAlsH1BBi8XQhEWbAW-mDPSQJpOtPuM6SEkw3Nyekdg,2606
 digsim/app/gui_objects/_gui_object_factory.py,sha256=90G_X8FOa-U05iqUFV4M5q6pe9r7_QDcQ5W8sXwTkQQ,2467
 digsim/app/gui_objects/_hexdigit_object.py,sha256=fLoqpfmmFWelMYosVGdcUZhXEsPCIIURJ07SJvRVIR4,1928
-digsim/app/gui_objects/_image_objects.py,sha256=sQK_u9QYjJgu-Mr0614JtpGwP92frXBZq4PJ2c8ucZA,7621
+digsim/app/gui_objects/_image_objects.py,sha256=M7s-lgKD7A7FaX3_O2BZroWpR_ooKlXIITxDAfI0z0s,7588
 digsim/app/gui_objects/_label_object.py,sha256=uRgTkLHpIddtnDSyOPZrbjVZKduodPHDGA8WxpnxZE4,3572
 digsim/app/gui_objects/_logic_analyzer_object.py,sha256=b-Q9V7fDvA411-m0HZGYx4fUnUv6Pyf9ZuXCzIUaeZU,2674
 digsim/app/gui_objects/_seven_segment_object.py,sha256=qPR2tBbbjzwcH6pr5Yg6BrWHXcTzI5vQwCrF5l9lqm0,4262
 digsim/app/gui_objects/_shortcut_objects.py,sha256=Ze3kayeBV7lweurSEsj98_-ChBjB6OwZESp4M6Zgljs,2763
-digsim/app/gui_objects/_yosys_object.py,sha256=Q9OBB2YZOAgB_U5y9lqLYlNlk9dHcAQlDdNVnj7mvfk,755
+digsim/app/gui_objects/_yosys_object.py,sha256=OucYqfEKQMLyj0Kma7BP0_6pM_3HUBMRKLs07V6l54M,955
 digsim/app/gui_objects/images/AND.png,sha256=d53gEcxIlfqmW-Q4Za3n5i_NmSEcjJqlbh8XxoSdR3o,12062
 digsim/app/gui_objects/images/Analyzer.png,sha256=1OrkKsL6ktxKI12KzNJT7rgEi2X-jAqp6vrVuVthErY,1591
 digsim/app/gui_objects/images/BUF.png,sha256=fd8DqEM3aht4cjoWuqsbHlTiQaFa9ddibe3iel1WYLo,12819
@@ -49,7 +49,7 @@ digsim/app/gui_objects/images/YOSYS.png,sha256=etTO9jadU0amxQG7ySRjD6fME4HjrEEqX
 digsim/app/gui_objects/images/ZERO.png,sha256=hXnZgEVO3T_zN5CiFhu6cIXr19LAu6SdvX-sIOq06E4,3459
 digsim/app/images/app_icon.png,sha256=OfPoYA4o4Af79DTqQxSNLca0FdXRHEYteBK-xCQFEAw,16041
 digsim/app/model/__init__.py,sha256=djkoPeT3QoWyjzHdxTTAo7lpu9XbnXDvBBkffCAewms,161
-digsim/app/model/_model.py,sha256=9q81tTE5IZZ4MxaEYtN0JIybLULdzNG_5rbt4P2tkQc,6534
+digsim/app/model/_model.py,sha256=MVrsIv8CZnITsVn79OyjJ9dMqajO5beEzhj7yJ_FCpE,6551
 digsim/app/model/_model_components.py,sha256=8x96YmkeHEaBYaB5i88G_Zf9MHcc05g8Go_YEBJ3R_o,6500
 digsim/app/model/_model_new_wire.py,sha256=5HnF5-gtKtB1Tp6ZIF7QuNo5zEHmsUpnBEmj6ZllLiA,1810
 digsim/app/model/_model_objects.py,sha256=mX7xMmLFYLZjwvG7CjpkWcKOfB5FPR1FgAe4mDSW1Vw,5078
@@ -64,39 +64,39 @@ digsim/circuit/_circuit.py,sha256=YM3Rj2_DtxrP3oaWfAaFJkQGUopTmXQtOITZhszu8ZA,11
 digsim/circuit/_waves_writer.py,sha256=tdh8Na_JoaC2gRHCPAK-UXEAgTC_ZcGHPBCAO7aekWA,1710
 digsim/circuit/components/__init__.py,sha256=YlrIUxtpi0K2ne3pEeMM0Z9s2h7y7ezOUbKNDQfT06Q,1269
 digsim/circuit/components/_bus_bits.py,sha256=0AvvteRnG4SpW_l-0e-cgBG85VxYlbfdVQFvQVSp88Y,1912
-digsim/circuit/components/_button.py,sha256=Nkwi0Ixq8dl3G_c7v3D6YyBmVtE6hul0fSjLwVZsf4c,1434
+digsim/circuit/components/_button.py,sha256=JK0yi48Putaf5RWJoPfD7kh9D4Gu5Nq2ZQKN3nnGOx0,1030
 digsim/circuit/components/_buzzer.py,sha256=zRvPhY8hdahDxfNTBzoGXJReQ_8iO3ot02Gz68szq2s,1125
 digsim/circuit/components/_clock.py,sha256=E6cINzY7_YXpHpr23Fn_V2_QhYLnPIZe0elxWozBUrY,1487
 digsim/circuit/components/_dip_switch.py,sha256=SX8vjNC2Nf0KZtXIRjBxz42fKJmp1qGHo4K0MJpg4N4,1807
 digsim/circuit/components/_flip_flops.py,sha256=eOB1hpSfK7vlpcOQzHqILpAzfwsqQPobC-_ebDxGVLw,2942
-digsim/circuit/components/_gates.py,sha256=cZuOUYkA1Myf18slsdXgu8u2WH4q7EW5g5iMdNJAgJE,7198
-digsim/circuit/components/_hexdigit.py,sha256=gJMRG5fq_Tpi4RLH8QEzUNh-YTRnehwdOvikS_xVC-4,2259
-digsim/circuit/components/_ic.py,sha256=fS93im6GEz8QLOADWNIlibu2Q5CLeV7fE8jnJ_plEEw,901
+digsim/circuit/components/_gates.py,sha256=_eQXmDCDnaE2QPjxoRa4QB0RB2YInPXW6JV1bPxiE0Q,7192
+digsim/circuit/components/_hexdigit.py,sha256=899_4hc02vWgpNVm7Ts7-PBHJc7Dc5hZFSJFayJuLQk,2257
+digsim/circuit/components/_ic.py,sha256=ppr6i7BpMiTdk889-TlFdANo0e-P4uDFeFA-666D1QQ,916
 digsim/circuit/components/_label_wire.py,sha256=NNlxwWCBGYGjQLiliqXRLGIkd3eOoCAVYW8tnPEI-sk,5112
 digsim/circuit/components/_led.py,sha256=djFGARGE1-DlTI7Xqd9eksqk6U1Cq8l51hLrzd_ut68,454
 digsim/circuit/components/_logic_analyzer.py,sha256=14iKsEifXXLIoZtm7ZOukHbFm7Y8TTTVO36Dplg-2hU,1809
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 digsim/circuit/components/_note.py,sha256=4o4bRw_7smKc_FGrVkhPwwIqC_500Vj_w8TrNtK1A8s,602
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 digsim/utils/__init__.py,sha256=1WW4WR61YIrehXvHp_fSTBkAUBb9G5v3npGQLYY_CvA,169
 digsim/utils/_yosys_netlist.py,sha256=g-7hkVgGOYJUQbKv8wBqHMHqj44utuGHGbtaRb-qG60,8562
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