da4ml 0.5.0__cp312-cp312-manylinux_2_24_x86_64.manylinux_2_28_x86_64.whl

da4ml/codegen/rtl/vhdl/comb.py

@@ -0,0 +1,206 @@
+from math import ceil, log2
+
+import numpy as np
+
+from ....cmvm.types import CombLogic, QInterval, _minimal_kif
+from ..verilog.comb import get_table_name
+
+
+def make_neg(
+    signals: list[str],
+    assigns: list[str],
+    idx: int,
+    qint: QInterval,
+    v0_name: str,
+    neg_repo: dict[int, tuple[int, str]],
+):
+    if idx in neg_repo:
+        return neg_repo[idx]
+    _min, _max, step = qint
+    was_signed = int(_min < 0)
+    bw0 = sum(_minimal_kif(qint))
+    bw_neg = sum(_minimal_kif(QInterval(-_max, -_min, step)))
+    signals.append(f'signal v{idx}_neg : std_logic_vector({bw_neg - 1} downto {0});')
+    assigns.append(
+        f'op_neg_{idx} : entity work.negative generic map (BW_IN => {bw0}, BW_OUT => {bw_neg}, IN_SIGNED => {was_signed}) port map (neg_in => {v0_name}, neg_out => v{idx}_neg);'
+    )
+    bw0 = bw_neg
+    v0_name = f'v{idx}_neg'
+    neg_repo[idx] = (bw0, v0_name)
+    return bw0, v0_name
+
+
+def ssa_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]], print_latency: bool = False):
+    ops = sol.ops
+    kifs = list(map(_minimal_kif, (op.qint for op in ops)))
+    widths = list(map(sum, kifs))
+    inp_kifs = [_minimal_kif(qint) for qint in sol.inp_qint]
+    inp_widths = list(map(sum, inp_kifs))
+    _inp_widths = np.cumsum([0] + inp_widths)
+    inp_idxs = np.stack([_inp_widths[1:] - 1, _inp_widths[:-1]], axis=1)
+
+    signals = []
+    assigns = []
+    ref_count = sol.ref_count
+
+    for i, op in enumerate(ops):
+        if ref_count[i] == 0:
+            continue
+
+        bw = widths[i]
+        if bw == 0:
+            continue
+
+        signals.append(f'signal v{i}:std_logic_vector({bw - 1} downto {0});')
+
+        match op.opcode:
+            case -1:  # Input marker
+                i0, i1 = inp_idxs[op.id0]
+                line = f'v{i} <= model_inp({i0} downto {i1});'
+
+            case 0 | 1:  # Common a+/-b<<shift oprs
+                p0, p1 = kifs[op.id0], kifs[op.id1]
+                bw0, bw1 = widths[op.id0], widths[op.id1]
+                s0, f0, s1, f1 = int(p0[0]), p0[2], int(p1[0]), p1[2]
+                shift = op.data + f0 - f1
+                line = f'op_{i}:entity work.shift_adder generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw},SHIFT1=>{shift},IS_SUB=>{op.opcode}) port map(in0=>v{op.id0},in1=>v{op.id1},result=>v{i});'
+
+            case 2 | -2:  # ReLU
+                lsb_bias = kifs[op.id0][2] - kifs[i][2]
+                i0, i1 = bw + lsb_bias - 1, lsb_bias
+                v0_name = f'v{op.id0}'
+                bw0 = widths[op.id0]
+                if op.opcode == -2:
+                    bw0, v0_name = make_neg(signals, assigns, op.id0, ops[op.id0].qint, v0_name, neg_repo)
+                if ops[op.id0].qint.min < 0:
+                    if bw > 1:
+                        line = f'v{i} <= {v0_name}({i0} downto {i1}) and ({bw - 1} downto 0 => not {v0_name}({bw0 - 1}));'
+                    else:
+                        line = f'v{i}(0) <= {v0_name}(0) and (not {v0_name}({bw0 - 1}));'
+                else:
+                    line = f'v{i} <= {v0_name}({i0} downto {i1});'
+
+            case 3 | -3:  # Explicit quantization
+                lsb_bias = kifs[op.id0][2] - kifs[i][2]
+                i0, i1 = bw + lsb_bias - 1, lsb_bias
+                v0_name = f'v{op.id0}'
+                bw0 = widths[op.id0]
+                if op.opcode == -3:
+                    bw0, v0_name = make_neg(signals, assigns, op.id0, ops[op.id0].qint, v0_name, neg_repo)
+
+                if i0 >= bw0:
+                    if op.opcode == 3:
+                        assert ops[op.id0].qint.min < 0, f'{i}, {op.id0}'
+                    else:
+                        assert ops[op.id0].qint.max > 0, f'{i}, {op.id0}'
+
+                    if i1 >= bw0:
+                        v0_name = f'({i0 - i1} downto 0 => {v0_name}({bw0 - 1}))'
+                    else:
+                        v0_name = f'({i0 - bw0} downto 0 => {v0_name}({bw0 - 1})) & {v0_name}({bw0 - 1} downto {i1})'
+                    line = f'v{i} <= {v0_name};'
+                else:
+                    line = f'v{i} <= {v0_name}({i0} downto {i1});'
+
+            case 4:  # constant addition
+                num = op.data
+                sign, mag = int(num < 0), abs(num)
+                bw1 = ceil(log2(mag + 1)) if mag > 0 else 1
+                bw0 = widths[op.id0]
+                s0 = int(kifs[op.id0][0])
+                shift = kifs[op.id0][2] - kifs[i][2]
+                bin_val = format(mag, f'0{bw1}b')
+                line = f'op_{i}:entity work.shift_adder generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>0,BW_OUT=>{bw},SHIFT1=>{shift},IS_SUB=>{sign}) port map(in0=>v{op.id0},in1=>"{bin_val}",result=>v{i});'
+            case 5:  # constant
+                num = op.data
+                if num < 0:
+                    num = 2**bw + num
+                bin_val = format(num, f'0{bw}b')
+                line = f'v{i} <= "{bin_val}";'
+
+            case 6 | -6:  # MSB Muxing
+                k, a, b = op.data & 0xFFFFFFFF, op.id0, op.id1
+                p0, p1 = kifs[a], kifs[b]
+                inv = '1' if op.opcode == -6 else '0'
+                bwk, bw0, bw1 = widths[k], widths[a], widths[b]
+                s0, f0, s1, f1 = int(p0[0]), p0[2], int(p1[0]), p1[2]
+                _shift = (op.data >> 32) & 0xFFFFFFFF
+                _shift = _shift if _shift < 0x80000000 else _shift - 0x100000000
+                shift = f0 - f1 + _shift
+                v0, v1 = f'v{a}', f'v{b}'
+                if bw0 == 0:
+                    v0, bw0 = 'B"0"', 1
+                if bw1 == 0:
+                    v1, bw1 = 'B"0"', 1
+                line = f'op_{i}:entity work.mux generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw},SHIFT1=>{shift},INVERT1=>{inv}) port map(key=>v{k}({bwk - 1}),in0=>{v0},in1=>{v1},result=>v{i});'
+
+            case 7:  # Multiplication
+                bw0, bw1 = widths[op.id0], widths[op.id1]
+                s0, s1 = int(kifs[op.id0][0]), int(kifs[op.id1][0])
+                line = f'op_{i}:entity work.multiplier generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw}) port map(in0=>v{op.id0},in1=>v{op.id1},result=>v{i});'
+
+            case 8:  # Lookup Table
+                name = get_table_name(sol, op)
+                bw0 = widths[op.id0]
+                line = f'op_{i}:entity work.lookup_table generic map(BW_IN=>{bw0},BW_OUT=>{bw},MEM_FILE=>"{name}") port map(inp=>v{op.id0},outp=>v{i});'
+
+            case _:
+                raise ValueError(f'Unknown opcode {op.opcode} for operation {i} ({op})')
+
+        if print_latency:
+            line += f' -- {op.latency}'
+        assigns.append(line)
+    return signals, assigns
+
+
+def output_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]]):
+    assigns = []
+    signals = []
+    widths = list(map(sum, map(_minimal_kif, sol.out_qint)))
+    _widths = np.cumsum([0] + widths)
+    out_idxs = np.stack([_widths[1:] - 1, _widths[:-1]], axis=1)
+    for i, idx in enumerate(sol.out_idxs):
+        if idx < 0:
+            continue
+        i0, i1 = out_idxs[i]
+        if i0 == i1 - 1:
+            continue
+        bw = widths[i]
+        if sol.out_negs[i]:
+            bw, name = make_neg(signals, assigns, idx, sol.ops[idx].qint, f'v{idx}', neg_repo)
+            assigns.append(f'model_out({i0} downto {i1}) <= {name}({bw - 1} downto {0});')
+        else:
+            assigns.append(f'model_out({i0} downto {i1}) <= v{idx}({bw - 1} downto {0});')
+    return signals, assigns
+
+
+def comb_logic_gen(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None):
+    inp_bits = sum(map(sum, map(_minimal_kif, sol.inp_qint)))
+    out_bits = sum(map(sum, map(_minimal_kif, sol.out_qint)))
+
+    neg_repo: dict[int, tuple[int, str]] = {}
+    ssa_signals, ssa_assigns = ssa_gen(sol, neg_repo=neg_repo, print_latency=print_latency)
+    output_signals, output_assigns = output_gen(sol, neg_repo)
+    blk = '\n    '
+
+    code = f"""library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity {fn_name} is port(
+    model_inp:in std_logic_vector({inp_bits - 1} downto {0});
+    model_out:out std_logic_vector({out_bits - 1} downto {0})
+);
+end entity {fn_name};
+
+architecture rtl of {fn_name} is
+    {blk.join(ssa_signals + output_signals)}
+
+
+begin
+    {blk.join(ssa_assigns + output_assigns)}
+
+end architecture rtl;
+
+"""
+    return code

da4ml/codegen/rtl/vhdl/io_wrapper.py

@@ -0,0 +1,120 @@
+from itertools import accumulate
+
+from ....cmvm.types import CombLogic, Pipeline, QInterval, _minimal_kif
+
+
+def _loc(i: int, j: int):
+    return f'({i} downto {j})' if i != j else f'({i})'
+
+
+def hetero_io_map(qints: list[QInterval], merge: bool = False):
+    N = len(qints)
+    ks, _is, fs = zip(*map(_minimal_kif, qints))
+    Is = [_i + _k for _i, _k in zip(_is, ks)]
+    max_I, max_f = max(_is) + max(ks), max(fs)
+    max_bw = max_I + max_f
+    width_regular, width_packed = max_bw * N, sum(Is) + sum(fs)
+
+    regular: list[tuple[int, int]] = []
+    pads: list[tuple[int, int, int]] = []
+
+    bws = [I + f for I, f in zip(Is, fs)]
+    _bw = list(accumulate([0] + bws))
+    hetero = [(i - 1, j) for i, j in zip(_bw[1:], _bw[:-1])]
+
+    for i in range(N):
+        base = max_bw * i
+        bias_low = max_f - fs[i]
+        bias_high = max_I - Is[i]
+        low = base + bias_low
+        high = (base + max_bw - 1) - bias_high
+        regular.append((high, low))
+
+        if bias_low != 0:
+            pads.append((base + bias_low - 1, base, -1))
+        if bias_high != 0:
+            copy_from = hetero[i][0] if ks[i] else -1
+            pads.append((base + max_bw - 1, base + max_bw - bias_high, copy_from))
+
+    mask = list(high < low for high, low in hetero)
+    regular = [r for r, m in zip(regular, mask) if not m]
+    hetero = [h for h, m in zip(hetero, mask) if not m]
+
+    if not merge:
+        return regular, hetero, pads, (width_regular, width_packed)
+
+    # Merging consecutive intervals when possible
+    NN = len(regular) - 2
+    for i in range(NN, -1, -1):
+        this_high = regular[i][0]
+        next_low = regular[i + 1][1]
+        if next_low - this_high != 1:
+            continue
+        regular[i] = (regular[i + 1][0], regular[i][1])
+        regular.pop(i + 1)
+        hetero[i] = (hetero[i + 1][0], hetero[i][1])
+        hetero.pop(i + 1)
+
+    for i in range(len(pads) - 2, -1, -1):
+        if pads[i + 1][1] - pads[i][0] == 1 and pads[i][2] == pads[i + 1][2]:
+            pads[i] = (pads[i + 1][0], pads[i][1], pads[i][2])
+            pads.pop(i + 1)
+
+    return regular, hetero, pads, (width_regular, width_packed)
+
+
+def generate_io_wrapper(sol: CombLogic | Pipeline, module_name: str, pipelined: bool = False):
+    reg_in, het_in, _, shape_in = hetero_io_map(sol.inp_qint, merge=True)
+    reg_out, het_out, pad_out, shape_out = hetero_io_map(sol.out_qint, merge=True)
+
+    w_reg_in, w_het_in = shape_in
+    w_reg_out, w_het_out = shape_out
+
+    inp_assignment = [f'packed_inp{_loc(ih, jh)} <= model_inp{_loc(ir, jr)};' for (ih, jh), (ir, jr) in zip(het_in, reg_in)]
+    _out_assignment: list[tuple[int, str]] = []
+
+    for i, ((ih, jh), (ir, jr)) in enumerate(zip(het_out, reg_out)):
+        if ih == jh - 1:
+            continue
+        _out_assignment.append((ih, f'model_out{_loc(ir, jr)} <= packed_out{_loc(ih, jh)};'))
+
+    for i, (i, j, copy_from) in enumerate(pad_out):
+        n_bit = i - j + 1
+        value = "'0'" if copy_from == -1 else f'packed_out({copy_from})'
+        pad = f'(others => {value})' if n_bit > 1 else value
+        _out_assignment.append((i, f'model_out{_loc(i, j)} <= {pad};'))
+    _out_assignment.sort(key=lambda x: x[0])
+    out_assignment = [v for _, v in _out_assignment]
+
+    inp_assignment_str = '\n    '.join(inp_assignment)
+    out_assignment_str = '\n    '.join(out_assignment)
+
+    clk_and_rst_inp, clk_and_rst_bind = '', ''
+    if pipelined:
+        clk_and_rst_inp = '\n    clk:in std_logic;'
+        clk_and_rst_bind = '\n        clk=>clk,'
+
+    return f"""library ieee;
+use ieee.std_logic_1164.all;
+entity {module_name}_wrapper is port({clk_and_rst_inp}
+    model_inp:in std_logic_vector({w_reg_in - 1} downto {0});
+    model_out:out std_logic_vector({w_reg_out - 1} downto {0})
+);
+end entity {module_name}_wrapper;
+
+architecture rtl of {module_name}_wrapper is
+    signal packed_inp:std_logic_vector({w_het_in - 1} downto {0});
+    signal packed_out:std_logic_vector({w_het_out - 1} downto {0});
+
+begin
+    {inp_assignment_str}
+
+    op:entity work.{module_name} port map({clk_and_rst_bind}
+        model_inp=>packed_inp,
+        model_out=>packed_out
+    );
+
+    {out_assignment_str}
+
+end architecture rtl;
+"""

da4ml/codegen/rtl/vhdl/pipeline.py

@@ -0,0 +1,71 @@
+from ....cmvm.types import Pipeline, _minimal_kif
+from .comb import comb_logic_gen
+
+
+def pipeline_logic_gen(
+    csol: Pipeline,
+    name: str,
+    print_latency=False,
+    timescale: str | None = None,
+    register_layers: int = 1,
+):
+    N = len(csol.solutions)
+    inp_bits = [sum(map(sum, map(_minimal_kif, sol.inp_qint))) for sol in csol.solutions]
+    out_bits = inp_bits[1:] + [sum(map(sum, map(_minimal_kif, csol.out_qint)))]
+
+    registers = [f'signal stage{i}_inp:std_logic_vector({width - 1} downto 0);' for i, width in enumerate(inp_bits)]
+    for i in range(0, register_layers - 1):
+        registers += [f'signal stage{j}_inp_copy{i}:std_logic_vector({width - 1} downto 0);' for j, width in enumerate(inp_bits)]
+    wires = [f'signal stage{i}_out:std_logic_vector({width - 1} downto 0);' for i, width in enumerate(out_bits)]
+
+    comb_logic = [
+        f'stage{i}:entity work.{name}_stage{i} port map(model_inp=>stage{i}_inp,model_out=>stage{i}_out);' for i in range(N)
+    ]
+
+    if register_layers == 1:
+        serial_logic = ['stage0_inp <= model_inp;']
+        serial_logic += [f'stage{i}_inp <= stage{i - 1}_out;' for i in range(1, N)]
+    else:
+        serial_logic = ['stage0_inp_copy0 <= model_inp;']
+        for j in range(1, register_layers - 1):
+            serial_logic.append(f'stage0_inp_copy{j} <= stage0_inp_copy{j - 1};')
+        serial_logic.append(f'stage0_inp <= stage0_inp_copy{register_layers - 2};')
+        for i in range(1, N):
+            serial_logic.append(f'stage{i}_inp_copy0 <= stage{i - 1}_out;')
+            for j in range(1, register_layers - 1):
+                serial_logic.append(f'stage{i}_inp_copy{j} <= stage{i}_inp_copy{j - 1};')
+            serial_logic.append(f'stage{i}_inp <= stage{i}_inp_copy{register_layers - 2};')
+
+    serial_logic += [f'model_out <= stage{N - 1}_out;']
+
+    blk = '\n    '
+
+    module = f"""library ieee;
+use ieee.std_logic_1164.all;
+entity {name} is port(
+    clk:in std_logic;
+    model_inp:in std_logic_vector({inp_bits[0] - 1} downto 0);
+    model_out:out std_logic_vector({out_bits[-1] - 1} downto 0));
+end entity {name};
+
+architecture rtl of {name} is
+    {blk.join(registers)}
+    {blk.join(wires)}
+
+begin
+    {blk.join(comb_logic)}
+
+    process(clk) begin
+        if rising_edge(clk) then
+            {f'{blk}        '.join(serial_logic)}
+        end if;
+    end process;
+end architecture rtl;
+"""
+
+    ret: dict[str, str] = {}
+    for i, s in enumerate(csol.solutions):
+        stage_name = f'{name}_stage{i}'
+        ret[stage_name] = comb_logic_gen(s, stage_name, print_latency=print_latency, timescale=timescale)
+    ret[name] = module
+    return ret

da4ml/codegen/rtl/vhdl/source/lookup_table.vhd

@@ -0,0 +1,52 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+
+entity lookup_table is
+	generic (
+		BW_IN    : positive := 8;
+		BW_OUT   : positive := 8;
+		MEM_FILE : string   := "whatever.mem"
+	);
+	port (
+		inp  : in  std_logic_vector(BW_IN - 1 downto 0);
+		outp : out std_logic_vector(BW_OUT - 1 downto 0)
+	);
+end entity lookup_table;
+
+architecture rtl of lookup_table is
+	subtype rom_index_t is natural range 0 to (2 ** BW_IN) - 1;
+	type rom_array_t is array (rom_index_t) of std_logic_vector(BW_OUT - 1 downto 0);
+
+	-- Load the ROM contents from an external hex file.
+	impure function init_rom return rom_array_t is
+		file rom_file : text;
+		variable rom_data : rom_array_t := (others => (others => '0'));
+		variable line_in  : line;
+		variable idx      : integer := 0;
+		variable data_val : std_logic_vector(BW_OUT - 1 downto 0);
+		variable temp_val : std_logic_vector(((BW_OUT + 3) / 4) * 4 - 1 downto 0);
+	begin
+		file_open(rom_file, MEM_FILE, read_mode);
+
+	while not endfile(rom_file) loop
+		exit when idx > rom_index_t'high;
+		readline(rom_file, line_in);
+		hread(line_in, temp_val);
+		rom_data(idx) := temp_val(BW_OUT - 1 downto 0);
+		idx := idx + 1;
+	end loop;
+
+	file_close(rom_file);
+	return rom_data;
+	end function init_rom;
+
+	signal ROM_CONTENTS : rom_array_t := init_rom;
+
+	attribute rom_style : string;
+	attribute rom_style of ROM_CONTENTS : signal is "distributed";
+begin
+	outp <= ROM_CONTENTS(to_integer(unsigned(inp)));
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/multiplier.vhd

@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity multiplier is
+    generic (
+        BW_INPUT0 : integer := 32;
+        BW_INPUT1 : integer := 32;
+        SIGNED0   : integer := 0;
+        SIGNED1   : integer := 0;
+        BW_OUT    : integer := 32
+    );
+    port (
+        in0 : in  std_logic_vector(BW_INPUT0-1 downto 0);
+        in1 : in  std_logic_vector(BW_INPUT1-1 downto 0);
+        result : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity multiplier;
+
+architecture rtl of multiplier is
+    constant BW_BUF : integer := BW_INPUT0 + BW_INPUT1;
+    signal mult_buffer : std_logic_vector(BW_BUF-1 downto 0);
+begin
+
+    gen_mult : process(in0, in1)
+    begin
+        if SIGNED0 = 1 and SIGNED1 = 1 then
+            mult_buffer <= std_logic_vector(resize(signed(in0) * signed(in1), BW_BUF));
+        elsif SIGNED0 = 1 and SIGNED1 = 0 then
+            mult_buffer <= std_logic_vector(resize(signed(in0) * signed('0' & in1), BW_BUF));
+        elsif SIGNED0 = 0 and SIGNED1 = 1 then
+            mult_buffer <= std_logic_vector(resize(signed('0' & in0) * signed(in1), BW_BUF));
+        else
+            mult_buffer <= std_logic_vector(resize(unsigned(in0) * unsigned(in1), BW_BUF));
+        end if;
+    end process;
+
+    result <= mult_buffer(BW_OUT-1 downto 0);
+
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/mux.vhd

@@ -0,0 +1,102 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mux is
+    generic (
+        BW_INPUT0 : integer := 32;
+        BW_INPUT1 : integer := 32;
+        SIGNED0   : integer := 0;
+        SIGNED1   : integer := 0;
+        BW_OUT    : integer := 32;
+        SHIFT1    : integer := 0;
+        INVERT1   : integer := 0
+    );
+    port (
+        key : in  std_logic;
+        in0 : in  std_logic_vector(BW_INPUT0-1 downto 0);
+        in1 : in  std_logic_vector(BW_INPUT1-1 downto 0);
+        result : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity mux;
+
+architecture rtl of mux is
+    function max(L, R: integer) return integer is
+    begin
+        if L > R then
+            return L;
+        else
+            return R;
+        end if;
+    end function;
+
+    function if_then_else(cond: boolean; val_true: integer; val_false: integer) return integer is
+    begin
+        if cond then
+            return val_true;
+        else
+            return val_false;
+        end if;
+    end function;
+
+    constant IN0_NEED_BITS : integer := if_then_else(SHIFT1 < 0, BW_INPUT0 - SHIFT1, BW_INPUT0);
+    constant IN1_NEED_BITS : integer := if_then_else(SHIFT1 > 0, BW_INPUT1 + SHIFT1, BW_INPUT1);
+    constant EXTRA_PAD : integer := if_then_else(SIGNED0 /= SIGNED1, INVERT1 + 1, INVERT1);
+    constant BW_BUF : integer := max(IN0_NEED_BITS, IN1_NEED_BITS) + EXTRA_PAD;
+
+    signal in0_ext : std_logic_vector(BW_BUF-1 downto 0);
+    signal in1_ext : std_logic_vector(BW_BUF-1 downto 0);
+    signal out_buf : std_logic_vector(BW_BUF-1 downto 0);
+
+begin
+
+    -- Extension and shifting for input 0
+    gen_in0_shift_neg: if SHIFT1 < 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_BUF)) sll (-SHIFT1);
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_BUF)) sll (-SHIFT1);
+        end generate;
+    end generate;
+
+    gen_in0_shift_pos: if SHIFT1 >= 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_BUF));
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_BUF));
+        end generate;
+    end generate;
+
+    -- Extension and shifting for input 1
+    gen_in1_shift_pos: if SHIFT1 > 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_BUF)) sll SHIFT1;
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_BUF)) sll SHIFT1;
+        end generate;
+    end generate;
+
+    gen_in1_shift_neg: if SHIFT1 <= 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_BUF));
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_BUF));
+        end generate;
+    end generate;
+
+    -- Mux logic
+    gen_invert: if INVERT1 = 1 generate
+        out_buf <= in0_ext when key = '1' else std_logic_vector(-signed(in1_ext));
+    end generate;
+
+    gen_no_invert: if INVERT1 = 0 generate
+        out_buf <= in0_ext when key = '1' else in1_ext;
+    end generate;
+
+    result <= out_buf(BW_OUT-1 downto 0);
+
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/negative.vhd

@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity negative is
+    generic (
+        BW_IN     : integer := 32;
+        BW_OUT    : integer := 32;
+        IN_SIGNED : integer := 0
+    );
+    port (
+        neg_in  : in  std_logic_vector(BW_IN-1 downto 0);
+        neg_out : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity negative;
+
+architecture rtl of negative is
+    signal in_ext : std_logic_vector(BW_OUT-1 downto 0);
+begin
+
+    gen_lt : if BW_IN < BW_OUT generate
+        gen_signed : if IN_SIGNED = 1 generate
+            in_ext <= std_logic_vector(resize(signed(neg_in), BW_OUT));
+        end generate;
+        gen_unsigned : if IN_SIGNED = 0 generate
+            in_ext <= std_logic_vector(resize(unsigned(neg_in), BW_OUT));
+        end generate;
+        neg_out <= std_logic_vector(-signed(in_ext));
+    end generate;
+
+    gen_ge : if BW_IN >= BW_OUT generate
+        neg_out <= std_logic_vector(-signed(neg_in(BW_OUT-1 downto 0)));
+    end generate;
+
+end architecture rtl;