da4ml 0.3.3__py3-none-any.whl → 0.4.0__py3-none-any.whl

da4ml/codegen/rtl/vhdl/source/mux.vhd

@@ -0,0 +1,102 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mux is
+    generic (
+        BW_INPUT0 : integer := 32;
+        BW_INPUT1 : integer := 32;
+        SIGNED0   : integer := 0;
+        SIGNED1   : integer := 0;
+        BW_OUT    : integer := 32;
+        SHIFT1    : integer := 0;
+        INVERT1   : integer := 0
+    );
+    port (
+        key : in  std_logic;
+        in0 : in  std_logic_vector(BW_INPUT0-1 downto 0);
+        in1 : in  std_logic_vector(BW_INPUT1-1 downto 0);
+        result : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity mux;
+
+architecture rtl of mux is
+    function max(L, R: integer) return integer is
+    begin
+        if L > R then
+            return L;
+        else
+            return R;
+        end if;
+    end function;
+
+    function if_then_else(cond: boolean; val_true: integer; val_false: integer) return integer is
+    begin
+        if cond then
+            return val_true;
+        else
+            return val_false;
+        end if;
+    end function;
+
+    constant IN0_NEED_BITS : integer := if_then_else(SHIFT1 < 0, BW_INPUT0 - SHIFT1, BW_INPUT0);
+    constant IN1_NEED_BITS : integer := if_then_else(SHIFT1 > 0, BW_INPUT1 + SHIFT1, BW_INPUT1);
+    constant EXTRA_PAD : integer := if_then_else(SIGNED0 /= SIGNED1, INVERT1 + 1, INVERT1);
+    constant BW_BUF : integer := max(IN0_NEED_BITS, IN1_NEED_BITS) + EXTRA_PAD;
+
+    signal in0_ext : std_logic_vector(BW_BUF-1 downto 0);
+    signal in1_ext : std_logic_vector(BW_BUF-1 downto 0);
+    signal out_buf : std_logic_vector(BW_BUF-1 downto 0);
+
+begin
+
+    -- Extension and shifting for input 0
+    gen_in0_shift_neg: if SHIFT1 < 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_BUF)) sll (-SHIFT1);
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_BUF)) sll (-SHIFT1);
+        end generate;
+    end generate;
+
+    gen_in0_shift_pos: if SHIFT1 >= 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_BUF));
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_BUF));
+        end generate;
+    end generate;
+
+    -- Extension and shifting for input 1
+    gen_in1_shift_pos: if SHIFT1 > 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_BUF)) sll SHIFT1;
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_BUF)) sll SHIFT1;
+        end generate;
+    end generate;
+
+    gen_in1_shift_neg: if SHIFT1 <= 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_BUF));
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_BUF));
+        end generate;
+    end generate;
+
+    -- Mux logic
+    gen_invert: if INVERT1 = 1 generate
+        out_buf <= in0_ext when key = '1' else std_logic_vector(-signed(in1_ext));
+    end generate;
+
+    gen_no_invert: if INVERT1 = 0 generate
+        out_buf <= in0_ext when key = '1' else in1_ext;
+    end generate;
+
+    result <= out_buf(BW_OUT-1 downto 0);
+
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/negative.vhd

@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity negative is
+    generic (
+        BW_IN     : integer := 32;
+        BW_OUT    : integer := 32;
+        IN_SIGNED : integer := 0
+    );
+    port (
+        neg_in  : in  std_logic_vector(BW_IN-1 downto 0);
+        neg_out : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity negative;
+
+architecture rtl of negative is
+    signal in_ext : std_logic_vector(BW_OUT-1 downto 0);
+begin
+
+    gen_lt : if BW_IN < BW_OUT generate
+        gen_signed : if IN_SIGNED = 1 generate
+            in_ext <= std_logic_vector(resize(signed(neg_in), BW_OUT));
+        end generate;
+        gen_unsigned : if IN_SIGNED = 0 generate
+            in_ext <= std_logic_vector(resize(unsigned(neg_in), BW_OUT));
+        end generate;
+        neg_out <= std_logic_vector(-signed(in_ext));
+    end generate;
+
+    gen_ge : if BW_IN >= BW_OUT generate
+        neg_out <= std_logic_vector(-signed(neg_in(BW_OUT-1 downto 0)));
+    end generate;
+
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/shift_adder.vhd

@@ -0,0 +1,101 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity shift_adder is
+    generic (
+        BW_INPUT0 : integer := 32;
+        BW_INPUT1 : integer := 32;
+        SIGNED0   : integer := 0;
+        SIGNED1   : integer := 0;
+        BW_OUT    : integer := 32;
+        SHIFT1    : integer := 0;
+        IS_SUB    : integer := 0
+    );
+    port (
+        in0 : in  std_logic_vector(BW_INPUT0-1 downto 0);
+        in1 : in  std_logic_vector(BW_INPUT1-1 downto 0);
+        result : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity shift_adder;
+
+architecture rtl of shift_adder is
+    function max(L, R: integer) return integer is
+    begin
+        if L > R then
+            return L;
+        else
+            return R;
+        end if;
+    end function;
+
+    function if_then_else(cond: boolean; val_true: integer; val_false: integer) return integer is
+    begin
+        if cond then
+            return val_true;
+        else
+            return val_false;
+        end if;
+    end function;
+
+    constant IN0_NEED_BITS : integer := if_then_else(SHIFT1 < 0, BW_INPUT0 - SHIFT1, BW_INPUT0);
+    constant IN1_NEED_BITS : integer := if_then_else(SHIFT1 > 0, BW_INPUT1 + SHIFT1, BW_INPUT1);
+    constant EXTRA_PAD     : integer := if_then_else(SIGNED0 /= SIGNED1, IS_SUB + 1, IS_SUB);
+    constant BW_ADD        : integer := max(IN0_NEED_BITS, IN1_NEED_BITS) + EXTRA_PAD + 1;
+
+    signal in0_ext : std_logic_vector(BW_ADD-1 downto 0);
+    signal in1_ext : std_logic_vector(BW_ADD-1 downto 0);
+    signal accum   : std_logic_vector(BW_ADD-1 downto 0);
+
+begin
+
+    -- Extension and shifting for input 0
+    gen_in0_shift_neg: if SHIFT1 < 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_ADD)) sll (-SHIFT1);
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_ADD)) sll (-SHIFT1);
+        end generate;
+    end generate;
+
+    gen_in0_shift_pos: if SHIFT1 >= 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_ADD));
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_ADD));
+        end generate;
+    end generate;
+
+    -- Extension and shifting for input 1
+    gen_in1_shift_pos: if SHIFT1 > 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_ADD)) sll SHIFT1;
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_ADD)) sll SHIFT1;
+        end generate;
+    end generate;
+
+    gen_in1_shift_neg: if SHIFT1 <= 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_ADD));
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_ADD));
+        end generate;
+    end generate;
+
+    -- Addition/subtraction logic
+    gen_sub: if IS_SUB = 1 generate
+        accum <= std_logic_vector(signed(in0_ext) - signed(in1_ext));
+    end generate;
+
+    gen_add: if IS_SUB = 0 generate
+        accum <= std_logic_vector(signed(in0_ext) + signed(in1_ext));
+    end generate;
+
+    result <= accum(BW_OUT-1 downto 0);
+
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/template.xdc

@@ -0,0 +1,32 @@
+set clock_period ${CLOCK_PERIOD}
+
+# Clock uncertainty as percentage of clock period
+set uncertainty_setup_r ${UNCERTAINITY_SETUP}
+set uncertainty_hold_r ${UNCERTAINITY_HOLD}
+set delay_max_r ${DELAY_MAX}
+set delay_min_r ${DELAY_MIN}
+
+# Calculate actual uncertainty values
+set uncertainty_setup [expr {$clock_period * $uncertainty_setup_r}]
+set uncertainty_hold [expr {$clock_period * $uncertainty_hold_r}]
+set delay_max [expr {$clock_period * $delay_max_r}]
+set delay_min [expr {$clock_period * $delay_min_r}]
+
+# Create clock with variable period
+create_clock -period $clock_period -name sys_clk [get_ports {clk}]
+
+# Input/Output constraints
+set_input_delay -clock sys_clk -max $delay_max [get_ports {inp[*]}]
+set_input_delay -clock sys_clk -min $delay_min [get_ports {inp[*]}]
+
+set_output_delay -clock sys_clk -max $delay_max [get_ports {out[*]}]
+set_output_delay -clock sys_clk -min $delay_min [get_ports {out[*]}]
+
+# Apply calculated uncertainty values
+set_clock_uncertainty -setup $uncertainty_setup [get_clocks sys_clk]
+set_clock_uncertainty -hold $uncertainty_hold [get_clocks sys_clk]
+
+set_property HD.CLK_SRC BUFG_X0Y0 [get_ports clk]
+
+set_property retiming_forward 1 [get_cells {stage[*]_inp}]
+set_property retiming_backward 1 [get_cells {stage[*]_inp}]

{da4ml-0.3.3.dist-info → da4ml-0.4.0.dist-info}/METADATA

@@ -1,7 +1,7 @@
 Metadata-Version: 2.4
 Name: da4ml
-Version: 0.3.3
-Summary: Digital Arithmetic for Machine Learning
+Version: 0.4.0
+Summary: Distributed Arithmetic for Machine Learning
 Author-email: Chang Sun <chsun@cern.ch>
 License: GNU Lesser General Public License v3 (LGPLv3)
 Project-URL: repository, https://github.com/calad0i/da4ml

da4ml-0.4.0.dist-info/RECORD

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da4ml/codegen/cpp/__init__.py

@@ -1,4 +0,0 @@
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-from .hls_model import HLSModel
-
-__all__ = ['cpp_logic_and_bridge_gen', 'HLSModel']

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