da4ml 0.3.0__py3-none-any.whl → 0.3.1__py3-none-any.whl

da4ml/_version.py

@@ -17,5 +17,5 @@ __version__: str
 __version_tuple__: VERSION_TUPLE
 version_tuple: VERSION_TUPLE
 
-__version__ = version = '0.3.0'
-__version_tuple__ = version_tuple = (0, 3, 0)
+__version__ = version = '0.3.1'
+__version_tuple__ = version_tuple = (0, 3, 1)

da4ml/codegen/verilog/source/build_prj.tcl

@@ -1,7 +1,7 @@
 set project_name "${PROJECT_NAME}"
 set device "${DEVICE}"
 
-set top_module "${project_name}_wrapper"
+set top_module "${project_name}"
 set output_dir "./output_${project_name}"
 
 create_project $project_name "${output_dir}/$project_name" -force -part $device
@@ -9,9 +9,10 @@ create_project $project_name "${output_dir}/$project_name" -force -part $device
 set_property TARGET_LANGUAGE Verilog [current_project]
 set_property DEFAULT_LIB work [current_project]
 
-read_verilog "${project_name}_wrapper.v"
 read_verilog "${project_name}.v"
 read_verilog "shift_adder.v"
+read_verilog "negative.v"
+read_verilog "mux.v"
 foreach file [glob -nocomplain "${project_name}_stage*.v"] {
     read_verilog $file
 }
@@ -25,8 +26,7 @@ file mkdir "${output_dir}/reports"
 
 # synth
 synth_design -top $top_module -mode out_of_context -retiming \
-    -flatten_hierarchy rebuilt -resource_sharing auto \
-    -directive AlternateRoutability
+    -flatten_hierarchy full -resource_sharing auto
 
 write_checkpoint -force "${output_dir}/${project_name}_post_synth.dcp"
 
@@ -34,15 +34,13 @@ report_timing_summary -file "${output_dir}/reports/${project_name}_post_synth_ti
 report_power -file "${output_dir}/reports/${project_name}_post_synth_power.rpt"
 report_utilization -file "${output_dir}/reports/${project_name}_post_synth_util.rpt"
 
-# set_property CARRY_REMAP 3 [get_cells -hier -filter {ref_name == CARRY8}]
-
-opt_design -directive ExploreSequentialArea
+# opt_design -directive ExploreSequentialArea
 opt_design -directive ExploreWithRemap
 
 report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_opt_congestion.rpt"
 
 # place
-place_design -directive AltSpreadLogic_high -fanout_opt
+place_design -directive SSI_HighUtilSLRs -fanout_opt
 report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_place_congestion_initial.rpt"
 
 phys_opt_design -directive AggressiveExplore

da4ml/codegen/verilog/verilog_model.py

@@ -28,10 +28,10 @@ class VerilogModel:
         solution: Solution | CascadedSolution,
         prj_name: str,
         path: str | Path,
-        latency_cutoff: int = -1,
+        latency_cutoff: float = -1,
         print_latency: bool = True,
         part_name: str = 'xcvu13p-flga2577-2-e',
-        clock_period: int = 5,
+        clock_period: float = 5,
         clock_uncertainty: float = 0.1,
         io_delay_minmax: tuple[float, float] = (0.2, 0.4),
         register_layers: int = 1,

da4ml/converter/hgq2/replica.py

@@ -157,7 +157,7 @@ class MirrorQDense(MirrorOperationBase):
             dim = inputs._vars.ndim
             axis = op.axis
             assert axis != 0, 'Cannot normalizing on batch axis'
-            axis -= 1
+            axis = axis - 1 if axis >= 0 else dim + axis
             idx = ''.join(chr(ord('a') + i) for i in range(dim))
             eq = f'...{idx},{idx[axis]}->...{idx}'
         else:

da4ml/trace/ops/conv_utils.py

@@ -40,7 +40,7 @@ def stride_arr(stride: int | tuple[int, ...], arr: np.ndarray):
         stride = (stride,) * (ndim - 1)
 
     _idx = tuple(slice(None, None, st) for st in stride)
-    return arr[*_idx]
+    return arr[_idx]
 
 
 TA = TypeVar('TA', 'FixedVariableArray', NDArray[np.integer | np.floating])

{da4ml-0.3.0.dist-info → da4ml-0.3.1.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: da4ml
-Version: 0.3.0
+Version: 0.3.1
 Summary: Digital Arithmetic for Machine Learning
 Author-email: Chang Sun <chsun@cern.ch>
 License: GNU Lesser General Public License v3 (LGPLv3)

{da4ml-0.3.0.dist-info → da4ml-0.3.1.dist-info}/RECORD

@@ -1,5 +1,5 @@
 da4ml/__init__.py,sha256=IETRRvzsJvPMLu1kzzi8UN5FYaM5MhNaXH2A_ZKr2_w,469
-da4ml/_version.py,sha256=AGmG_Lx0-9ztFw_7d9mYbaYuC-2abxE1oXOUNAY29YY,511
+da4ml/_version.py,sha256=lOWWIGJeBi0KkFopWU_n3GH71C1PsaZ-ZYDfxFkne6c,511
 da4ml/cmvm/__init__.py,sha256=4Tbt913k9zP0w8R1p6Oss06v5jrManbUhskyHl6e-U0,154
 da4ml/cmvm/api.py,sha256=JpecMt6g8zutGh_uWT61_0iX8TuXct7-jq7N7HMIsgA,9626
 da4ml/cmvm/types.py,sha256=hdthYdP5muIQ-9qFE0CjObGT7lCxB1-udXU16LxtuBI,20959
@@ -36,10 +36,10 @@ da4ml/codegen/verilog/__init__.py,sha256=rXmW2V9sDp2RYMDAWlhj_gfMXH3G5lPNmLrFtsJ
 da4ml/codegen/verilog/comb.py,sha256=CmCwiddeiT4TCZV088lF2ENlAXx3vjZKszTz1sYXEao,7614
 da4ml/codegen/verilog/io_wrapper.py,sha256=SSs-ZRhBVLR6tpFso8GNGk-FH6JDe-p7LPvVPjTspxo,5002
 da4ml/codegen/verilog/pipeline.py,sha256=YsPRTLp04Aofg33QMw6_ga3fNX9LeCD7Pq2PnERLWOg,2377
-da4ml/codegen/verilog/verilog_model.py,sha256=_50dggtH24xMdI0beuyvdsv8G8dlB4MWa1m8KWZQdNE,12295
+da4ml/codegen/verilog/verilog_model.py,sha256=3ZFaHqx1ONX3uxDKsbzLPxy3D7dehveRmdBfBiiS64o,12299
 da4ml/codegen/verilog/source/binder_util.hh,sha256=Dn9ysUdonw0HR8bxom8YfQF7vc1LEvT_B1V_o8Gw1rY,2503
 da4ml/codegen/verilog/source/build_binder.mk,sha256=rQbI98itE_b1wIQ_0uCXfBzNmGK2XT4vWmRyCJNnPKk,960
-da4ml/codegen/verilog/source/build_prj.tcl,sha256=bcFCpcHR26TJGOQZEpUx0eM1SEiJOCoH-9EPpIvqWu0,3124
+da4ml/codegen/verilog/source/build_prj.tcl,sha256=JA-zLl7fd2PV-BFaX22-MTex04QTi0urWUXNAEUDTy0,3003
 da4ml/codegen/verilog/source/ioutil.hh,sha256=1o1-oIyQyYc9CU91bBxuitVzzcrNT8p4MTarFKiJoG4,3967
 da4ml/codegen/verilog/source/mux.v,sha256=1PMSQKGR_Cku1EQnePBVCuX6we_dqYBXW54WBEURvs0,1928
 da4ml/codegen/verilog/source/negative.v,sha256=YphTCLnYslktsnCPq1xjbYgIFavani5NBbqs20uwhBI,688
@@ -47,18 +47,18 @@ da4ml/codegen/verilog/source/shift_adder.v,sha256=qrpXBX9bhHI-o75v5zshOfq0giEATv
 da4ml/codegen/verilog/source/template.xdc,sha256=GlSRy8tw_orohSuUwUSNEYJLLkAAHttGTfLTcQqRQDg,1262
 da4ml/converter/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 da4ml/converter/hgq2/parser.py,sha256=bAtnEXQxRKU9a1HFJWTy-e_HDzZY_wXOBVdyYG3ndsM,3826
-da4ml/converter/hgq2/replica.py,sha256=9ICJGfK2Q2C_glwE0KMcvXttuWvJYRblkO7RLmalzss,13829
+da4ml/converter/hgq2/replica.py,sha256=VzasMOasU73ZQr0xH2e8uOeKVFX_Is0n9aZFscGKcik,13864
 da4ml/trace/__init__.py,sha256=dv-rti3t8iE0RqeThfOb40mAg8FZB2WkkGQq3enJft0,282
 da4ml/trace/fixed_variable.py,sha256=6dfMHBN1NfqYIbPZ79GCPCXj2JFQUKTyDZu6xDaG3rg,17082
 da4ml/trace/fixed_variable_array.py,sha256=A0ApTvZxpkr7kHrUQkyhrGJuuPe4kDgLFyD_1CW7lBk,10985
 da4ml/trace/pipeline.py,sha256=_R2uqWgnpuQ4tD7VKz2eu8CF9Air2RtYH2o03Vfg0Mk,5353
 da4ml/trace/tracer.py,sha256=NqPEH9hyVlGQOf9_kJL3A7SujCcxkT-z28bk0Ael5jE,5664
 da4ml/trace/ops/__init__.py,sha256=I4VqB43lVkFlLtkoWxiSDHBFGvxKwutNbAJw5aLVeAI,2108
-da4ml/trace/ops/conv_utils.py,sha256=P8ccpeHF5D0jY9LdkIfwui3HNs-WpTnGfwiYehtboCU,8246
+da4ml/trace/ops/conv_utils.py,sha256=Yn73t4F6Tcs1hBwK08L1DPOin2HYVcng4PSkU4vuZFo,8245
 da4ml/trace/ops/einsum_utils.py,sha256=MoWvOfvtVjXGwqEhXEzZ3uGrgSmLTHngV8I1eLyANGE,11433
 da4ml/trace/ops/reduce_utils.py,sha256=8gohGQRVr8Bn5rfyrGsnE8EDxUXAObv521qu4mJrX9I,3348
-da4ml-0.3.0.dist-info/licenses/LICENSE,sha256=46mU2C5kSwOnkqkw9XQAJlhBL2JAf1_uCD8lVcXyMRg,7652
-da4ml-0.3.0.dist-info/METADATA,sha256=JVugmlP6dRkZ8PZTOisE6OZ3JaNNjm18yKAUBDZC04s,4569
-da4ml-0.3.0.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
-da4ml-0.3.0.dist-info/top_level.txt,sha256=N0tnKVwRqFiffFdeAzCgFq71hUNySh5-ITbNd6-R58Q,6
-da4ml-0.3.0.dist-info/RECORD,,
+da4ml-0.3.1.dist-info/licenses/LICENSE,sha256=46mU2C5kSwOnkqkw9XQAJlhBL2JAf1_uCD8lVcXyMRg,7652
+da4ml-0.3.1.dist-info/METADATA,sha256=3H1yt5sKqrIncAGok6NqE27O66_yD7hPUN6jFmCdMqQ,4569
+da4ml-0.3.1.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
+da4ml-0.3.1.dist-info/top_level.txt,sha256=N0tnKVwRqFiffFdeAzCgFq71hUNySh5-ITbNd6-R58Q,6
+da4ml-0.3.1.dist-info/RECORD,,