da4ml 0.1.1__py3-none-any.whl → 0.2.0__py3-none-any.whl

da4ml/codegen/verilog/io_wrapper.py

@@ -0,0 +1,255 @@
+from itertools import accumulate
+
+from ...cmvm.types import CascadedSolution, QInterval, Solution, _minimal_kif
+
+
+def hetero_io_map(qints: list[QInterval], merge: bool = False):
+    N = len(qints)
+    ks, _is, fs = zip(*map(_minimal_kif, qints))
+    Is = [_i + _k for _i, _k in zip(_is, ks)]
+    max_I, max_f = max(Is), max(fs)
+    max_bw = max_I + max_f
+    width_regular, width_packed = max_bw * N, sum(Is) + sum(fs)
+
+    regular: list[tuple[int, int]] = []
+    pads: list[tuple[int, int, int]] = []
+
+    bws = [I + f for I, f in zip(Is, fs)]
+    _bw = list(accumulate([0] + bws))
+    hetero = [(i - 1, j) for i, j in zip(_bw[1:], _bw[:-1])]
+
+    for i in range(N):
+        base = max_bw * i
+        bias_low = max_f - fs[i]
+        bias_high = max_I - Is[i]
+        low = base + bias_low
+        high = (base + max_bw - 1) - bias_high
+        regular.append((high, low))
+
+        if bias_low != 0:
+            pads.append((base + bias_low - 1, base, -1))
+        if bias_high != 0:
+            copy_from = hetero[i][0] if ks[i] else -1
+            pads.append((base + max_bw - 1, base + max_bw - bias_high, copy_from))
+
+    if not merge:
+        return regular, hetero, pads, (width_regular, width_packed)
+
+    # Merging consecutive intervals when possible
+    for i in range(N - 2, -1, -1):
+        this_high = regular[i][0]
+        next_low = regular[i + 1][1]
+        if next_low - this_high != 1:
+            continue
+        regular[i] = (regular[i + 1][0], regular[i][1])
+        regular.pop(i + 1)
+        hetero[i] = (hetero[i + 1][0], hetero[i][1])
+        hetero.pop(i + 1)
+
+    for i in range(len(pads) - 2, -1, -1):
+        if pads[i + 1][1] - pads[i][0] == 1 and pads[i][2] == pads[i + 1][2]:
+            pads[i] = (pads[i + 1][0], pads[i][1], pads[i][2])
+            pads.pop(i + 1)
+
+    return regular, hetero, pads, (width_regular, width_packed)
+
+
+def generate_io_wrapper(sol: Solution | CascadedSolution, module_name: str, pipelined: bool = False):
+    reg_in, het_in, _, shape_in = hetero_io_map(sol.inp_qint, merge=True)
+    reg_out, het_out, pad_out, shape_out = hetero_io_map(sol.out_qint, merge=True)
+
+    w_reg_in, w_het_in = shape_in
+    w_reg_out, w_het_out = shape_out
+
+    inp_assignment = [f'assign packed_inp[{ih}:{jh}] = inp[{ir}:{jr}];' for (ih, jh), (ir, jr) in zip(het_in, reg_in)]
+    _out_assignment: list[tuple[int, str]] = []
+
+    for i, ((ih, jh), (ir, jr)) in enumerate(zip(het_out, reg_out)):
+        _out_assignment.append((ih, f'assign out[{ir}:{jr}] = packed_out[{ih}:{jh}];'))
+
+    for i, (i, j, copy_from) in enumerate(pad_out):
+        n_bit = i - j + 1
+        pad = f"{n_bit}'b0" if copy_from == -1 else f'{{{n_bit}{{packed_out[{copy_from}]}}}}'
+        _out_assignment.append((i, f'assign out[{i}:{j}] = {pad};'))
+    _out_assignment.sort(key=lambda x: x[0])
+    out_assignment = [v for _, v in _out_assignment]
+
+    inp_assignment_str = '\n    '.join(inp_assignment)
+    out_assignment_str = '\n    '.join(out_assignment)
+
+    clk_and_rst_inp, clk_and_rst_bind = '', ''
+    if pipelined:
+        clk_and_rst_inp = '\n   input clk,'
+        clk_and_rst_bind = '\n        .clk(clk),'
+
+    return f"""`timescale 1 ns / 1 ps
+
+module {module_name}_wrapper ({clk_and_rst_inp}
+    // verilator lint_off UNUSEDSIGNAL
+    input [{w_reg_in-1}:0] inp,
+    // verilator lint_on UNUSEDSIGNAL
+    output [{w_reg_out-1}:0] out
+);
+    wire [{w_het_in-1}:0] packed_inp;
+    wire [{w_het_out-1}:0] packed_out;
+
+    {inp_assignment_str}
+
+    {module_name} op ({clk_and_rst_bind}
+        .inp(packed_inp),
+        .out(packed_out)
+    );
+
+    {out_assignment_str}
+
+endmodule
+"""
+
+
+def comb_binder_gen(sol: Solution, module_name: str):
+    k_in, i_in, f_in = zip(*map(_minimal_kif, sol.inp_qint))
+    k_out, i_out, f_out = zip(*map(_minimal_kif, sol.out_qint))
+    max_inp_bw = max(k + i for k, i in zip(k_in, i_in)) + max(f_in)
+    max_out_bw = max(k + i for k, i in zip(k_out, i_out)) + max(f_out)
+
+    n_in, n_out = sol.shape
+    return f"""#include "V{module_name}.h"
+#include "ioutils.hh"
+#include <verilated.h>
+
+#ifdef _OPENMP
+#include <omp.h>
+constexpr bool _openmp = true;
+#else
+constexpr bool _openmp = false;
+#endif
+
+constexpr size_t N_inp = {n_in};
+constexpr size_t N_out = {n_out};
+constexpr size_t max_inp_bw = {max_inp_bw};
+constexpr size_t max_out_bw = {max_out_bw};
+typedef V{module_name} dut_t;
+
+extern "C" {{
+
+bool openmp_enabled() {{
+    return _openmp;
+}}
+
+void _inference(int32_t *c_inp, int32_t *c_out, size_t n_samples) {{
+    dut_t *dut = new dut_t;
+
+    for (size_t i = 0; i < n_samples; ++i) {{
+        write_input<N_inp, max_inp_bw>(dut->inp, &c_inp[i * N_inp]);
+        dut->eval();
+        read_output<N_out, max_out_bw>(dut->out, &c_out[i * N_out]);
+    }}
+
+    dut->final();
+    delete dut;
+}}
+
+void inference(int32_t *c_inp, int32_t *c_out, size_t n_samples) {{
+    size_t n_max_threads = omp_get_max_threads();
+    size_t n_samples_per_thread = std::max<size_t>(n_samples / n_max_threads, 32);
+    size_t n_thread = n_samples / n_samples_per_thread;
+    n_thread += (n_samples % n_samples_per_thread) ? 1 : 0;
+
+    #ifdef _OPENMP
+    #pragma omp parallel for num_threads(n_thread) schedule(static)
+    for (size_t i = 0; i < n_thread; ++i) {{
+        size_t start = i * n_samples_per_thread;
+        size_t end = std::min<size_t>(start + n_samples_per_thread, n_samples);
+        size_t n_samples_this_thread = end - start;
+
+        _inference(&c_inp[start * N_inp], &c_out[start * N_out], n_samples_this_thread);
+    }}
+    #else
+    _inference(c_inp, c_out, n_samples);
+    #endif
+}}
+}}"""
+
+
+def pipeline_binder_gen(csol: CascadedSolution, module_name: str, II: int = 1):
+    k_in, i_in, f_in = zip(*map(_minimal_kif, csol.inp_qint))
+    k_out, i_out, f_out = zip(*map(_minimal_kif, csol.out_qint))
+    max_inp_bw = max(k + i for k, i in zip(k_in, i_in)) + max(f_in)
+    max_out_bw = max(k + i for k, i in zip(k_out, i_out)) + max(f_out)
+
+    n_stage = len(csol.solutions)
+
+    n_in, n_out = csol.shape
+    return f"""#include "V{module_name}.h"
+#include "ioutils.hh"
+#include <verilated.h>
+
+#ifdef _OPENMP
+#include <omp.h>
+constexpr bool _openmp = true;
+#else
+constexpr bool _openmp = false;
+#endif
+
+constexpr size_t N_inp = {n_in};
+constexpr size_t N_out = {n_out};
+constexpr size_t max_inp_bw = {max_inp_bw};
+constexpr size_t max_out_bw = {max_out_bw};
+constexpr size_t II = {II};
+constexpr size_t latency = {n_stage};
+typedef V{module_name} dut_t;
+
+extern "C" {{
+
+bool openmp_enabled() {{
+    return _openmp;
+}}
+
+void _inference(int32_t *c_inp, int32_t *c_out, size_t n_samples) {{
+    dut_t *dut = new dut_t;
+
+    size_t clk_req = n_samples * II + latency + 1;
+
+    for (size_t t_inp = 0; t_inp < clk_req; ++t_inp) {{
+        size_t t_out = t_inp - latency - 1;
+
+        if (t_inp < n_samples * II && t_inp % II == 0) {{
+            write_input<N_inp, max_inp_bw>(dut->inp, &c_inp[t_inp / II * N_inp]);
+        }}
+
+        dut->clk = 0;
+        dut->eval();
+
+        if (t_inp > latency && t_out % II == 0) {{
+            read_output<N_out, max_out_bw>(dut->out, &c_out[t_out / II * N_out]);
+        }}
+
+        dut->clk = 1;
+        dut->eval();
+    }}
+
+    dut->final();
+    delete dut;
+}}
+
+void inference(int32_t *c_inp, int32_t *c_out, size_t n_samples) {{
+#ifdef _OPENMP
+    size_t n_max_threads = omp_get_max_threads();
+    size_t n_samples_per_thread = std::max<size_t>(n_samples / n_max_threads, 32);
+    size_t n_thread = n_samples / n_samples_per_thread;
+    n_thread += (n_samples % n_samples_per_thread) ? 1 : 0;
+
+    #pragma omp parallel for num_threads(n_thread) schedule(static)
+    for (size_t i = 0; i < n_thread; ++i) {{
+        size_t start = i * n_samples_per_thread;
+        size_t end = std::min<size_t>(start + n_samples_per_thread, n_samples);
+        size_t n_samples_this_thread = end - start;
+
+        _inference(&c_inp[start * N_inp], &c_out[start * N_out], n_samples_this_thread);
+    }}
+#else
+    _inference(c_inp, c_out, n_samples);
+#endif
+}}
+
+}}"""

da4ml/codegen/verilog/pipeline.py

@@ -0,0 +1,49 @@
+from ...cmvm.types import CascadedSolution, _minimal_kif
+from .comb import comb_logic_gen
+
+
+def pipeline_logic_gen(
+    csol: CascadedSolution, name: str, print_latency=False, timescale: str | None = '`timescale 1 ns / 1 ps', reset_high=True
+):
+    N = len(csol.solutions)
+    inp_bits = [sum(map(sum, map(_minimal_kif, sol.inp_qint))) for sol in csol.solutions]
+    out_bits = inp_bits[1:] + [sum(map(sum, map(_minimal_kif, csol.out_qint)))]
+
+    registers = [f'reg [{width}-1:0] stage{i}_inp;' for i, width in enumerate(inp_bits)]
+    wires = [f'wire [{width}-1:0] stage{i}_out;' for i, width in enumerate(out_bits)]
+
+    comb_logic = [f'{name}_stage{i} stage{i} (.inp(stage{i}_inp), .out(stage{i}_out));' for i in range(N)]
+
+    serial_logic = ['stage0_inp <= inp;']
+    serial_logic += [f'stage{i}_inp <= stage{i-1}_out;' for i in range(1, N)]
+    serial_logic += [f'out <= stage{N-1}_out;']
+
+    sep0 = '\n    '
+    sep1 = '\n        '
+
+    module = f"""module {name} (
+    input clk,
+    input [{inp_bits[0]-1}:0] inp,
+    output reg [{out_bits[-1]-1}:0] out
+);
+
+    {sep0.join(registers)}
+    {sep0.join(wires)}
+
+    {sep0.join(comb_logic)}
+
+    always @(posedge clk) begin
+        {sep1.join(serial_logic)}
+    end
+endmodule
+"""
+
+    if timescale:
+        module = f'{timescale}\n\n{module}'
+
+    ret: dict[str, str] = {}
+    for i, s in enumerate(csol.solutions):
+        stage_name = f'{name}_stage{i}'
+        ret[stage_name] = comb_logic_gen(s, stage_name, print_latency=print_latency, timescale=timescale)
+    ret[name] = module
+    return ret

da4ml/codegen/verilog/source/build_binder.mk

@@ -0,0 +1,27 @@
+default: slow
+
+VERILATOR_ROOT = $(shell verilator -V | grep -a VERILATOR_ROOT | tail -1 | awk '{{print $$3}}')
+INCLUDES = -I./obj_dir -I$(VERILATOR_ROOT)/include
+WARNINGS = -Wl,--no-undefined
+CFLAGS = -std=c++17 -fPIC
+LINKFLAGS = $(INCLUDES) $(WARNINGS)
+LIBNAME = lib$(VM_PREFIX)_$(STAMP).so
+N_JOBS ?= $(shell nproc)
+
+
+./obj_dir/libV$(VM_PREFIX).a ./obj_dir/libverilated.a ./obj_dir/V$(VM_PREFIX)__ALL.a: $(VM_PREFIX).v
+	verilator --cc -j $(N_JOBS) -Wall -build $(VM_PREFIX).v --prefix V$(VM_PREFIX) -CFLAGS "$(CFLAGS)"
+
+$(LIBNAME): ./obj_dir/libV$(VM_PREFIX).a ./obj_dir/libverilated.a ./obj_dir/V$(VM_PREFIX)__ALL.a $(VM_PREFIX)_binder.cc
+	$(CXX) $(CFLAGS) $(LINKFLAGS) $(CXXFLAGS2) -pthread -shared -o $(LIBNAME) $(VM_PREFIX)_binder.cc ./obj_dir/libV$(VM_PREFIX).a ./obj_dir/libverilated.a ./obj_dir/V$(VM_PREFIX)__ALL.a $(EXTRA_CXXFLAGS)
+
+
+fast: CFLAGS += -O3
+fast: $(LIBNAME)
+
+slow: CFLAGS += -O
+slow: $(LIBNAME)
+
+clean:
+	rm -rf obj_dir
+	rm -f $(LIBNAME)

da4ml/codegen/verilog/source/build_prj.tcl

@@ -0,0 +1,75 @@
+set project_name "${PROJECT_NAME}"
+set device "${DEVICE}"
+
+set top_module "${project_name}_wrapper"
+set output_dir "./output_${project_name}"
+
+create_project $project_name "${output_dir}/$project_name" -force -part $device
+
+set_property TARGET_LANGUAGE Verilog [current_project]
+set_property DEFAULT_LIB work [current_project]
+
+read_verilog "${project_name}_wrapper.v"
+read_verilog "${project_name}.v"
+read_verilog "shift_adder.v"
+foreach file [glob -nocomplain "${project_name}_stage*.v"] {
+    read_verilog $file
+}
+
+read_xdc "${project_name}.xdc" -mode out_of_context
+
+set_property top $top_module [current_fileset]
+
+file mkdir $output_dir
+file mkdir "${output_dir}/reports"
+
+# synth
+synth_design -top $top_module -mode out_of_context -retiming \
+    -flatten_hierarchy rebuilt -resource_sharing auto \
+    -keep_equivalent_registers -shreg_min_size 8 \
+    -directive AlternateRoutability
+
+write_checkpoint -force "${output_dir}/${project_name}_post_synth.dcp"
+
+report_timing_summary -file "${output_dir}/reports/${project_name}_post_synth_timing.rpt"
+report_power -file "${output_dir}/reports/${project_name}_post_synth_power.rpt"
+report_utilization -file "${output_dir}/reports/${project_name}_post_synth_util.rpt"
+
+# set_property CARRY_REMAP 3 [get_cells -hier -filter {ref_name == CARRY8}]
+
+opt_design -directive ExploreSequentialArea
+opt_design -directive ExploreWithRemap
+
+report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_opt_congestion.rpt"
+
+# place
+place_design -directive AltSpreadLogic_high -fanout_opt
+report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_place_congestion_initial.rpt"
+
+phys_opt_design -directive AggressiveExplore
+write_checkpoint -force "${output_dir}/${project_name}_post_place.dcp"
+
+report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_place_congestion_final.rpt"
+
+report_timing_summary -file "${output_dir}/reports/${project_name}_post_place_timing.rpt"
+report_utilization -hierarchical -file "${output_dir}/reports/${project_name}_post_place_util.rpt"
+
+# route
+route_design -directive NoTimingRelaxation
+write_checkpoint -force "${output_dir}/${project_name}_post_route.dcp"
+
+
+report_timing_summary -file "${output_dir}/reports/${project_name}_post_route_timing.rpt"
+report_timing -sort_by group -max_paths 100 -path_type summary -file "${output_dir}/reports/${project_name}_post_route_timing_paths.rpt"
+report_clock_utilization -file "${output_dir}/reports/${project_name}_post_route_clock_util.rpt"
+report_utilization -file "${output_dir}/reports/${project_name}_post_route_util.rpt"
+report_power -file "${output_dir}/reports/${project_name}_post_route_power.rpt"
+report_drc -file "${output_dir}/reports/${project_name}_post_route_drc.rpt"
+
+report_utilization -format xml -hierarchical -file "${output_dir}/reports/${project_name}_post_route_util.xml"
+report_power -xpe "${output_dir}/reports/${project_name}_post_route_power.xml"
+
+# Generate Verilog netlist for simulation
+# write_verilog -force "${output_dir}/${project_name}_impl_netlist.v" -mode timesim -sdf_anno true
+
+puts "Implementation complete. Results saved in ${output_dir}"

da4ml/codegen/verilog/source/ioutils.hh

@@ -0,0 +1,117 @@
+#include "verilated.h"
+#include <cassert>
+#include <cstdint>
+#include <vector>
+template <size_t bw, size_t N_in> std::vector<int32_t> bitpack(const int32_t *values) {
+    static_assert(bw > 0 && bw <= 32, "Bit width must be between 1 and 32");
+
+    constexpr size_t total_bits = N_in * bw;
+    constexpr size_t result_size = (total_bits + 31) / 32;
+    std::vector<int32_t> result(result_size, 0);
+
+    constexpr uint32_t mask = (bw == 32) ? 0xFFFFFFFF : ((1U << bw) - 1);
+
+    size_t bit_pos = 0;
+    for (size_t i = 0; i < N_in; i++) {
+        int32_t val = values[i];
+        uint32_t bits = val & mask;
+
+        size_t result_idx = bit_pos / 32;
+        size_t offset = bit_pos % 32;
+
+        // base case
+        result[result_idx] |= (bits << offset);
+
+        // cross boundary case
+        if (offset + bw > 32 && result_idx + 1 < result.size()) {
+            result[result_idx + 1] |= (bits >> (32 - offset));
+        }
+
+        bit_pos += bw;
+    }
+
+    return result;
+}
+
+template <size_t bw, size_t N_out> std::vector<int32_t> bitunpack(const std::vector<int32_t> &packed) {
+    static_assert(bw > 0 && bw <= 32, "Bit width must be between 1 and 32");
+
+    constexpr size_t total_bits = N_out * bw;
+    constexpr size_t packed_size = (total_bits + 31) / 32;
+    assert(packed.size() == packed_size);
+
+    std::vector<int32_t> result(N_out, 0);
+
+    for (size_t i = 0; i < N_out; i++) {
+        size_t bit_pos = i * bw;
+        size_t packed_idx = bit_pos / 32;
+        size_t offset = bit_pos % 32;
+
+        // base case
+        size_t bw_v0 = std::min(bw, 32 - offset);
+        uint32_t mask = bw_v0 == 32 ? 0xFFFFFFFF : ((1U << bw_v0) - 1);
+        int32_t value = (packed[packed_idx] >> offset) & mask;
+
+        // cross boundary
+        if (offset + bw > 32) {
+            assert(packed_idx + 1 < packed.size());
+            size_t bw_v1 = offset + bw - 32;
+            uint32_t mask_v1 = ((1U << bw_v1) - 1);
+            uint32_t additional_bits = packed[packed_idx + 1] & mask_v1;
+            value |= (additional_bits << bw_v0);
+        }
+
+        result[i] = value;
+    }
+
+    return result;
+}
+
+template <size_t bits_in, typename inp_buf_t>
+std::enable_if_t<std::is_integral_v<inp_buf_t>, void> _write_input(inp_buf_t &inp_buf, const std::vector<int32_t> &input) {
+    assert(input.size() == (bits_in + 31) / 32);
+    inp_buf = input[0] & 0xFFFFFFFF;
+    if (bits_in > 32) {
+        inp_buf |= static_cast<int64_t>(input[1]) << 32;
+    }
+}
+
+template <size_t bits_in, size_t N_in> void _write_input(VlWide<N_in> &inp_buf, const std::vector<int32_t> &input) {
+    assert(input.size() == (bits_in + 31) / 32);
+    for (size_t i = 0; i < input.size(); ++i) {
+        inp_buf[i] = input[i];
+    }
+}
+
+template <size_t bits_out, typename out_buf_t>
+std::enable_if_t<std::is_integral_v<out_buf_t>, std::vector<int32_t>> _read_output(out_buf_t &out_buf) {
+    std::vector<int32_t> output((bits_out + 31) / 32);
+    output[0] = out_buf & 0xFFFFFFFF;
+    if (bits_out > 32) {
+        output[1] = (out_buf >> 32) & 0xFFFFFFFF;
+    }
+    return output;
+}
+
+template <size_t bits_out, size_t N_out> std::vector<int32_t> _read_output(VlWide<N_out> out_buf) {
+    std::vector<int32_t> output((bits_out + 31) / 32);
+    for (size_t i = 0; i < output.size(); ++i) {
+        output[i] = out_buf[i] & 0xFFFFFFFF;
+    }
+    return output;
+}
+
+template <size_t N, size_t max_bw, typename inp_buf_t> void write_input(inp_buf_t &inp_buf, const int32_t *c_inp) {
+    constexpr size_t bits_in = N * max_bw;
+    std::vector<int32_t> input = bitpack<max_bw, N>(c_inp);
+    _write_input<bits_in>(inp_buf, input);
+}
+
+template <size_t N, size_t max_bw, typename out_buf_t> void read_output(out_buf_t out_buf, int32_t *c_out) {
+    constexpr size_t bits_out = N * max_bw;
+    std::vector<int32_t> packed = _read_output<bits_out>(out_buf);
+    std::vector<int32_t> unpacked = bitunpack<max_bw, N>(packed);
+    for (size_t i = 0; i < N; ++i) {
+        c_out[i] = unpacked[i];
+    }
+}

da4ml/codegen/verilog/source/shift_adder.v

@@ -0,0 +1,56 @@
+`timescale 1ns / 1ps
+
+
+module shift_adder #(
+    parameter BW_INPUT0 = 32,
+    parameter BW_INPUT1 = 32,
+    parameter SIGNED0 = 0,
+    parameter SIGNED1 = 0,
+    parameter BW_OUT = 32,
+    parameter SHIFT1 = 0,
+    parameter IS_SUB = 0
+) (
+    input [BW_INPUT0-1:0] in0,
+    input [BW_INPUT1-1:0] in1,
+    output [BW_OUT-1:0] out
+);
+
+  localparam IN0_NEED_BITS = (SHIFT1 < 0) ? BW_INPUT0 - SHIFT1 : BW_INPUT0;
+  localparam IN1_NEED_BITS = (SHIFT1 > 0) ? BW_INPUT1 + SHIFT1 : BW_INPUT1;
+  localparam EXTRA_PAD = (SIGNED0 != SIGNED1) ? IS_SUB+1 : IS_SUB+0;
+  localparam BW_ADD = (IN0_NEED_BITS > IN1_NEED_BITS) ? IN0_NEED_BITS + EXTRA_PAD + 1 : IN1_NEED_BITS + EXTRA_PAD + 1;
+  localparam IN0_PAD_LEFT = (SHIFT1 < 0) ? BW_ADD - BW_INPUT0 + SHIFT1 : BW_ADD - BW_INPUT0;
+  localparam IN0_PAD_RIGHT = (SHIFT1 < 0) ? -SHIFT1 : 0;
+  localparam IN1_PAD_LEFT = (SHIFT1 > 0) ? BW_ADD - BW_INPUT1 - SHIFT1 : BW_ADD - BW_INPUT1;
+  localparam IN1_PAD_RIGHT = (SHIFT1 > 0) ? SHIFT1 : 0;
+
+  wire [BW_ADD-1:0] in0_ext;
+  wire [BW_ADD-1:0] in1_ext;
+
+  // verilator lint_off UNUSEDSIGNAL
+  wire [BW_ADD-1:0] accum;
+  // verilator lint_on UNUSEDSIGNAL
+
+  generate
+    if (SIGNED0 == 1) begin : in0_is_signed
+      assign in0_ext = {{IN0_PAD_LEFT{in0[BW_INPUT0-1]}}, in0, {IN0_PAD_RIGHT{1'b0}}};
+    end else begin : in0_is_unsigned
+      assign in0_ext = {{IN0_PAD_LEFT{1'b0}}, in0, {IN0_PAD_RIGHT{1'b0}}};
+    end
+    if (SIGNED1 == 1) begin : in1_is_signed
+      assign in1_ext = {{IN1_PAD_LEFT{in1[BW_INPUT1-1]}}, in1, {IN1_PAD_RIGHT{1'b0}}};
+    end else begin : in1_is_unsigned
+      assign in1_ext = {{IN1_PAD_LEFT{1'b0}}, in1, {IN1_PAD_RIGHT{1'b0}}};
+    end
+  endgenerate
+
+  generate
+    if (IS_SUB == 1) begin : is_sub
+      assign accum = in0_ext - in1_ext;
+    end else begin : is_add
+      assign accum = in0_ext + in1_ext;
+    end
+  endgenerate
+  assign out = accum[BW_OUT-1:0];
+
+endmodule

da4ml/codegen/verilog/source/template.xdc

@@ -0,0 +1,29 @@
+set clock_period ${CLOCK_PERIOD}
+
+# Clock uncertainty as percentage of clock period
+set uncertainty_setup_r ${UNCERTAINITY_SETUP}
+set uncertainty_hold_r ${UNCERTAINITY_HOLD}
+set delay_max_r ${DELAY_MAX}
+set delay_min_r ${DELAY_MIN}
+
+# Calculate actual uncertainty values
+set uncertainty_setup [expr {$clock_period * $uncertainty_setup_r}]
+set uncertainty_hold [expr {$clock_period * $uncertainty_hold_r}]
+set delay_max [expr {$clock_period * $delay_max_r}]
+set delay_min [expr {$clock_period * $delay_min_r}]
+
+# Create clock with variable period
+create_clock -period $clock_period -name sys_clk [get_ports {clk}]
+
+# Input/Output constraints
+set_input_delay -clock sys_clk -max $delay_max [get_ports {inp[*]}]
+set_input_delay -clock sys_clk -min $delay_min [get_ports {inp[*]}]
+
+set_output_delay -clock sys_clk -max $delay_max [get_ports {out[*]}]
+set_output_delay -clock sys_clk -min $delay_min [get_ports {out[*]}]
+
+# Apply calculated uncertainty values
+set_clock_uncertainty -setup $uncertainty_setup [get_clocks sys_clk]
+set_clock_uncertainty -hold $uncertainty_hold [get_clocks sys_clk]
+
+set_property HD.CLK_SRC BUFG_X0Y0 [get_ports clk]