cuequivariance-ops-cu12 0.8.1__py3-none-manylinux_2_24_aarch64.manylinux_2_28_aarch64.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- cuequivariance_ops/VERSION +1 -0
- cuequivariance_ops/__init__.py +42 -0
- cuequivariance_ops/_version.py +20 -0
- cuequivariance_ops/common/common.hpp +98 -0
- cuequivariance_ops/common/cudart.hpp +286 -0
- cuequivariance_ops/common/error.hpp +66 -0
- cuequivariance_ops/common/error_raft.hpp +323 -0
- cuequivariance_ops/common/nvtx.hpp +29 -0
- cuequivariance_ops/equivariance/batch_dimension.hh +15 -0
- cuequivariance_ops/equivariance/dtypes.hh +65 -0
- cuequivariance_ops/equivariance/fused_tensor_product.cuh +297 -0
- cuequivariance_ops/equivariance/indexed_linear.hh +41 -0
- cuequivariance_ops/equivariance/run_fmha.h +192 -0
- cuequivariance_ops/equivariance/run_fmha_cudafree.h +176 -0
- cuequivariance_ops/equivariance/run_fmha_sm100.h +135 -0
- cuequivariance_ops/equivariance/segmented_transpose.cuh +40 -0
- cuequivariance_ops/equivariance/tensor_product_uniform_1d_jit.hh +38 -0
- cuequivariance_ops/gpu_timing_kernels.hh +42 -0
- cuequivariance_ops/lib/libcue_ops.so +0 -0
- cuequivariance_ops/sleep.hh +40 -0
- cuequivariance_ops/triton/__init__.py +66 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_backward_pregemm_kernel_wrapper.10.0.json +37142 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_backward_pregemm_kernel_wrapper.12.0.json +37132 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_backward_pregemm_kernel_wrapper.8.0.json +37133 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_backward_pregemm_kernel_wrapper.8.6.json +37133 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_backward_pregemm_kernel_wrapper.8.9.json +37132 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_backward_pregemm_kernel_wrapper.9.0.json +74262 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_forward_kernel_wrapper.10.0.json +48482 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_forward_kernel_wrapper.12.0.json +55692 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_forward_kernel_wrapper.8.0.json +55693 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_forward_kernel_wrapper.8.6.json +55692 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_forward_kernel_wrapper.8.9.json +55693 -0
- cuequivariance_ops/triton/cache/fused_sigmoid_gated_dual_gemm_forward_kernel_wrapper.9.0.json +111382 -0
- cuequivariance_ops/triton/cache_manager.py +336 -0
- cuequivariance_ops/triton/fused_layer_norm_triton.py +546 -0
- cuequivariance_ops/triton/gated_gemm_triton.py +394 -0
- cuequivariance_ops/triton/pair_bias.py +365 -0
- cuequivariance_ops/triton/tuning_decorator.py +188 -0
- cuequivariance_ops/triton/utils.py +29 -0
- cuequivariance_ops_cu12-0.8.1.dist-info/METADATA +182 -0
- cuequivariance_ops_cu12-0.8.1.dist-info/RECORD +46 -0
- cuequivariance_ops_cu12-0.8.1.dist-info/WHEEL +6 -0
- cuequivariance_ops_cu12-0.8.1.dist-info/licenses/LICENSE +142 -0
- cuequivariance_ops_cu12-0.8.1.dist-info/licenses/Third_party_attr.txt +24 -0
- cuequivariance_ops_cu12-0.8.1.dist-info/sboms/auditwheel.cdx.json +1 -0
- cuequivariance_ops_cu12.libs/libnvfatbin-b51d3b3f.so.12.8.90 +0 -0
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# SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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# SPDX-License-Identifier: LicenseRef-NvidiaProprietary
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#
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# NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
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# property and proprietary rights in and to this material, related
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# documentation and any modifications thereto. Any use, reproduction,
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# disclosure or distribution of this material and related documentation
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# without an express license agreement from NVIDIA CORPORATION or
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# its affiliates is strictly prohibited.
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import triton
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import triton.language as tl
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from cuequivariance_ops.triton.utils import cvt_tf32_rn
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@triton.jit
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def fused_sigmoid_gated_dual_gemm_forward_kernel(
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# inputs
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x1_ptr,
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x2_ptr,
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w1_ptr,
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w2_ptr,
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b1_ptr,
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b2_ptr,
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mask_ptr,
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M,
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N,
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K,
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# outputs
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o_ptr,
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TILE_M: tl.constexpr,
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TILE_N: tl.constexpr,
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TILE_K: tl.constexpr,
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PRECISION: tl.constexpr,
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APPLY_MASK: tl.constexpr,
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TRANSPOSE_OUT: tl.constexpr,
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TWO_INPUTS: tl.constexpr,
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HAS_B1: tl.constexpr,
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HAS_B2: tl.constexpr,
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NEEDS_INT64: tl.constexpr = True,
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):
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# fully gated GEMM kernel with optional mask at the end
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pid_m = tl.program_id(axis=0)
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pid_n = tl.program_id(axis=1)
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if NEEDS_INT64:
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pid_m = tl.cast(pid_m, tl.int64)
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pid_n = tl.cast(pid_n, tl.int64)
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M = tl.cast(M, tl.int64)
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N = tl.cast(N, tl.int64)
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start_m = pid_m * TILE_M
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start_n = pid_n * TILE_N
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offs_xm = start_m + tl.arange(0, TILE_M)
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offs_wn = start_n + tl.arange(0, TILE_N)
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offs_k = tl.arange(0, TILE_K)
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x1_ptrs = x1_ptr + (offs_xm[:, None] * K + offs_k[None, :])
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if TWO_INPUTS:
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x2_ptrs = x2_ptr + (offs_xm[:, None] * K + offs_k[None, :])
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w_tile_offs = offs_wn[None, :] * K + offs_k[:, None]
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acc_1 = tl.zeros((TILE_M, TILE_N), dtype=tl.float32)
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acc_2 = tl.zeros((TILE_M, TILE_N), dtype=tl.float32)
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mask_m = offs_xm < M
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if TWO_INPUTS:
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for _ in range(0, tl.cdiv(K, TILE_K)):
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x1 = tl.load(x1_ptrs, mask=mask_m[:, None], other=0.0).to(
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w1_ptr.type.element_ty
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)
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w1_ptrs = w1_ptr + w_tile_offs
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w1 = tl.load(w1_ptrs)
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if PRECISION == 0:
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acc_1 = tl.dot(x1, w1, acc_1)
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elif PRECISION == 1:
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x1 = cvt_tf32_rn(x1)
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w1 = cvt_tf32_rn(w1)
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acc_1 = tl.dot(x1, w1, acc_1, input_precision="tf32")
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elif PRECISION == 2:
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acc_1 = tl.dot(x1, w1, acc_1, input_precision="tf32x3")
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elif PRECISION == 3:
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acc_1 = tl.dot(x1, w1, acc_1, input_precision="ieee")
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else:
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tl.static_assert(
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False,
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"PRECISION must be 0 (default), 1 (tf32), 2 (tf32x3) or 3 (ieee)",
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)
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x1_ptrs += TILE_K
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w1_ptr += TILE_K
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for _ in range(0, tl.cdiv(K, TILE_K)):
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x2 = tl.load(x2_ptrs, mask=mask_m[:, None], other=0.0).to(
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w2_ptr.type.element_ty
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)
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w2_ptrs = w2_ptr + w_tile_offs
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w2 = tl.load(w2_ptrs)
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if PRECISION == 0:
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acc_2 = tl.dot(x2, w2, acc_2)
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elif PRECISION == 1:
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x2 = cvt_tf32_rn(x2)
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w2 = cvt_tf32_rn(w2)
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acc_2 = tl.dot(x2, w2, acc_2, input_precision="tf32")
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elif PRECISION == 2:
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acc_2 = tl.dot(x2, w2, acc_2, input_precision="tf32x3")
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elif PRECISION == 3:
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acc_2 = tl.dot(x2, w2, acc_2, input_precision="ieee")
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else:
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tl.static_assert(
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False,
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"PRECISION must be 0 (default), 1 (tf32), 2 (tf32x3) or 3 (ieee)",
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)
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x2_ptrs += TILE_K
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w2_ptr += TILE_K
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else:
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for _ in range(0, tl.cdiv(K, TILE_K)):
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x = tl.load(x1_ptrs, mask=mask_m[:, None], other=0.0).to(
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w1_ptr.type.element_ty
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)
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w1_ptrs = w1_ptr + w_tile_offs
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w1 = tl.load(w1_ptrs)
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if PRECISION == 0:
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acc_1 = tl.dot(x, w1, acc_1)
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elif PRECISION == 1:
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x = cvt_tf32_rn(x)
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w1 = cvt_tf32_rn(w1)
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acc_1 = tl.dot(x, w1, acc_1, input_precision="tf32")
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elif PRECISION == 2:
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acc_1 = tl.dot(x, w1, acc_1, input_precision="tf32x3")
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elif PRECISION == 3:
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acc_1 = tl.dot(x, w1, acc_1, input_precision="ieee")
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else:
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tl.static_assert(
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False,
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"PRECISION must be 0 (default), 1 (tf32), 2 (tf32x3) or 3 (ieee)",
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)
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w2_ptrs = w2_ptr + w_tile_offs
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w2 = tl.load(w2_ptrs)
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if PRECISION == 0:
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acc_2 = tl.dot(x, w2, acc_2)
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elif PRECISION == 1:
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x = cvt_tf32_rn(x)
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w2 = cvt_tf32_rn(w2)
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acc_2 = tl.dot(x, w2, acc_2, input_precision="tf32")
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elif PRECISION == 2:
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acc_2 = tl.dot(x, w2, acc_2, input_precision="tf32x3")
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elif PRECISION == 3:
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acc_2 = tl.dot(x, w2, acc_2, input_precision="ieee")
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else:
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tl.static_assert(
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False,
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"PRECISION must be 0 (default), 1 (tf32), 2 (tf32x3) or 3 (ieee)",
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)
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x1_ptrs += TILE_K
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w1_ptr += TILE_K
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w2_ptr += TILE_K
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offs_om = pid_m * TILE_M + tl.arange(0, TILE_M)
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offs_on = pid_n * TILE_N + tl.arange(0, TILE_N)
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if HAS_B1:
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b1_ptrs = b1_ptr + offs_on
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b1_tile = tl.load(b1_ptrs).to(tl.float32)
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acc_1 += b1_tile
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if HAS_B2:
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b2_ptrs = b2_ptr + offs_on
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b2_tile = tl.load(b2_ptrs).to(tl.float32)
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acc_2 += b2_tile
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acc_1 = 1.0 / (1.0 + tl.exp(-acc_1))
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acc_gated = acc_1 * acc_2
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if APPLY_MASK:
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mask = tl.load(mask_ptr + offs_om, mask=mask_m, other=0.0).to(tl.float32)
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acc_gated = acc_gated * mask[:, None]
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if TRANSPOSE_OUT:
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o_ptrs = o_ptr + offs_on[None, :] * M + offs_om[:, None]
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else:
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o_ptrs = o_ptr + offs_om[:, None] * N + offs_on[None, :]
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o_mask = offs_om[:, None] < M
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tl.store(o_ptrs, acc_gated, mask=o_mask)
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@triton.jit
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def fused_sigmoid_gated_dual_gemm_backward_pregemm_kernel(
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# inputs
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grad_o_ptr,
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x1_ptr,
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x2_ptr,
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w1_ptr,
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w2_ptr,
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b1_ptr,
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b2_ptr,
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mask_ptr,
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M,
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N,
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K,
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# outputs
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grad_xw1_ptr,
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grad_xw2_ptr,
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grad_mask_ptr,
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TILE_M: tl.constexpr,
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TILE_N: tl.constexpr,
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TILE_K: tl.constexpr,
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PRECISION: tl.constexpr,
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APPLY_MASK: tl.constexpr,
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TRANSPOSE_OUT: tl.constexpr,
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TWO_INPUTS: tl.constexpr,
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HAS_B1: tl.constexpr,
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HAS_B2: tl.constexpr,
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NEEDS_INT64: tl.constexpr = True,
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):
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# fully gated GEMM kernel with optional mask at the end
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pid_m = tl.program_id(axis=0)
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pid_n = tl.program_id(axis=1)
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if NEEDS_INT64:
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pid_m = tl.cast(pid_m, tl.int64)
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pid_n = tl.cast(pid_n, tl.int64)
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M = tl.cast(M, tl.int64)
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N = tl.cast(N, tl.int64)
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start_m = pid_m * TILE_M
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start_n = pid_n * TILE_N
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offs_xm = start_m + tl.arange(0, TILE_M)
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offs_wn = start_n + tl.arange(0, TILE_N)
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offs_k = tl.arange(0, TILE_K)
|
|
243
|
+
|
|
244
|
+
x1_ptrs = x1_ptr + (offs_xm[:, None] * K + offs_k[None, :])
|
|
245
|
+
if TWO_INPUTS:
|
|
246
|
+
x2_ptrs = x2_ptr + (offs_xm[:, None] * K + offs_k[None, :])
|
|
247
|
+
w_tile_offs = offs_wn[None, :] * K + offs_k[:, None]
|
|
248
|
+
|
|
249
|
+
acc_1 = tl.zeros((TILE_M, TILE_N), dtype=tl.float32)
|
|
250
|
+
acc_2 = tl.zeros((TILE_M, TILE_N), dtype=tl.float32)
|
|
251
|
+
|
|
252
|
+
mask_m = offs_xm < M
|
|
253
|
+
|
|
254
|
+
if TWO_INPUTS:
|
|
255
|
+
# recompute acc1 and acc2
|
|
256
|
+
for _ in range(0, tl.cdiv(K, TILE_K)):
|
|
257
|
+
x1 = tl.load(x1_ptrs, mask=mask_m[:, None], other=0.0).to(
|
|
258
|
+
w1_ptr.type.element_ty
|
|
259
|
+
)
|
|
260
|
+
w1_ptrs = w1_ptr + w_tile_offs
|
|
261
|
+
w1 = tl.load(w1_ptrs)
|
|
262
|
+
|
|
263
|
+
if PRECISION == 0:
|
|
264
|
+
acc_1 = tl.dot(x1, w1, acc_1)
|
|
265
|
+
elif PRECISION == 1:
|
|
266
|
+
x1 = cvt_tf32_rn(x1)
|
|
267
|
+
w1 = cvt_tf32_rn(w1)
|
|
268
|
+
acc_1 = tl.dot(x1, w1, acc_1, input_precision="tf32")
|
|
269
|
+
elif PRECISION == 2:
|
|
270
|
+
acc_1 = tl.dot(x1, w1, acc_1, input_precision="tf32x3")
|
|
271
|
+
elif PRECISION == 3:
|
|
272
|
+
acc_1 = tl.dot(x1, w1, acc_1, input_precision="ieee")
|
|
273
|
+
else:
|
|
274
|
+
tl.static_assert(
|
|
275
|
+
False,
|
|
276
|
+
"PRECISION must be 0 (default), 1 (tf32), 2 (tf32x3) or 3 (ieee)",
|
|
277
|
+
)
|
|
278
|
+
|
|
279
|
+
x1_ptrs += TILE_K
|
|
280
|
+
w1_ptr += TILE_K
|
|
281
|
+
|
|
282
|
+
for _ in range(0, tl.cdiv(K, TILE_K)):
|
|
283
|
+
x2 = tl.load(x2_ptrs, mask=mask_m[:, None], other=0.0).to(
|
|
284
|
+
w2_ptr.type.element_ty
|
|
285
|
+
)
|
|
286
|
+
w2_ptrs = w2_ptr + w_tile_offs
|
|
287
|
+
w2 = tl.load(w2_ptrs)
|
|
288
|
+
|
|
289
|
+
if PRECISION == 0:
|
|
290
|
+
acc_2 = tl.dot(x2, w2, acc_2)
|
|
291
|
+
elif PRECISION == 1:
|
|
292
|
+
x2 = cvt_tf32_rn(x2)
|
|
293
|
+
w2 = cvt_tf32_rn(w2)
|
|
294
|
+
acc_2 = tl.dot(x2, w2, acc_2, input_precision="tf32")
|
|
295
|
+
elif PRECISION == 2:
|
|
296
|
+
acc_2 = tl.dot(x2, w2, acc_2, input_precision="tf32x3")
|
|
297
|
+
elif PRECISION == 3:
|
|
298
|
+
acc_2 = tl.dot(x2, w2, acc_2, input_precision="ieee")
|
|
299
|
+
else:
|
|
300
|
+
tl.static_assert(
|
|
301
|
+
False,
|
|
302
|
+
"PRECISION must be 0 (default), 1 (tf32), 2 (tf32x3) or 3 (ieee)",
|
|
303
|
+
)
|
|
304
|
+
|
|
305
|
+
x2_ptrs += TILE_K
|
|
306
|
+
w2_ptr += TILE_K
|
|
307
|
+
|
|
308
|
+
else:
|
|
309
|
+
# recompute acc1 and acc2
|
|
310
|
+
for _ in range(0, tl.cdiv(K, TILE_K)):
|
|
311
|
+
x = tl.load(x1_ptrs, mask=mask_m[:, None], other=0.0).to(
|
|
312
|
+
w1_ptr.type.element_ty
|
|
313
|
+
)
|
|
314
|
+
|
|
315
|
+
w1_ptrs = w1_ptr + w_tile_offs
|
|
316
|
+
w1 = tl.load(w1_ptrs)
|
|
317
|
+
if PRECISION == 0:
|
|
318
|
+
acc_1 = tl.dot(x, w1, acc_1)
|
|
319
|
+
elif PRECISION == 1:
|
|
320
|
+
x = cvt_tf32_rn(x)
|
|
321
|
+
w1 = cvt_tf32_rn(w1)
|
|
322
|
+
acc_1 = tl.dot(x, w1, acc_1, input_precision="tf32")
|
|
323
|
+
elif PRECISION == 2:
|
|
324
|
+
acc_1 = tl.dot(x, w1, acc_1, input_precision="tf32x3")
|
|
325
|
+
elif PRECISION == 3:
|
|
326
|
+
acc_1 = tl.dot(x, w1, acc_1, input_precision="ieee")
|
|
327
|
+
else:
|
|
328
|
+
tl.static_assert(
|
|
329
|
+
False,
|
|
330
|
+
"PRECISION must be 0 (default), 1 (tf32), 2 (tf32x3) or 3 (ieee)",
|
|
331
|
+
)
|
|
332
|
+
|
|
333
|
+
w2_ptrs = w2_ptr + w_tile_offs
|
|
334
|
+
w2 = tl.load(w2_ptrs)
|
|
335
|
+
if PRECISION == 0:
|
|
336
|
+
acc_2 = tl.dot(x, w2, acc_2)
|
|
337
|
+
elif PRECISION == 1:
|
|
338
|
+
x = cvt_tf32_rn(x)
|
|
339
|
+
w2 = cvt_tf32_rn(w2)
|
|
340
|
+
acc_2 = tl.dot(x, w2, acc_2, input_precision="tf32")
|
|
341
|
+
elif PRECISION == 2:
|
|
342
|
+
acc_2 = tl.dot(x, w2, acc_2, input_precision="tf32x3")
|
|
343
|
+
elif PRECISION == 3:
|
|
344
|
+
acc_2 = tl.dot(x, w2, acc_2, input_precision="ieee")
|
|
345
|
+
else:
|
|
346
|
+
tl.static_assert(
|
|
347
|
+
False,
|
|
348
|
+
"PRECISION must be 0 (default), 1 (tf32), 2 (tf32x3) or 3 (ieee)",
|
|
349
|
+
)
|
|
350
|
+
|
|
351
|
+
x1_ptrs += TILE_K
|
|
352
|
+
w1_ptr += TILE_K
|
|
353
|
+
w2_ptr += TILE_K
|
|
354
|
+
|
|
355
|
+
offs_om = pid_m * TILE_M + tl.arange(0, TILE_M)
|
|
356
|
+
offs_on = pid_n * TILE_N + tl.arange(0, TILE_N)
|
|
357
|
+
|
|
358
|
+
if HAS_B1:
|
|
359
|
+
b1_ptrs = b1_ptr + offs_on
|
|
360
|
+
b1_tile = tl.load(b1_ptrs).to(tl.float32)
|
|
361
|
+
acc_1 += b1_tile
|
|
362
|
+
|
|
363
|
+
if HAS_B2:
|
|
364
|
+
b2_ptrs = b2_ptr + offs_on
|
|
365
|
+
b2_tile = tl.load(b2_ptrs).to(tl.float32)
|
|
366
|
+
acc_2 += b2_tile
|
|
367
|
+
|
|
368
|
+
if TRANSPOSE_OUT:
|
|
369
|
+
grad_o_ptrs = grad_o_ptr + offs_on[None, :] * M + offs_om[:, None]
|
|
370
|
+
else:
|
|
371
|
+
grad_o_ptrs = grad_o_ptr + offs_om[:, None] * N + offs_on[None, :]
|
|
372
|
+
|
|
373
|
+
grad_o = tl.load(grad_o_ptrs, mask=mask_m[:, None], other=0.0).to(tl.float32)
|
|
374
|
+
|
|
375
|
+
acc_sig = 1.0 / (1.0 + tl.exp(-acc_1))
|
|
376
|
+
|
|
377
|
+
if APPLY_MASK:
|
|
378
|
+
tmp = acc_sig * acc_2
|
|
379
|
+
grad_mask = grad_o * tmp
|
|
380
|
+
grad_mask = tl.sum(grad_mask, axis=1)
|
|
381
|
+
grad_mask_ptrs = grad_mask_ptr + pid_n * M + offs_om
|
|
382
|
+
tl.store(grad_mask_ptrs, grad_mask, mask=mask_m)
|
|
383
|
+
|
|
384
|
+
mask = tl.load(mask_ptr + offs_om, mask=mask_m, other=0.0).to(tl.float32)
|
|
385
|
+
grad_o = grad_o * mask[:, None]
|
|
386
|
+
|
|
387
|
+
grad_xw2 = grad_o * acc_sig
|
|
388
|
+
grad_xw2_ptrs = grad_xw2_ptr + offs_om[:, None] * N + offs_on[None, :]
|
|
389
|
+
tl.store(grad_xw2_ptrs, grad_xw2, mask=mask_m[:, None])
|
|
390
|
+
|
|
391
|
+
tmp = (1.0 - acc_sig) * acc_sig
|
|
392
|
+
grad_xw1 = grad_o * acc_2 * tmp
|
|
393
|
+
grad_xw1_ptrs = grad_xw1_ptr + offs_om[:, None] * N + offs_on[None, :]
|
|
394
|
+
tl.store(grad_xw1_ptrs, grad_xw1, mask=mask_m[:, None])
|