cocotb 2.0.0rc2__cp39-cp39-macosx_11_0_arm64.whl

cocotb_tools/makefiles/simulators/Makefile.activehdl

@@ -0,0 +1,72 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Common Makefile for the Aldec Active-HDL simulator
+
+CMD_BIN := vsimsa
+
+ifdef ACTIVEHDL_BIN_DIR
+    CMD := $(shell :; command -v $(ACTIVEHDL_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+    ACTIVEHDL_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+ALOG_ARGS += -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)
+
+# below allows for maintaining legacy syntax as well as enables using cross-simulator vars COMPILE_ARGS/SIM_ARGS
+ALOG_ARGS += $(COMPILE_ARGS)
+ACOM_ARGS += $(COMPILE_ARGS)
+ASIM_ARGS += $(SIM_ARGS)
+
+ifdef RTL_LIBRARY
+    $(warning Using RTL_LIBRARY is deprecated, please use TOPLEVEL_LIBRARY instead.)
+    TOPLEVEL_LIBRARY ?= $(RTL_LIBRARY)
+else
+    TOPLEVEL_LIBRARY ?= work
+endif
+
+ALOG_ARGS += -dbg
+ACOM_ARGS += -dbg
+
+GPI_EXTRA:=
+ifeq ($(TOPLEVEL_LANG),verilog)
+    # backslashes needed because we embed in `echo` below
+    GPI_ARGS = -pli \"$(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi activehdl)\"
+ifneq ($(VHDL_SOURCES),)
+    GPI_EXTRA = $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi activehdl):cocotbvhpi_entry_point
+endif
+
+else ifeq ($(TOPLEVEL_LANG),vhdl)
+    # backslashes needed because we embed in `echo` below
+    GPI_ARGS = -loadvhpi \"$(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi activehdl):vhpi_startup_routines_bootstrap\"
+ifneq ($(VERILOG_SOURCES),)
+    GPI_EXTRA = $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi activehdl):cocotbvpi_entry_point
+endif
+else
+   $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
+endif
+
+# Create a DO script (Tcl-like but not fully compatible) based on the list of $(VERILOG_SOURCES)
+$(SIM_BUILD)/runsim.do : $(VERILOG_SOURCES) $(VHDL_SOURCES) | $(SIM_BUILD)
+	@echo "alib $(TOPLEVEL_LIBRARY)" > $@
+	@echo "set worklib $(TOPLEVEL_LIBRARY)" >> $@
+ifneq ($(VHDL_SOURCES),)
+	@echo "acom $(ACOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES))" >> $@
+endif
+ifneq ($(VERILOG_SOURCES),)
+	@echo "alog $(ALOG_ARGS) $(call to_tcl_path,$(VERILOG_SOURCES))" >> $@
+endif
+	@echo "asim $(ASIM_ARGS) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) +access +w_nets -interceptcoutput $(GPI_ARGS) $(COCOTB_TOPLEVEL) $(EXTRA_TOPS)" >> $@
+	@echo "run -all" >> $@
+	@echo "endsim" >> $@
+
+$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/runsim.do $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	set -o pipefail; GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) $(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.do $(SIM_CMD_SUFFIX)
+
+	$(call check_results)

cocotb_tools/makefiles/simulators/Makefile.cvc

@@ -0,0 +1,61 @@
+# Copyright cocotb contributors
+# Copyright (c) 2014 Potential Ventures Ltd
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+ifneq ($(VHDL_SOURCES),)
+
+$(COCOTB_RESULTS_FILE):
+	@echo "Skipping simulation as VHDL is not supported on simulator=$(SIM)"
+debug: $(COCOTB_RESULTS_FILE)
+
+else
+
+CMD_BIN := cvc64
+
+ifdef CVC_BIN_DIR
+    CMD := $(shell :; command -v $(CVC_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+    CVC_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+#only interpreted mode works for the moment
+CVC_ITERP ?= 1
+
+ifeq ($(CVC_ITERP),1)
+    CVC_ARGS    += +interp
+endif
+
+# Compilation phase
+$(SIM_BUILD)/sim.vvp: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) \
+	COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        $(CMD) $(CVC_ARGS) +acc+2 -o $(SIM_BUILD)/sim.vvp +loadvpi=$(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
+
+# Execution phase
+ifeq ($(CVC_ITERP),1)
+    $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp
+else
+    $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) \
+        COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        $(SIM_CMD_PREFIX) $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(SIM_CMD_SUFFIX)
+endif
+
+# Execution phase
+ifeq ($(CVC_ITERP),1)
+    debug:  $(CUSTOM_SIM_DEPS)
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) \
+        COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        $(SIM_CMD_PREFIX) gdb --args $(CMD) $(CVC_ARGS) +acc+2 -o $(SIM_BUILD)/sim.vvp +loadvpi=$(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
+else
+    debug: $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) \
+        COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        gdb --args $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS)
+endif
+
+
+endif

cocotb_tools/makefiles/simulators/Makefile.dsim

@@ -0,0 +1,39 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+CMD_BIN := dsim
+
+ifdef DSIM_BIN_DIR
+    CMD := $(shell :; command -v $(DSIM_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+endif
+
+ifeq (, $(CMD))
+    $(error Unable to locate command >$(CMD_BIN)<)
+endif
+
+ifeq ($(WAVES), 1)
+    WAVE_ARG := -waves file.vcd
+else
+    WAVE_ARG :=
+endif
+
+TOPMODULE_ARG = -top $(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL)
+
+DSIM_ARGS = -work $(SIM_BUILD) -pli_lib $(shell cocotb-config --lib-name-path vpi dsim) +acc+rwcbfsWF
+COMP_ARGS = $(DSIM_ARGS) -genimage image -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)
+RUN_ARGS = $(DSIM_ARGS) -image image $(WAVE_ARG)
+
+$(SIM_BUILD)/image.so: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS)
+	$(SIM_CMD_PREFIX) $(CMD) $(COMP_ARGS) $(TOPMODULE_ARG) $(EXTRA_ARGS) $(VERILOG_SOURCES)
+
+$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/image.so $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) \
+	GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	$(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) $(TOPMODULE_ARG) $(EXTRA_ARGS) $(VERILOG_SOURCES)
+
+	$(call check_results)

cocotb_tools/makefiles/simulators/Makefile.ghdl

@@ -0,0 +1,84 @@
+# Copyright cocotb contributors
+# Copyright (c) 2014 Potential Ventures Ltd
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+TOPLEVEL_LANG ?= vhdl
+
+ifneq ($(or $(filter-out $(TOPLEVEL_LANG),vhdl),$(VERILOG_SOURCES)),)
+
+$(COCOTB_RESULTS_FILE):
+	@echo "Skipping simulation as only VHDL is supported on simulator=$(SIM)"
+
+else
+
+CMD_BIN := ghdl
+
+ifdef GHDL_BIN_DIR
+    CMD := $(shell :; command -v $(GHDL_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+    GHDL_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+ifdef RTL_LIBRARY
+    $(warning Using RTL_LIBRARY is deprecated, please use TOPLEVEL_LIBRARY instead.)
+    TOPLEVEL_LIBRARY ?= $(RTL_LIBRARY)
+else
+    TOPLEVEL_LIBRARY ?= work
+endif
+GHDL_ARGS ?=
+GHDL_ARGS += $(EXTRA_ARGS)
+
+# On Windows add GHDL lib folder to PATH to find libraries
+ifeq ($(OS),Msys)
+    export PATH := $(GHDL_BIN_DIR)/../lib:$(PATH)
+endif
+
+GHDL_RUN_ARGS ?=
+
+ifeq ($(shell $(CMD) --version | grep -q mcode; echo $$?),0)
+    ifneq ($(COCOTB_HDL_TIMEPRECISION),)
+        # Convert the time precision to a format string supported by GHDL, if
+        # possible.
+        # GHDL only supports setting the time precision if the mcode backend is
+        # used, using the --time-resolution argument causes GHDL to error out
+        # otherwise.
+        # https://ghdl.github.io/ghdl/using/InvokingGHDL.html#cmdoption-ghdl-time-resolution
+        ifeq ($(COCOTB_HDL_TIMEPRECISION),1fs)
+            GHDL_TIME_RESOLUTION=fs
+        else ifeq ($(COCOTB_HDL_TIMEPRECISION),1ps)
+            GHDL_TIME_RESOLUTION=ps
+        else ifeq ($(COCOTB_HDL_TIMEPRECISION),1us)
+            GHDL_TIME_RESOLUTION=us
+        else ifeq ($(COCOTB_HDL_TIMEPRECISION),1ms)
+            GHDL_TIME_RESOLUTION=ms
+        else ifeq ($(COCOTB_HDL_TIMEPRECISION),1s)
+            GHDL_TIME_RESOLUTION=sec
+        else
+            $(error GHDL only supports the following values for COCOTB_HDL_TIMEPRECISION: 1fs, 1ps, 1us, 1ms, 1s)
+        endif
+
+        GHDL_RUN_ARGS += --time-resolution=$(GHDL_TIME_RESOLUTION)
+    endif
+endif
+
+.PHONY: analyse
+
+# Compilation phase
+analyse: $(VHDL_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
+	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), \
+		$(CMD) -i $(GHDL_ARGS) $(COMPILE_ARGS) --workdir=$(SIM_BUILD) --work=$(SOURCES_VAR:VHDL_SOURCES_%=%) $($(SOURCES_VAR)) && ) \
+	$(CMD) -i $(GHDL_ARGS) $(COMPILE_ARGS) --workdir=$(SIM_BUILD) --work=$(TOPLEVEL_LIBRARY) $(VHDL_SOURCES) && \
+	$(CMD) -m $(GHDL_ARGS) $(COMPILE_ARGS) --workdir=$(SIM_BUILD) -P$(SIM_BUILD) --work=$(TOPLEVEL_LIBRARY) $(COCOTB_TOPLEVEL) $(ARCH)
+
+$(COCOTB_RESULTS_FILE): analyse $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	$(SIM_CMD_PREFIX) $(CMD) -r $(GHDL_ARGS) $(GHDL_RUN_ARGS) --workdir=$(SIM_BUILD) -P$(SIM_BUILD) --work=$(TOPLEVEL_LIBRARY) $(COCOTB_TOPLEVEL) $(ARCH) --vpi=$(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi ghdl) $(SIM_ARGS) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(SIM_CMD_SUFFIX)
+
+	$(call check_results)
+
+endif

cocotb_tools/makefiles/simulators/Makefile.icarus

@@ -0,0 +1,80 @@
+# Copyright cocotb contributors
+# Copyright (c) 2013 Potential Ventures Ltd
+# Copyright (c) 2013 SolarFlare Communications Inc
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+TOPLEVEL_LANG ?= verilog
+
+ifneq ($(or $(filter-out $(TOPLEVEL_LANG),verilog),$(VHDL_SOURCES)),)
+
+$(COCOTB_RESULTS_FILE):
+	@echo "Skipping simulation as only Verilog is supported on simulator=$(SIM)"
+debug: $(COCOTB_RESULTS_FILE)
+
+else
+
+CMD_BIN := iverilog
+
+ifdef ICARUS_BIN_DIR
+    CMD := $(shell :; command -v $(ICARUS_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+    ICARUS_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+ifdef COCOTB_TOPLEVEL
+  TOPMODULE_ARG := -s $(COCOTB_TOPLEVEL)
+else
+  TOPMODULE_ARG :=
+endif
+
+COMPILE_ARGS += -f $(SIM_BUILD)/cmds.f
+
+ifdef VERILOG_INCLUDE_DIRS
+    COMPILE_ARGS += $(addprefix -I, $(VERILOG_INCLUDE_DIRS))
+endif
+
+# Compilation phase
+
+ifeq ($(WAVES), 1)
+    VERILOG_SOURCES += $(SIM_BUILD)/cocotb_iverilog_dump.v
+    COMPILE_ARGS += -s cocotb_iverilog_dump
+    FST = -fst
+else
+    # Disable waveform output
+    FST = -none
+endif
+
+$(SIM_BUILD)/sim.vvp: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
+	@echo "+timescale+$(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)" > $(SIM_BUILD)/cmds.f
+	$(CMD) -o $(SIM_BUILD)/sim.vvp $(TOPMODULE_ARG) -g2012 $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
+
+$(SIM_BUILD)/cocotb_iverilog_dump.v: | $(SIM_BUILD)
+	@echo 'module cocotb_iverilog_dump();' > $@
+	@echo 'initial begin' >> $@
+	@echo '    $$dumpfile("$(SIM_BUILD)/$(COCOTB_TOPLEVEL).fst");' >> $@
+	@echo '    $$dumpvars(0, $(COCOTB_TOPLEVEL));' >> $@
+	@echo 'end' >> $@
+	@echo 'endmodule' >> $@
+
+# Execution phase
+
+$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        $(SIM_CMD_PREFIX) $(ICARUS_BIN_DIR)/vvp -M $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-dir) -m $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name vpi icarus) $(SIM_ARGS) $(EXTRA_ARGS) $(SIM_BUILD)/sim.vvp $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(FST) $(SIM_CMD_SUFFIX)
+
+	$(call check_results)
+
+debug: $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
+	$(RM) -r $(COCOTB_RESULTS_FILE)
+
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        $(SIM_CMD_PREFIX) gdb --args $(ICARUS_BIN_DIR)/vvp -M $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-dir) -m $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name vpi icarus) $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(FST) $(SIM_CMD_SUFFIX)
+
+	$(call check_results)
+
+endif

cocotb_tools/makefiles/simulators/Makefile.ius

@@ -0,0 +1,93 @@
+# Copyright cocotb contributors
+# Copyright (c) 2013 Potential Ventures Ltd
+# Copyright (c) 2013 SolarFlare Communications Inc
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Common Makefile for Cadence Incisive
+
+CMD_BIN := irun
+
+ifdef IUS_BIN_DIR
+    CMD := $(shell :; command -v $(IUS_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+    IUS_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+ifdef VERILOG_INCLUDE_DIRS
+    COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
+EXTRA_ARGS += $(COMPILE_ARGS)
+EXTRA_ARGS += $(SIM_ARGS)
+EXTRA_ARGS += -licqueue
+
+ifeq ($(PYTHON_ARCH),64bit)
+    EXTRA_ARGS += -64
+endif
+
+EXTRA_ARGS += -nclibdirpath $(SIM_BUILD)
+EXTRA_ARGS += -plinowarn
+
+ifeq ($(GUI),1)
+    EXTRA_ARGS += -gui
+else
+    EXTRA_ARGS +=
+endif
+
+# IUS errors out if multiple timescales are specified on the command line.
+ifneq (,$(findstring timescale,$(EXTRA_ARGS)))
+    $(error Please use COCOTB_HDL_TIMEUNIT and COCOTB_HDL_TIMEPRECISION to specify timescale.)
+endif
+
+# Loading the VHPI library causes an error, so we always load the VPI library and supply
+# GPI_EXTRA=$(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi ius) if needed.
+
+# Xcelium will use default vlog_startup_routines symbol only if vpi library name is libvpi.so
+GPI_ARGS = -loadvpi $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi ius):vlog_startup_routines_bootstrap
+
+ifeq ($(TOPLEVEL_LANG),verilog)
+    EXTRA_ARGS += -v93
+    HDL_SOURCES = $(VERILOG_SOURCES)
+    ROOT_LEVEL = $(COCOTB_TOPLEVEL)
+ifneq ($(VHDL_SOURCES),)
+    HDL_SOURCES += $(VHDL_SOURCES)
+    GPI_EXTRA = $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi ius):cocotbvhpi_entry_point
+endif
+else ifeq ($(TOPLEVEL_LANG),vhdl)
+    GPI_EXTRA = $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi ius):cocotbvhpi_entry_point
+    EXTRA_ARGS += -v93
+    EXTRA_ARGS += -top $(COCOTB_TOPLEVEL)
+ifdef RTL_LIBRARY
+    $(warning Using RTL_LIBRARY is deprecated, please use TOPLEVEL_LIBRARY instead.)
+    TOPLEVEL_LIBRARY ?= $(RTL_LIBRARY)
+else
+    TOPLEVEL_LIBRARY ?= work
+endif
+    MAKE_LIB = -makelib $(TOPLEVEL_LIBRARY)
+    HDL_SOURCES = $(VHDL_SOURCES)
+ifneq ($(VERILOG_SOURCES),)
+    HDL_SOURCES += $(VERILOG_SOURCES)
+endif
+else
+   $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
+endif
+
+# Builds a list of arguments to support VHDL libraries specified in VHDL_SOURCES_*:
+LIBS := $(foreach LIB, $(VHDL_LIB_ORDER),-makelib $(LIB) $(VHDL_SOURCES_$(LIB)) -endlib)
+
+$(COCOTB_RESULTS_FILE): $(HDL_SOURCES) $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS) | $(SIM_BUILD)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	# Make sure all libs in SOURCES_VHDL_* are mentioned in VHDL_LIB_ORDER and vice versa
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(check_vhdl_sources))
+	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), $(check_lib_order))
+
+	set -o pipefail; \
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	$(SIM_CMD_PREFIX) $(CMD) -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \
+	$(EXTRA_ARGS) $(GPI_ARGS) +access+rwc $(LIBS) $(MAKE_LIB) $(HDL_SOURCES) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(SIM_CMD_SUFFIX)
+
+	$(call check_results)

cocotb_tools/makefiles/simulators/Makefile.modelsim

@@ -0,0 +1,9 @@
+# Copyright cocotb contributors
+# Copyright (c) 2013 Potential Ventures Ltd
+# Copyright (c) 2013 SolarFlare Communications Inc
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+
+# Identical to Questa with the compat flow.
+include $(COCOTB_MAKEFILES_DIR)/simulators/Makefile.questa-compat

cocotb_tools/makefiles/simulators/Makefile.nvc

@@ -0,0 +1,60 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+ifneq ($(VERILOG_SOURCES),)
+
+$(COCOTB_RESULTS_FILE):
+	@echo "Skipping simulation as Verilog is not supported on simulator=$(SIM)"
+
+else
+
+CMD_BIN := nvc
+
+ifdef NVC_BIN_DIR
+    CMD := $(shell :; command -v $(NVC_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+	NVC_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+PRESERVE_CASE := $(shell $(CMD) --version | $(PYTHON_BIN) -c "from cocotb_tools.sim_versions import NvcVersion; import sys; print('--preserve-case' if NvcVersion.from_commandline(sys.stdin.read()) > NvcVersion('1.16') else '')")
+
+ifdef RTL_LIBRARY
+    $(warning Using RTL_LIBRARY is deprecated, please use TOPLEVEL_LIBRARY instead.)
+    TOPLEVEL_LIBRARY ?= $(RTL_LIBRARY)
+else
+    TOPLEVEL_LIBRARY ?= work
+endif
+
+.PHONY: analyse
+
+# Split SIM_ARGS into those options that need to be passed to -e and
+# those that need to be passed to -r
+NVC_E_FILTER := -g% --cover --cover=%
+
+NVC_E_ARGS := $(filter $(NVC_E_FILTER),$(SIM_ARGS))
+NVC_R_ARGS := $(filter-out $(NVC_E_FILTER),$(SIM_ARGS))
+
+# Compilation phase
+analyse: $(VHDL_SOURCES) $(SIM_BUILD) $(CUSTOM_COMPILE_DEPS)
+	# Make sure all libs in SOURCES_VHDL_* are mentioned in VHDL_LIB_ORDER and vice versa
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(check_vhdl_sources))
+	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), $(check_lib_order))
+
+	$(foreach LIB_VAR,$(VHDL_LIB_ORDER), \
+		$(CMD) $(EXTRA_ARGS) --work=$(LIB_VAR):$(SIM_BUILD)/$(LIB_VAR) -L $(SIM_BUILD) -a $(VHDL_SOURCES_$(LIB_VAR)) $(PRESERVE_CASE) $(COMPILE_ARGS) && ) \
+	$(CMD) $(EXTRA_ARGS) --work=$(TOPLEVEL_LIBRARY):$(SIM_BUILD)/$(TOPLEVEL_LIBRARY) -L $(SIM_BUILD) -a $(VHDL_SOURCES) $(PRESERVE_CASE) $(COMPILE_ARGS)
+
+$(COCOTB_RESULTS_FILE): analyse $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	  $(SIM_CMD_PREFIX) $(CMD) $(EXTRA_ARGS) --work=$(TOPLEVEL_LIBRARY):$(SIM_BUILD)/$(TOPLEVEL_LIBRARY) -L $(SIM_BUILD) \
+	  -e $(COCOTB_TOPLEVEL) --no-save $(NVC_E_ARGS) \
+	  -r --load $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi nvc) $(TRACE) $(NVC_R_ARGS) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(SIM_CMD_SUFFIX)
+
+	$(call check_results)
+
+endif

cocotb_tools/makefiles/simulators/Makefile.questa

@@ -0,0 +1,29 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Detect the version of Questa in use to choose the best flow.
+
+CMD_BIN := vsim
+
+ifdef MODELSIM_BIN_DIR
+    CMD := $(shell :; command -v $(MODELSIM_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+endif
+
+# Determine the version of Questa being used.
+QUESTA_VERSION := $(shell $(CMD) -version | $(PYTHON_BIN) -c 'import re,sys; print(re.sub(r".+vsim (\d+)\.(\d).+", "\\1 \\2", sys.stdin.read()))')
+QUESTA_VERSION_MAJOR := $(firstword $(QUESTA_VERSION))
+QUESTA_VERSION_MINOR := $(lastword $(QUESTA_VERSION))
+
+# Use the QIS/Qrun flow for Questa >= 2025.2 (the first version which fully
+# passes the cocotb regression suite). Use the compat flow otherwise.
+ifeq ($(shell test $(QUESTA_VERSION_MAJOR)$(QUESTA_VERSION_MINOR) -lt 20252; echo $$?),0)
+    $(info Using the Questa compat flow for Questa version $(QUESTA_VERSION_MAJOR).$(QUESTA_VERSION_MINOR) < 2025.2. Run make with SIM=questa-qisqrun to force the newer QIS/Qrun flow.)
+    include $(COCOTB_MAKEFILES_DIR)/simulators/Makefile.questa-compat
+else
+    $(info Using the Questa QIS/Qrun flow for Questa $(QUESTA_VERSION_MAJOR).$(QUESTA_VERSION_MINOR) >= 2025.2. Run make with SIM=questa-compat for the compat flow.)
+    include $(COCOTB_MAKEFILES_DIR)/simulators/Makefile.questa-qisqrun
+endif

cocotb_tools/makefiles/simulators/Makefile.questa-compat

@@ -0,0 +1,143 @@
+# Copyright (c) 2013, 2018 Potential Ventures Ltd
+# Copyright (c) 2013 SolarFlare Communications Inc
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Questa compatibility flow using the vlog and vsim commands with the +acc
+# switch for design access.
+
+CMD_BIN := vsim
+
+ifdef MODELSIM_BIN_DIR
+    CMD := $(shell :; command -v $(MODELSIM_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+	MODELSIM_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+ifdef RTL_LIBRARY
+    $(warning Using RTL_LIBRARY is deprecated, please use TOPLEVEL_LIBRARY instead.)
+    TOPLEVEL_LIBRARY ?= $(RTL_LIBRARY)
+else
+    TOPLEVEL_LIBRARY ?= work
+endif
+COCOTB_TOPLEVEL := "$(TOPLEVEL_LIBRARY).$(COCOTB_TOPLEVEL)"
+
+ifndef VLOG_ARGS
+    VLOG_ARGS = -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) -mfcu
+endif
+
+COMPILE_ARGS += +acc
+
+ifdef VERILOG_INCLUDE_DIRS
+    VLOG_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
+# below allows for maintaining legacy syntax as well as enables using cross-simulator vars COMPILE_ARGS/SIM_ARGS
+VLOG_ARGS += $(COMPILE_ARGS)
+VCOM_ARGS += $(COMPILE_ARGS)
+VSIM_ARGS += $(SIM_ARGS)
+
+ifeq ($(GUI),1)
+    CMD += -gui
+    VSIM_ARGS += -onfinish stop
+else
+    CMD += -c
+    VSIM_ARGS += -onfinish exit
+endif
+
+FLI_LIB := $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path fli questa)
+VHPI_LIB := $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi questa)
+
+GPI_EXTRA :=
+
+VHDL_GPI_INTERFACE ?= fli
+
+ifeq ($(filter vhpi fli,$(VHDL_GPI_INTERFACE)),)
+    $(error A valid value (fli or vhpi) was not provided for VHDL_GPI_INTERFACE=$(VHDL_GPI_INTERFACE))
+endif
+
+ifeq ($(TOPLEVEL_LANG),vhdl)
+    VSIM_ARGS += -t $(COCOTB_HDL_TIMEPRECISION)
+ifeq ($(VHDL_GPI_INTERFACE),fli)
+    CUSTOM_COMPILE_DEPS += $(FLI_LIB)
+    VSIM_ARGS += -foreign \"cocotb_init $(FLI_LIB)\"
+else
+    VSIM_ARGS += -voptargs="-access=rw+/." -foreign \"vhpi_startup_routines_bootstrap $(call to_tcl_path,$(VHPI_LIB))\"
+endif
+ifneq ($(VERILOG_SOURCES),)
+    GPI_EXTRA :=  $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi questa):cocotbvpi_entry_point
+endif
+
+else ifeq ($(TOPLEVEL_LANG),verilog)
+    VSIM_ARGS += -pli $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi questa)
+ifneq ($(VHDL_SOURCES),)
+    GPI_EXTRA := $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path $(VHDL_GPI_INTERFACE) questa):cocotb$(VHDL_GPI_INTERFACE)_entry_point
+endif
+
+else
+   $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
+endif
+
+define make_lib
+  echo "if [file exists $(SIM_BUILD)/$(LIB)] {vdel -lib $(SIM_BUILD)/$(LIB) -all}" >> $@;
+  echo "vlib $(SIM_BUILD)/$(LIB)" >> $@;
+  echo "vmap $(LIB) $(SIM_BUILD)/$(LIB)" >> $@;
+  echo "vcom -work $(LIB) $(VCOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES_$(LIB)))" >> $@;
+endef
+
+$(SIM_BUILD)/runsim.do : $(VHDL_SOURCES) $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS) | $(SIM_BUILD)
+	# Make sure all libs in SOURCES_VHDL_* are mentioned in VHDL_LIB_ORDER and vice versa
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(check_vhdl_sources))
+	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), $(check_lib_order))
+
+	@echo "# Autogenerated file" > $@
+	@echo "onerror {" >> $@
+	@echo "	quit -f -code 1" >> $@
+	@echo "}" >> $@
+	@echo "vmap -c" >> $@
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(make_lib))
+	@echo "if [file exists $(SIM_BUILD)/$(TOPLEVEL_LIBRARY)] {vdel -lib $(SIM_BUILD)/$(TOPLEVEL_LIBRARY) -all}" >> $@
+	@echo "vlib $(SIM_BUILD)/$(TOPLEVEL_LIBRARY)" >> $@
+	@echo "vmap $(TOPLEVEL_LIBRARY) $(SIM_BUILD)/$(TOPLEVEL_LIBRARY)" >> $@
+ifneq ($(VHDL_SOURCES),)
+	@echo "vcom -work $(TOPLEVEL_LIBRARY) $(VCOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES))" >> $@
+endif
+ifneq ($(VERILOG_SOURCES),)
+	@echo "vlog -work $(TOPLEVEL_LIBRARY) -sv $(VLOG_ARGS) $(EXTRA_ARGS) $(call to_tcl_path,$(VERILOG_SOURCES))" >> $@
+endif
+ifdef SCRIPT_FILE
+	@echo "do $(SCRIPT_FILE)" >> $@
+endif
+	@echo "vsim $(VSIM_ARGS) $(EXTRA_ARGS) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(COCOTB_TOPLEVEL)" >> $@
+ifeq ($(WAVES),1)
+	@echo "log -recursive /*" >> $@
+endif
+ifeq ($(GUI),1)
+	@echo "add log -r *" >> $@
+else
+	@echo "onbreak resume" >> $@
+	@echo "run -all" >> $@
+	@echo "quit" >> $@
+endif
+
+ifeq ($(PYTHON_ARCH),64bit)
+    CMD += -64
+endif
+
+$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/runsim.do
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	set -o pipefail; \
+	  COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) \
+	  COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) \
+	  COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) \
+	  COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) \
+	  GPI_EXTRA=$(GPI_EXTRA) \
+	  TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	  VHDL_GPI_INTERFACE=$(VHDL_GPI_INTERFACE) \
+	  COCOTB__QUESTA_MODE=compat \
+	$(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.do $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(SIM_CMD_SUFFIX)
+
+	$(call check_results)