cocotb 2.0.0rc2__cp310-cp310-macosx_11_0_arm64.whl

cocotb_tools/makefiles/simulators/Makefile.questa-qisqrun

@@ -0,0 +1,149 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Questa QIS/Qrun flow using the Questa Information System (QIS) for design
+# access and qrun to build and run the simulation.
+
+QRUN_BIN := qrun
+VIS_BIN := vis
+
+ifdef MODELSIM_BIN_DIR
+    QRUN_CMD := $(shell :; command -v $(MODELSIM_BIN_DIR)/$(QRUN_BIN) 2>/dev/null)
+    VIS_CMD := $(shell :; command -v $(MODELSIM_BIN_DIR)/$(VIS_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    QRUN_CMD := $(shell :; command -v $(QRUN_BIN) 2>/dev/null)
+    VIS_CMD := $(shell :; command -v $(VIS_BIN) 2>/dev/null)
+endif
+
+ifeq (,$(QRUN_CMD))
+    $(error Unable to locate command >$(QRUN_BIN)<)
+endif
+ifeq (,$(VIS_CMD))
+    $(error Unable to locate command >$(VIS_BIN)<)
+endif
+
+DESIGNFILE ?= design.bin
+WAVEFILE ?= qwave.db
+TOPLEVEL_LIBRARY ?= work
+COCOTB_TOPLEVEL := "$(TOPLEVEL_LIBRARY).$(COCOTB_TOPLEVEL)"
+
+
+ifndef VLOG_ARGS
+    VLOG_ARGS = -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) -mfcu
+endif
+
+ifdef VERILOG_INCLUDE_DIRS
+    VLOG_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
+# below allows for maintaining legacy syntax as well as enables using cross-simulator vars COMPILE_ARGS/SIM_ARGS
+VLOG_ARGS += $(COMPILE_ARGS)
+VCOM_ARGS +=
+VOPT_ARGS += -access=rw+/.
+VSIM_ARGS += $(SIM_ARGS)
+
+ifdef GUI
+    # Run in GUI mode.
+
+    # Two modes are supported:
+    # - GUI=livesim: Open the Visualizer GUI before running the simulation.
+    #   GUI=1 is a backwards-compatible alias for livesim.
+    # - GUI=postsim: Open the Visualizer GUI after the simulation has finished.
+
+    ifeq ($(filter livesim postsim 1,$(GUI)),)
+        $(error A valid value (livesim, postsim, or 1) was not provided for GUI=$(GUI))
+    endif
+
+    # Map GUI=1 to GUI=livesim.
+    ifeq ($(GUI),1)
+        GUI := livesim
+    endif
+
+    VOPT_ARGS += -designfile $(DESIGNFILE)
+    VSIM_ARGS += -onfinish stop -qwavedb=+signal+memory=all+class+assertion+uvm_schematic+msg+wavefile=$(WAVEFILE)
+
+    ifeq ($(GUI),livesim)
+        QRUN_CMD += -gui -visualizer
+        VOPT_ARGS += -debug,livesim
+    endif
+
+    # For GUI=postsim Visualizer is called in the $(COCOTB_RESULTS_FILE) target.
+else
+    # Run in batch mode (no GUI).
+    QRUN_CMD += -c
+    VSIM_ARGS += -onfinish exit
+endif # ifdef GUI
+
+FLI_LIB := $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path fli questa)
+VHPI_LIB := $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi questa)
+GPI_EXTRA :=
+
+VHDL_GPI_INTERFACE ?= fli
+
+ifeq ($(filter vhpi fli,$(VHDL_GPI_INTERFACE)),)
+    $(error A valid value (fli or vhpi) was not provided for VHDL_GPI_INTERFACE=$(VHDL_GPI_INTERFACE))
+endif
+
+ifeq ($(TOPLEVEL_LANG),vhdl)
+    VSIM_ARGS += -t $(COCOTB_HDL_TIMEPRECISION)
+ifeq ($(VHDL_GPI_INTERFACE),fli)
+    CUSTOM_COMPILE_DEPS += $(FLI_LIB)
+    VSIM_ARGS += -foreign "cocotb_init $(FLI_LIB)"
+else
+    VSIM_ARGS += -foreign "vhpi_startup_routines_bootstrap $(call to_tcl_path,$(VHPI_LIB))"
+endif
+ifneq ($(VERILOG_SOURCES),)
+    GPI_EXTRA :=  $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi questa):cocotbvpi_entry_point
+endif
+
+else ifeq ($(TOPLEVEL_LANG),verilog)
+    VSIM_ARGS += -pli $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi questa)
+ifneq ($(VHDL_SOURCES),)
+    GPI_EXTRA := $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path $(VHDL_GPI_INTERFACE) questa):cocotb$(VHDL_GPI_INTERFACE)_entry_point
+endif
+
+else
+    $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
+endif
+
+ifdef SCRIPT_FILE
+    VSIM_ARGS += -do $(SCRIPT_FILE)
+endif
+
+ifeq ($(PYTHON_ARCH),64bit)
+    QRUN_CMD += -64
+endif
+
+define make_lib
+  -makelib $(LIB) $(VHDL_SOURCES_$(LIB)) -end
+endef
+
+$(COCOTB_RESULTS_FILE):
+	# Make sure all libs in SOURCES_VHDL_* are mentioned in VHDL_LIB_ORDER and vice versa
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(check_vhdl_sources))
+	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), $(check_lib_order))
+
+	$(RM) $(COCOTB_RESULTS_FILE)
+	mkdir -p $(SIM_BUILD)
+
+	set -o pipefail; \
+	  COCOTB_TEST_MODULES=$(COCOTB_TEST_MODULES) \
+	  COCOTB_TESTCASE=$(COCOTB_TESTCASE) \
+	  COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) \
+	  COCOTB_TOPLEVEL=$(COCOTB_TOPLEVEL) \
+	  GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	  VHDL_GPI_INTERFACE=$(VHDL_GPI_INTERFACE) \
+	  COCOTB__QUESTA_MODE=qisqrun \
+	  $(SIM_CMD_PREFIX) $(QRUN_CMD) $(RUN_ARGS) -outdir $(SIM_BUILD) \
+	  $(foreach LIB, $(VHDL_LIB_ORDER), $(make_lib)) \
+	  -makelib $(TOPLEVEL_LIBRARY) $(VERILOG_SOURCES) $(VHDL_SOURCES) $(VLOG_ARGS) $(VCOM_ARGS) -end \
+	  $(VOPT_ARGS) $(VSIM_ARGS) $(EXTRA_ARGS) $(COCOTB_PLUSARGS) -sv \
+	  -top $(COCOTB_TOPLEVEL) 2>&1 | tee $(SIM_BUILD)/sim.log
+
+ifeq ($(GUI),postsim)
+	$(VIS_CMD) -designfile $(DESIGNFILE) -wavefile $(WAVEFILE)
+endif
+
+	$(call check_results)

cocotb_tools/makefiles/simulators/Makefile.riviera

@@ -0,0 +1,144 @@
+# Copyright cocotb contributors
+# Copyright (c) 2013 Potential Ventures Ltd
+# Copyright (c) 2013 SolarFlare Communications Inc
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Common Makefile for Aldec Riviera-PRO simulator
+
+ifeq ($(GUI),1)
+    CMD_BIN := riviera
+else
+    CMD_BIN := vsimsa
+endif
+
+ifdef ALDEC_BIN_DIR
+    CMD := $(shell :; command -v $(ALDEC_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+	ALDEC_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+ifeq ($(GUI),1)
+    CMD += -nosplash
+endif
+
+ALOG_ARGS += -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)
+
+ifdef VERILOG_INCLUDE_DIRS
+    ALOG_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
+# below allows for maintaining legacy syntax as well as enables using cross-simulator vars COMPILE_ARGS/SIM_ARGS
+ALOG_ARGS += $(COMPILE_ARGS)
+ACOM_ARGS += $(COMPILE_ARGS)
+ASIM_ARGS += $(SIM_ARGS)
+
+# Plusargs need to be passed to ASIM command not vsimsa
+ASIM_ARGS += $(call deprecate,PLUSARGS,COCOTB_PLUSARGS)
+
+ifdef RTL_LIBRARY
+    $(warning Using RTL_LIBRARY is deprecated, please use TOPLEVEL_LIBRARY instead.)
+    TOPLEVEL_LIBRARY ?= $(RTL_LIBRARY)
+else
+    TOPLEVEL_LIBRARY ?= work
+endif
+
+# Pass the VPI library to the Verilog compilation to get extended checking.
+ALOG_ARGS += -pli $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi riviera)
+
+# Aldec-specific coverage types:
+# - (s)tatement
+# - (b)ranch
+# - (e)xpression
+# - (c)ondition
+# - (a)ssertion
+# - (p)ath
+# - finite state (m)achine
+# Documentation: Riviera Pro 2017.02 Documentation - Page 359
+COVERAGE_TYPES ?= sb
+ifeq ($(COCOTB_USER_COVERAGE),1)
+    ALOG_ARGS += -dbg -coverage $(COVERAGE_TYPES)
+    ACOM_ARGS += -dbg -coverage $(COVERAGE_TYPES)
+
+    ASIM_ARGS += -dbg -acdb -acdb_cov $(COVERAGE_TYPES)
+endif
+
+GPI_EXTRA:=
+ifeq ($(TOPLEVEL_LANG),verilog)
+    GPI_ARGS = -pli $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi riviera)
+ifneq ($(VHDL_SOURCES),)
+    GPI_EXTRA = $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi riviera):cocotbvhpi_entry_point
+endif
+
+else ifeq ($(TOPLEVEL_LANG),vhdl)
+    GPI_ARGS = -loadvhpi $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi riviera):vhpi_startup_routines_bootstrap
+ifneq ($(VERILOG_SOURCES),)
+    GPI_EXTRA = $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi riviera):cocotbvpi_entry_point
+endif
+
+else
+   $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
+endif
+
+define make_lib
+  echo "if [file exists $(SIM_BUILD)/$(LIB)] {adel -lib $(SIM_BUILD)/$(LIB) -all}" >> $@;
+  echo "alib $(SIM_BUILD)/$(LIB)" >> $@;
+  echo "amap $(LIB) $(SIM_BUILD)/$(LIB)" >> $@;
+  echo "acom -work $(LIB) $(ACOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES_$(LIB)))" >> $@;
+endef
+
+# Create a TCL script based on the list of $(VERILOG_SOURCES)
+$(SIM_BUILD)/runsim.tcl : $(VERILOG_SOURCES) $(VHDL_SOURCES) | $(SIM_BUILD)
+	@echo "onerror {" > $@
+	@echo "	puts [read [open sim.log r]]" >> $@
+	@echo "	quit -code 1" >> $@
+	@echo "}" >> $@
+	@echo "amap -c" >> $@
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(make_lib))
+	@echo "@if [string length [array get env LICENSE_QUEUE]] {" >> $@
+	@echo " set LICENSE_QUEUE $$::env(LICENSE_QUEUE)" >> $@
+	@echo "}" >> $@
+	@echo "if [file exists $(SIM_BUILD)/$(TOPLEVEL_LIBRARY)] {adel -lib $(SIM_BUILD)/$(TOPLEVEL_LIBRARYRTL_LIBRARY) -all}" >> $@;
+	@echo "alib $(SIM_BUILD)/$(TOPLEVEL_LIBRARY)" >> $@
+	@echo "amap $(TOPLEVEL_LIBRARY) $(SIM_BUILD)/$(TOPLEVEL_LIBRARY)" >> $@;
+	@echo "set worklib $(TOPLEVEL_LIBRARY)" >> $@;
+ifneq ($(VHDL_SOURCES),)
+	@echo "acom -work $(TOPLEVEL_LIBRARY) $(ACOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES))" >> $@
+endif
+ifneq ($(VERILOG_SOURCES),)
+	@echo "alog -work $(TOPLEVEL_LIBRARY) $(ALOG_ARGS) $(call to_tcl_path,$(VERILOG_SOURCES))" >> $@
+endif
+ifdef SCRIPT_FILE
+	@echo "do $(SCRIPT_FILE)" >> $@
+endif
+ifneq ($(CFG_TOPLEVEL),)
+	@echo "asim $(ASIM_ARGS) +access +w_nets -interceptcoutput $(GPI_ARGS) $(CFG_TOPLEVEL) $(EXTRA_TOPS)" >> $@
+else
+	@echo "asim $(ASIM_ARGS) +access +w_nets -interceptcoutput $(GPI_ARGS) $(COCOTB_TOPLEVEL) $(EXTRA_TOPS)" >> $@
+endif
+ifeq ($(WAVES),1)
+	@echo "log -recursive *" >> $@
+endif
+ifeq ($(GUI),1)
+	@echo "wave -rec *" >> $@
+else
+	@echo "run -all" >> $@
+	@echo "endsim" >> $@
+ifeq ($(COCOTB_USER_COVERAGE),1)
+	@echo "acdb report -cov $(COVERAGE_TYPES) -db $(TOPLEVEL_LIBRARY).acdb -html -o coverage/acdb_report.html" >> $@
+	@echo "acdb report -cov $(COVERAGE_TYPES) -db $(TOPLEVEL_LIBRARY).acdb -txt -o coverage/acdb_report.txt" >> $@
+endif
+	@echo "exit" >> $@
+endif
+
+# Note it's the redirection of the output rather than the 'do' command
+# that turns on batch mode (i.e. exit on completion/error)
+$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/runsim.tcl $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	set -o pipefail; GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) $(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.tcl $(SIM_CMD_SUFFIX)
+
+	$(call check_results)

cocotb_tools/makefiles/simulators/Makefile.vcs

@@ -0,0 +1,65 @@
+# Copyright cocotb contributors
+# Copyright (c) 2013 Potential Ventures Ltd
+# Copyright (c) 2013 SolarFlare Communications Inc
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+ifneq ($(VHDL_SOURCES),)
+
+$(COCOTB_RESULTS_FILE):
+	@echo "Skipping simulation as VHDL is not supported on simulator=$(SIM)"
+
+else
+
+CMD_BIN := vcs
+
+ifdef VCS_BIN_DIR
+    CMD := $(shell :; command -v $(VCS_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+    VCS_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+ifdef VERILOG_INCLUDE_DIRS
+    COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
+ifeq ($(PYTHON_ARCH),64bit)
+    COMPILE_ARGS += -full64
+endif
+
+ifeq ($(GUI),1)
+    EXTRA_ARGS += -gui -kdb
+endif
+
+# Avoid linker "undefined reference to" error
+COMPILE_ARGS += -LDFLAGS -Wl,--no-as-needed
+
+# Enables globally access for read, write, and callback capabilities.
+COMPILE_ARGS += +acc+3
+
+# Enables globally debug capabilities.
+COMPILE_ARGS += -debug_access+all
+
+# TODO:
+# investigate +vpi+1 option which reduces memory requirements
+
+# Compilation phase
+$(SIM_BUILD)/simv: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
+	cd $(SIM_BUILD) && \
+	COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) \
+	$(CMD) -top $(COCOTB_TOPLEVEL) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) -sverilog \
+	-timescale=$(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \
+	$(EXTRA_ARGS) -load $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi vcs) $(COMPILE_ARGS) $(VERILOG_SOURCES)
+
+# Execution phase
+$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/simv $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	$(SIM_CMD_PREFIX) $(SIM_BUILD)/simv $(SIM_ARGS) $(EXTRA_ARGS) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(SIM_CMD_SUFFIX)
+
+	$(call check_results)
+
+endif

cocotb_tools/makefiles/simulators/Makefile.verilator

@@ -0,0 +1,79 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+TOPLEVEL_LANG ?= verilog
+
+ifneq ($(or $(filter-out $(TOPLEVEL_LANG),verilog),$(VHDL_SOURCES)),)
+
+results.xml:
+	@echo "Skipping simulation as only Verilog is supported on simulator=$(SIM)"
+debug: results.xml
+
+else
+
+CMD_BIN := verilator
+
+ifdef VERILATOR_BIN_DIR
+  CMD := $(shell :; command -v $(VERILATOR_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+  # auto-detect bin dir from system path
+  CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+  VERILATOR_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+VLT_MIN := 5.036
+VLT_VERSION := $(shell $(CMD) --version | cut -d " " -f 2)
+MIN_VERSION := $(shell printf "%s\n%s\n" "$(VLT_MIN)" "$(VLT_VERSION)" | sort -g | head -1)
+ifneq ($(MIN_VERSION),$(VLT_MIN))
+  $(error cocotb requires Verilator $(VLT_MIN) or later, but using $(VLT_VERSION))
+endif
+
+ifdef COCOTB_TOPLEVEL
+  TOPMODULE_ARG := --top-module $(COCOTB_TOPLEVEL)
+else
+  TOPMODULE_ARG :=
+endif
+
+ifeq ($(VERILATOR_SIM_DEBUG), 1)
+  COMPILE_ARGS += --debug -CFLAGS "-DVL_DEBUG -DVERILATOR_SIM_DEBUG -g -Og"
+  DEBUG = +verilator+debug
+  BUILD_ARGS += OPT_FAST=-Og OPT_SLOW=-Og OPT_GLOBAL=-Og
+endif
+
+ifeq ($(VERILATOR_TRACE),1)
+  COMPILE_ARGS += --trace --trace-structs
+  SIM_ARGS += --trace
+endif
+
+COMPILE_ARGS += --timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)
+
+_COCOTB_LIB_DIR = $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-dir)
+COMPILE_ARGS += --vpi --public-flat-rw --prefix Vtop -o Vtop -LDFLAGS "-Wl,-rpath,$(_COCOTB_LIB_DIR) -L$(_COCOTB_LIB_DIR) -lcocotbvpi_verilator"
+
+ifdef VERILOG_INCLUDE_DIRS
+  COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
+VERILATOR_CPP := $(shell $(PYTHON_BIN) -m cocotb_tools.config --share)/lib/verilator/verilator.cpp
+
+$(SIM_BUILD)/Vtop.mk: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) $(VERILATOR_CPP) | $(SIM_BUILD)
+	$(CMD) -cc --exe -Mdir $(SIM_BUILD) $(TOPMODULE_ARG) $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES) $(VERILATOR_CPP)
+
+# Compilation phase
+$(SIM_BUILD)/Vtop: $(SIM_BUILD)/Vtop.mk
+	$(MAKE) -C $(SIM_BUILD) $(BUILD_ARGS) -f Vtop.mk
+
+$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/Vtop $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	-COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        $(SIM_CMD_PREFIX) $< $(SIM_ARGS) $(EXTRA_ARGS) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(DEBUG) $(SIM_CMD_SUFFIX)
+
+	$(call check_results)
+
+debug:
+	$(MAKE) VERILATOR_SIM_DEBUG=1 SIM_CMD_PREFIX="gdb --args" $(COCOTB_RESULTS_FILE)
+
+
+endif

cocotb_tools/makefiles/simulators/Makefile.xcelium

@@ -0,0 +1,104 @@
+# Copyright cocotb contributors
+# Copyright (c) 2013, 2018 Potential Ventures Ltd
+# Copyright (c) 2013 SolarFlare Communications Inc
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Common Makefile for Cadence Xcelium
+
+CMD_BIN := xrun
+
+ifdef XCELIUM_BIN_DIR
+    CMD := $(shell :; command -v $(XCELIUM_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+    XCELIUM_BIN_DIR := $(shell dirname $(CMD))
+endif
+
+ifdef VERILOG_INCLUDE_DIRS
+    COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
+endif
+
+EXTRA_ARGS += $(COMPILE_ARGS)
+EXTRA_ARGS += $(SIM_ARGS)
+EXTRA_ARGS += -licqueue
+
+ifeq ($(PYTHON_ARCH),64bit)
+    EXTRA_ARGS += -64
+endif
+
+EXTRA_ARGS += -xmlibdirpath $(SIM_BUILD)
+ifeq ($(DEBUG),1)
+    EXTRA_ARGS += -pliverbose
+    EXTRA_ARGS += -messages
+    EXTRA_ARGS += -plidebug             # Enhance the profile output with PLI info
+    EXTRA_ARGS += -plierr_verbose       # Expand handle info in PLI/VPI/VHPI messages
+    EXTRA_ARGS += -vpicompat 1800v2005  #  <1364v1995|1364v2001|1364v2005|1800v2005> Specify the IEEE VPI
+else
+    EXTRA_ARGS += -plinowarn
+endif
+
+ifeq ($(GUI),1)
+    EXTRA_ARGS += -gui
+else
+    EXTRA_ARGS +=
+endif
+
+# Xcelium errors out if multiple timescales are specified on the command line.
+ifneq (,$(filter -timescale%,$(EXTRA_ARGS)))
+    $(error Please use COCOTB_HDL_TIMEUNIT and COCOTB_HDL_TIMEPRECISION to specify timescale.)
+endif
+
+# Loading the VHPI library causes an error, so we always load the VPI library and supply
+# GPI_EXTRA=$(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi xcelium) if needed.
+
+# Xcelium will use default vlog_startup_routines symbol only if VPI library name is libvpi.so
+GPI_ARGS = -loadvpi $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vpi xcelium):vlog_startup_routines_bootstrap
+ifeq ($(TOPLEVEL_LANG),verilog)
+    HDL_SOURCES = $(VERILOG_SOURCES)
+    ROOT_LEVEL = $(COCOTB_TOPLEVEL)
+    EXTRA_ARGS += -top $(COCOTB_TOPLEVEL)
+    ifneq ($(VHDL_SOURCES),)
+        HDL_SOURCES += $(VHDL_SOURCES)
+        GPI_EXTRA = $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi xcelium):cocotbvhpi_entry_point
+    endif
+else ifeq ($(TOPLEVEL_LANG),vhdl)
+    GPI_EXTRA = $(shell $(PYTHON_BIN) -m cocotb_tools.config --lib-name-path vhpi xcelium):cocotbvhpi_entry_point
+    EXTRA_ARGS += -top $(COCOTB_TOPLEVEL)
+    # Xcelium 23.09.004 fixes cocotb issue #1076 as long as the following define
+    # is set.
+    EXTRA_ARGS += -NEW_VHPI_PROPAGATE_DELAY
+ifdef RTL_LIBRARY
+    $(warning Using RTL_LIBRARY is deprecated, please use TOPLEVEL_LIBRARY instead.)
+    TOPLEVEL_LIBRARY ?= $(RTL_LIBRARY)
+else
+    TOPLEVEL_LIBRARY ?= work
+endif
+    MAKE_LIB = -makelib $(TOPLEVEL_LIBRARY)
+    END_LIB = -endlib
+    HDL_SOURCES = $(VHDL_SOURCES)
+    ifneq ($(VERILOG_SOURCES),)
+        HDL_SOURCES += $(VERILOG_SOURCES)
+    endif
+else
+    $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
+endif
+
+# Builds a list of arguments to support VHDL libraries specified in VHDL_SOURCES_*:
+LIBS := $(foreach LIB, $(VHDL_LIB_ORDER),-makelib $(LIB) $(VHDL_SOURCES_$(LIB)) -endlib)
+
+$(COCOTB_RESULTS_FILE): $(HDL_SOURCES) $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS) | $(SIM_BUILD)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	# Make sure all libs in SOURCES_VHDL_* are mentioned in VHDL_LIB_ORDER and vice versa
+	$(foreach LIB, $(VHDL_LIB_ORDER), $(check_vhdl_sources))
+	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), $(check_lib_order))
+
+	set -o pipefail; \
+	COCOTB_TEST_MODULES=$(call deprecate,MODULE,COCOTB_TEST_MODULES) COCOTB_TESTCASE=$(call deprecate,TESTCASE,COCOTB_TESTCASE) COCOTB_TEST_FILTER=$(COCOTB_TEST_FILTER) COCOTB_TOPLEVEL=$(call deprecate,TOPLEVEL,COCOTB_TOPLEVEL) GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	$(SIM_CMD_PREFIX) $(CMD) -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \
+	-vhdl_time_precision "$(COCOTB_HDL_TIMEPRECISION)" \
+	$(EXTRA_ARGS) $(GPI_ARGS) $(INCDIRS) -access +rwc -createdebugdb $(LIBS) $(MAKE_LIB) $(HDL_SOURCES) $(END_LIB) $(call deprecate,PLUSARGS,COCOTB_PLUSARGS) $(SIM_CMD_SUFFIX)
+
+	$(call check_results)