cocotb 1.9.2__cp36-cp36m-win_amd64.whl → 2.0.0b1__cp36-cp36m-win_amd64.whl

cocotb/share/lib/verilator/verilator.cpp

@@ -20,9 +20,12 @@
 #if VM_TRACE
 #if VM_TRACE_FST
 #include <verilated_fst_c.h>
+using verilated_trace_t = VerilatedFstC;
 #else
 #include <verilated_vcd_c.h>
+using verilated_trace_t = VerilatedVcdC;
 #endif
+static verilated_trace_t* tfp;
 #endif
 
 static vluint64_t main_time = 0;  // Current simulation time
@@ -50,18 +53,43 @@ static inline bool settle_value_callbacks() {
     return cbs_called;
 }
 
+void wrap_up() {
+    VerilatedVpi::callCbs(cbEndOfSimulation);
+
+#if VM_TRACE
+    if (tfp) {
+        delete tfp;
+        tfp = nullptr;
+    }
+#endif
+
+    // VM_COVERAGE is a define which is set if Verilator is
+    // instructed to collect coverage (when compiling the simulation)
+#if VM_COVERAGE
+    VerilatedCov::write();  // Uses +verilator+coverage+file+<filename>,
+                            // defaults to coverage.dat
+#endif
+}
+
 int main(int argc, char** argv) {
-    bool traceOn = false;
 #if VM_TRACE_FST
     const char* traceFile = "dump.fst";
 #else
     const char* traceFile = "dump.vcd";
 #endif
+    bool traceOn = false;
 
     for (int i = 1; i < argc; i++) {
         std::string arg = std::string(argv[i]);
         if (arg == "--trace") {
+#if VM_TRACE
             traceOn = true;
+#else
+            fprintf(stderr,
+                    "Error: --trace requires the design to be built with trace "
+                    "support\n");
+            return -1;
+#endif
         } else if (arg == "--trace-file") {
             if (++i < argc) {
                 traceFile = argv[i];
@@ -95,57 +123,44 @@ int main(int argc, char** argv) {
     Verilated::internalsDump();
 #endif
 
-    vlog_startup_routines_bootstrap();
-    VerilatedVpi::callCbs(cbStartOfSimulation);
-
 #if VM_TRACE
-#if VM_TRACE_FST
-    std::unique_ptr<VerilatedFstC> tfp(new VerilatedFstC);
-#else
-    std::unique_ptr<VerilatedVcdC> tfp(new VerilatedVcdC);
-#endif
-
+    Verilated::traceEverOn(true);
     if (traceOn) {
-        Verilated::traceEverOn(true);
-        top->trace(tfp.get(), 99);
+        tfp = new verilated_trace_t;
+        top->trace(tfp, 99);
         tfp->open(traceFile);
     }
 #endif
 
-    while (!Verilated::gotFinish()) {
-        // Call registered timed callbacks (e.g. clock timer)
-        // These are called at the beginning of the time step
-        // before the iterative regions (IEEE 1800-2012 4.4.1)
-        VerilatedVpi::callTimedCbs();
-
-        // Call Value Change callbacks triggered by Timer callbacks
-        // These can modify signal values
-        settle_value_callbacks();
-
-        // We must evaluate whole design until we process all 'events'
-        bool again = true;
-        while (again) {
-            // Evaluate design
-            top->eval_step();
-
-            // Call Value Change callbacks triggered by eval()
-            // These can modify signal values
-            again = settle_value_callbacks();
+    vlog_startup_routines_bootstrap();
+    Verilated::addExitCb([](void*) { wrap_up(); }, nullptr);
+    VerilatedVpi::callCbs(cbStartOfSimulation);
+    settle_value_callbacks();
 
-            // Call registered ReadWrite callbacks
-            again |= VerilatedVpi::callCbs(cbReadWriteSynch);
+    while (!Verilated::gotFinish()) {
+        do {
+            // We must evaluate whole design until we process all 'events' for
+            // this time step
+            do {
+                top->eval_step();
+                VerilatedVpi::clearEvalNeeded();
+                VerilatedVpi::doInertialPuts();
+                settle_value_callbacks();
+            } while (VerilatedVpi::evalNeeded());
+
+            // Run ReadWrite callback as we are done processing this eval step
+            VerilatedVpi::callCbs(cbReadWriteSynch);
+            VerilatedVpi::doInertialPuts();
+            settle_value_callbacks();
+        } while (VerilatedVpi::evalNeeded());
 
-            // Call Value Change callbacks triggered by ReadWrite callbacks
-            // These can modify signal values
-            again |= settle_value_callbacks();
-        }
         top->eval_end_step();
 
         // Call ReadOnly callbacks
         VerilatedVpi::callCbs(cbReadOnlySynch);
 
 #if VM_TRACE
-        if (traceOn) {
+        if (tfp) {
             tfp->dump(main_time);
         }
 #endif
@@ -169,28 +184,18 @@ int main(int argc, char** argv) {
         // It should be called in simulation cycle before everything else
         // but not on first cycle
         VerilatedVpi::callCbs(cbNextSimTime);
+        settle_value_callbacks();
 
-        // Call Value Change callbacks triggered by NextTimeStep callbacks
-        // These can modify signal values
+        // Call registered timed callbacks (e.g. clock timer)
+        // These are called at the beginning of the time step
+        // before the iterative regions (IEEE 1800-2012 4.4.1)
+        VerilatedVpi::callTimedCbs();
         settle_value_callbacks();
     }
 
-    VerilatedVpi::callCbs(cbEndOfSimulation);
-
     top->final();
 
-#if VM_TRACE
-    if (traceOn) {
-        tfp->close();
-    }
-#endif
-
-// VM_COVERAGE is a define which is set if Verilator is
-// instructed to collect coverage (when compiling the simulation)
-#if VM_COVERAGE
-    VerilatedCov::write();  // Uses +verilator+coverage+file+<filename>,
-                            // defaults to coverage.dat
-#endif
+    wrap_up();
 
     return 0;
 }