cocotb 1.9.2__cp313-cp313-win_amd64.whl → 2.0.0b1__cp313-cp313-win_amd64.whl

cocotb/share/makefiles/Makefile.deprecations

@@ -1,12 +0,0 @@
-# Copyright cocotb contributors
-# Licensed under the Revised BSD License, see LICENSE for details.
-# SPDX-License-Identifier: BSD-3-Clause
-
-ifdef VERILATOR_TRACE
-    $(warning VERILATOR_TRACE is deprecated, see the "Simulator Support" section in the documentation.)
-endif
-
-ifeq ($(SIM_LOWERCASE),aldec)
-    $(warning Using SIM=aldec is deprecated, please use SIM=riviera instead.)
-    SIM_LOWERCASE := riviera
-endif

cocotb/share/makefiles/simulators/Makefile.cvc

@@ -1,94 +0,0 @@
-###############################################################################
-# Copyright (c) 2014 Potential Ventures Ltd
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#     * Redistributions of source code must retain the above copyright
-#       notice, this list of conditions and the following disclaimer.
-#     * Redistributions in binary form must reproduce the above copyright
-#       notice, this list of conditions and the following disclaimer in the
-#       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Potential Ventures Ltd, nor the
-#       names of its contributors may be used to endorse or promote products
-#       derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-###############################################################################
-
-include $(shell cocotb-config --makefiles)/Makefile.inc
-
-ifneq ($(VHDL_SOURCES),)
-
-$(COCOTB_RESULTS_FILE):
-	@echo "Skipping simulation as VHDL is not supported on simulator=$(SIM)"
-debug: $(COCOTB_RESULTS_FILE)
-clean::
-
-else
-
-CMD_BIN := cvc64
-
-ifdef CVC_BIN_DIR
-    CMD := $(shell :; command -v $(CVC_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
-else
-    # auto-detect bin dir from system path
-    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
-endif
-
-ifeq (, $(CMD))
-    $(error Unable to locate command >$(CMD_BIN)<)
-else
-    CVC_BIN_DIR := $(shell dirname $(CMD))
-    export CVC_BIN_DIR
-endif
-
-#only interpreted mode works for the moment
-CVC_ITERP ?= 1
-
-ifeq ($(CVC_ITERP),1)
-    CVC_ARGS    += +interp
-endif
-
-# Compilation phase
-$(SIM_BUILD)/sim.vvp: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
-	MODULE=$(MODULE) \
-	TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        $(CMD) $(CVC_ARGS) +acc+2 -o $(SIM_BUILD)/sim.vvp +define+COCOTB_SIM=1 +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
-
-# Execution phase
-ifeq ($(CVC_ITERP),1)
-    $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp
-else
-    $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
-	MODULE=$(MODULE) \
-        TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        $(SIM_CMD_PREFIX) $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
-endif
-
-# Execution phase
-ifeq ($(CVC_ITERP),1)
-    debug:  $(CUSTOM_SIM_DEPS)
-	MODULE=$(MODULE) \
-        TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        $(SIM_CMD_PREFIX) gdb --args $(CMD) $(CVC_ARGS) +acc+2 -o $(SIM_BUILD)/sim.vvp +define+COCOTB_SIM=1 +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
-else
-    debug: $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
-	MODULE=$(MODULE) \
-        TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        gdb --args $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS)
-endif
-
-
-clean::
-	$(RM) -r $(SIM_BUILD)
-endif

cocotb/share/makefiles/simulators/Makefile.icarus

@@ -1,111 +0,0 @@
-###############################################################################
-# Copyright (c) 2013 Potential Ventures Ltd
-# Copyright (c) 2013 SolarFlare Communications Inc
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#     * Redistributions of source code must retain the above copyright
-#       notice, this list of conditions and the following disclaimer.
-#     * Redistributions in binary form must reproduce the above copyright
-#       notice, this list of conditions and the following disclaimer in the
-#       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Potential Ventures Ltd,
-#       SolarFlare Communications Inc nor the
-#       names of its contributors may be used to endorse or promote products
-#       derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-###############################################################################
-
-TOPLEVEL_LANG ?= verilog
-
-include $(shell cocotb-config --makefiles)/Makefile.inc
-
-ifneq ($(or $(filter-out $(TOPLEVEL_LANG),verilog),$(VHDL_SOURCES)),)
-
-$(COCOTB_RESULTS_FILE):
-	@echo "Skipping simulation as only Verilog is supported on simulator=$(SIM)"
-debug: $(COCOTB_RESULTS_FILE)
-clean::
-
-else
-
-CMD_BIN := iverilog
-
-ifdef ICARUS_BIN_DIR
-    CMD := $(shell :; command -v $(ICARUS_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
-else
-    # auto-detect bin dir from system path
-    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
-endif
-
-ifeq (, $(CMD))
-    $(error Unable to locate command >$(CMD_BIN)<)
-else
-    ICARUS_BIN_DIR := $(shell dirname $(CMD))
-    export ICARUS_BIN_DIR
-endif
-
-ifdef TOPLEVEL
-  TOPMODULE_ARG := -s $(TOPLEVEL)
-else
-  TOPMODULE_ARG :=
-endif
-
-COMPILE_ARGS += -f $(SIM_BUILD)/cmds.f
-
-ifdef VERILOG_INCLUDE_DIRS
-    COMPILE_ARGS += $(addprefix -I, $(VERILOG_INCLUDE_DIRS))
-endif
-
-# Compilation phase
-
-ifeq ($(WAVES), 1)
-    VERILOG_SOURCES += $(SIM_BUILD)/cocotb_iverilog_dump.v
-    COMPILE_ARGS += -s cocotb_iverilog_dump
-    PLUSARGS += -fst
-endif
-
-$(SIM_BUILD)/sim.vvp: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
-	@echo "+timescale+$(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)" > $(SIM_BUILD)/cmds.f
-	$(CMD) -o $(SIM_BUILD)/sim.vvp -D COCOTB_SIM=1 $(TOPMODULE_ARG) -g2012 $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
-
-$(SIM_BUILD)/cocotb_iverilog_dump.v: | $(SIM_BUILD)
-	@echo 'module cocotb_iverilog_dump();' > $@
-	@echo 'initial begin' >> $@
-	@echo '    $$dumpfile("$(SIM_BUILD)/$(TOPLEVEL).fst");' >> $@
-	@echo '    $$dumpvars(0, $(TOPLEVEL));' >> $@
-	@echo 'end' >> $@
-	@echo 'endmodule' >> $@
-
-# Execution phase
-
-$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
-	$(RM) $(COCOTB_RESULTS_FILE)
-
-	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        $(SIM_CMD_PREFIX) $(ICARUS_BIN_DIR)/vvp -M $(shell cocotb-config --lib-dir) -m $(shell cocotb-config --lib-name vpi icarus) $(SIM_ARGS) $(EXTRA_ARGS) $(SIM_BUILD)/sim.vvp $(PLUSARGS) $(SIM_CMD_SUFFIX)
-
-	$(call check_for_results_file)
-
-debug: $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
-	$(RM) -r $(COCOTB_RESULTS_FILE)
-
-	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-        $(SIM_CMD_PREFIX) gdb --args $(ICARUS_BIN_DIR)/vvp $(shell cocotb-config --lib-dir) -m $(shell cocotb-config --lib-name vpi icarus) $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
-
-	$(call check_for_results_file)
-
-clean::
-	$(RM) -r $(SIM_BUILD)
-endif

cocotb/share/makefiles/simulators/Makefile.ius

@@ -1,125 +0,0 @@
-###############################################################################
-# Copyright (c) 2013 Potential Ventures Ltd
-# Copyright (c) 2013 SolarFlare Communications Inc
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#     * Redistributions of source code must retain the above copyright
-#       notice, this list of conditions and the following disclaimer.
-#     * Redistributions in binary form must reproduce the above copyright
-#       notice, this list of conditions and the following disclaimer in the
-#       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Potential Ventures Ltd,
-#       SolarFlare Communications Inc nor the
-#       names of its contributors may be used to endorse or promote products
-#       derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-###############################################################################
-
-# Common Makefile for Cadence Incisive
-
-include $(shell cocotb-config --makefiles)/Makefile.inc
-
-CMD_BIN := irun
-
-ifdef IUS_BIN_DIR
-    CMD := $(shell :; command -v $(IUS_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
-else
-    # auto-detect bin dir from system path
-    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
-endif
-
-ifeq (, $(CMD))
-    $(error Unable to locate command >$(CMD_BIN)<)
-else
-    IUS_BIN_DIR := $(shell dirname $(CMD))
-    export IUS_BIN_DIR
-endif
-
-ifdef VERILOG_INCLUDE_DIRS
-    COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
-endif
-
-EXTRA_ARGS += $(COMPILE_ARGS)
-EXTRA_ARGS += $(SIM_ARGS)
-EXTRA_ARGS += -licqueue
-
-ifeq ($(PYTHON_ARCH),64bit)
-    EXTRA_ARGS += -64
-endif
-
-EXTRA_ARGS += -nclibdirpath $(SIM_BUILD)
-EXTRA_ARGS += -plinowarn
-
-ifeq ($(GUI),1)
-    EXTRA_ARGS += -gui
-else
-    EXTRA_ARGS +=
-endif
-
-# IUS errors out if multiple timescales are specified on the command line.
-ifneq (,$(findstring timescale,$(EXTRA_ARGS)))
-    $(error Please use COCOTB_HDL_TIMEUNIT and COCOTB_HDL_TIMEPRECISION to specify timescale.)
-endif
-
-# Loading the VHPI library causes an error, so we always load the VPI library and supply
-# GPI_EXTRA=$(shell cocotb-config --lib-name-path vhpi ius) if needed.
-
-# Xcelium will use default vlog_startup_routines symbol only if vpi library name is libvpi.so
-GPI_ARGS = -loadvpi $(shell cocotb-config --lib-name-path vpi ius):vlog_startup_routines_bootstrap
-
-ifeq ($(TOPLEVEL_LANG),verilog)
-    EXTRA_ARGS += -v93
-    HDL_SOURCES = $(VERILOG_SOURCES)
-    ROOT_LEVEL = $(TOPLEVEL)
-ifneq ($(VHDL_SOURCES),)
-    HDL_SOURCES += $(VHDL_SOURCES)
-    GPI_EXTRA = $(shell cocotb-config --lib-name-path vhpi ius):cocotbvhpi_entry_point
-endif
-else ifeq ($(TOPLEVEL_LANG),vhdl)
-    GPI_EXTRA = $(shell cocotb-config --lib-name-path vhpi ius):cocotbvhpi_entry_point
-    EXTRA_ARGS += -v93
-    EXTRA_ARGS += -top $(TOPLEVEL)
-    RTL_LIBRARY ?= $(TOPLEVEL)
-    MAKE_LIB = -makelib $(RTL_LIBRARY)
-    HDL_SOURCES = $(VHDL_SOURCES)
-ifneq ($(VERILOG_SOURCES),)
-    HDL_SOURCES += $(VERILOG_SOURCES)
-endif
-else
-   $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
-endif
-
-# Builds a list of arguments to support VHDL libraries specified in VHDL_SOURCES_*:
-LIBS := $(foreach LIB, $(VHDL_LIB_ORDER),-makelib $(LIB) $(VHDL_SOURCES_$(LIB)) -endlib)
-
-$(COCOTB_RESULTS_FILE): $(HDL_SOURCES) $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS) | $(SIM_BUILD)
-	$(RM) $(COCOTB_RESULTS_FILE)
-
-	# Make sure all libs in SOURCES_VHDL_* are mentioned in VHDL_LIB_ORDER and vice versa
-	$(foreach LIB, $(VHDL_LIB_ORDER), $(check_vhdl_sources))
-	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), $(check_lib_order))
-
-	set -o pipefail; \
-	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-	$(SIM_CMD_PREFIX) $(CMD) -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \
-	$(EXTRA_ARGS) $(GPI_ARGS) +access+rwc $(LIBS) $(MAKE_LIB) $(HDL_SOURCES) $(PLUSARGS) $(SIM_CMD_SUFFIX)
-
-	$(call check_for_results_file)
-
-clean::
-	$(RM) -r $(SIM_BUILD)
-	$(RM) -r irun.*
-	$(RM) -r ncsim.*
-	$(RM) -r gdb_cmd_ncsim

cocotb/share/makefiles/simulators/Makefile.modelsim

@@ -1,32 +0,0 @@
-###############################################################################
-# Copyright (c) 2013 Potential Ventures Ltd
-# Copyright (c) 2013 SolarFlare Communications Inc
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#     * Redistributions of source code must retain the above copyright
-#       notice, this list of conditions and the following disclaimer.
-#     * Redistributions in binary form must reproduce the above copyright
-#       notice, this list of conditions and the following disclaimer in the
-#       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Potential Ventures Ltd,
-#       SolarFlare Communications Inc nor the
-#       names of its contributors may be used to endorse or promote products
-#       derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-###############################################################################
-
-
-# Identical to Questa
-include $(shell cocotb-config --makefiles)/simulators/Makefile.questa

cocotb/share/makefiles/simulators/Makefile.nvc

@@ -1,64 +0,0 @@
-# Copyright cocotb contributors
-# Licensed under the Revised BSD License, see LICENSE for details.
-# SPDX-License-Identifier: BSD-3-Clause
-
-include $(shell cocotb-config --makefiles)/Makefile.inc
-
-ifneq ($(VERILOG_SOURCES),)
-
-$(COCOTB_RESULTS_FILE):
-	@echo "Skipping simulation as Verilog is not supported on simulator=$(SIM)"
-clean::
-
-else
-
-CMD_BIN := nvc
-
-ifdef NVC_BIN_DIR
-    CMD := $(shell :; command -v $(NVC_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
-else
-    # auto-detect bin dir from system path
-    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
-endif
-
-ifeq (, $(CMD))
-    $(error "Unable to locate command >$(CMD_BIN)<")
-else
-    NVC_BIN_DIR := $(shell dirname $(CMD))
-    export NVC_BIN_DIR
-endif
-
-RTL_LIBRARY ?= work
-
-.PHONY: analyse
-
-# Split SIM_ARGS into those options that need to be passed to -e and
-# those that need to be passed to -r
-NVC_E_FILTER := -g% --cover --cover=%
-
-NVC_E_ARGS := $(filter $(NVC_E_FILTER),$(SIM_ARGS))
-NVC_R_ARGS := $(filter-out $(NVC_E_FILTER),$(SIM_ARGS))
-
-# Compilation phase
-analyse: $(VHDL_SOURCES) $(SIM_BUILD) $(CUSTOM_COMPILE_DEPS)
-	# Make sure all libs in SOURCES_VHDL_* are mentioned in VHDL_LIB_ORDER and vice versa
-	$(foreach LIB, $(VHDL_LIB_ORDER), $(check_vhdl_sources))
-	$(foreach SOURCES_VAR, $(filter VHDL_SOURCES_%, $(.VARIABLES)), $(check_lib_order))
-
-	$(foreach LIB_VAR,$(VHDL_LIB_ORDER), \
-		$(CMD) $(EXTRA_ARGS) --work=$(LIB_VAR):$(SIM_BUILD)/$(LIB_VAR) -L $(SIM_BUILD) -a $(VHDL_SOURCES_$(LIB_VAR)) $(COMPILE_ARGS) && ) \
-	$(CMD) $(EXTRA_ARGS) --work=$(RTL_LIBRARY):$(SIM_BUILD)/$(RTL_LIBRARY) -L $(SIM_BUILD) -a $(VHDL_SOURCES) $(COMPILE_ARGS)
-
-$(COCOTB_RESULTS_FILE): analyse $(CUSTOM_SIM_DEPS)
-	$(RM) $(COCOTB_RESULTS_FILE)
-
-	TESTCASE=$(TESTCASE) MODULE=$(MODULE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-	  $(SIM_CMD_PREFIX) $(CMD) $(EXTRA_ARGS) --work=$(RTL_LIBRARY):$(SIM_BUILD)/$(RTL_LIBRARY) -L $(SIM_BUILD) \
-	  -e $(TOPLEVEL) --no-save $(NVC_E_ARGS) \
-	  -r --load $(shell cocotb-config --lib-name-path vhpi nvc) $(TRACE) $(NVC_R_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
-
-	$(call check_for_results_file)
-
-clean::
-	$(RM) -r $(SIM_BUILD)
-endif

cocotb/share/makefiles/simulators/Makefile.vcs

@@ -1,98 +0,0 @@
-###############################################################################
-# Copyright (c) 2013 Potential Ventures Ltd
-# Copyright (c) 2013 SolarFlare Communications Inc
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#     * Redistributions of source code must retain the above copyright
-#       notice, this list of conditions and the following disclaimer.
-#     * Redistributions in binary form must reproduce the above copyright
-#       notice, this list of conditions and the following disclaimer in the
-#       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Potential Ventures Ltd,
-#       SolarFlare Communications Inc nor the
-#       names of its contributors may be used to endorse or promote products
-#       derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-###############################################################################
-
-include $(shell cocotb-config --makefiles)/Makefile.inc
-
-ifneq ($(VHDL_SOURCES),)
-
-$(COCOTB_RESULTS_FILE):
-	@echo "Skipping simulation as VHDL is not supported on simulator=$(SIM)"
-clean::
-
-else
-
-CMD_BIN := vcs
-
-ifdef VCS_BIN_DIR
-     CMD := $(shell :; command -v $(VCS_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
-else
-     # auto-detect bin dir from system path
-     CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
-endif
-
-ifeq (, $(CMD))
-     $(error Unable to locate command >$(CMD_BIN)<)
-else
-     VCS_BIN_DIR := $(shell dirname $(CMD))
-     export VCS_BIN_DIR
-endif
-
-ifdef VERILOG_INCLUDE_DIRS
-    COMPILE_ARGS += $(addprefix +incdir+, $(VERILOG_INCLUDE_DIRS))
-endif
-
-ifeq ($(PYTHON_ARCH),64bit)
-    EXTRA_ARGS += -full64
-endif
-
-ifeq ($(GUI),1)
-    EXTRA_ARGS += -gui
-endif
-
-# TODO:
-# investigate +vpi+1 option which reduces memory requirements
-
-# Can't do this using an argument, we have to create a PLI table file
-# enabling write access to the design
-$(SIM_BUILD)/pli.tab : | $(SIM_BUILD)
-	echo "acc+=rw,wn:*" > $@
-
-# Compilation phase
-$(SIM_BUILD)/simv: $(VERILOG_SOURCES) $(SIM_BUILD)/pli.tab $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
-	cd $(SIM_BUILD) && \
-	TOPLEVEL=$(TOPLEVEL) \
-	$(CMD) -top $(TOPLEVEL) $(PLUSARGS) -debug_access+r+w-memcbk -debug_region+cell +vpi -P pli.tab +define+COCOTB_SIM=1 -sverilog \
-	-timescale=$(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \
-	$(EXTRA_ARGS) -debug -load $(shell cocotb-config --lib-name-path vpi vcs) $(COMPILE_ARGS) $(VERILOG_SOURCES)
-
-# Execution phase
-$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/simv $(CUSTOM_SIM_DEPS)
-	$(RM) $(COCOTB_RESULTS_FILE)
-
-	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
-	$(SIM_CMD_PREFIX) $(SIM_BUILD)/simv +define+COCOTB_SIM=1 $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
-
-	$(call check_for_results_file)
-
-clean::
-	$(RM) -r $(SIM_BUILD)
-	$(RM) -r simv.daidir
-	$(RM) -r cm.log
-	$(RM) -r ucli.key
-endif