cocotb 1.9.2__cp313-cp313-manylinux_2_17_x86_64.manylinux2014_x86_64.whl

cocotb/share/lib/verilator/verilator.cpp

@@ -0,0 +1,196 @@
+// Copyright cocotb contributors
+// Licensed under the Revised BSD License, see LICENSE for details.
+// SPDX-License-Identifier: BSD-3-Clause
+
+#include <libgen.h>  // basename
+#include <stdio.h>   // stderr, fprintf
+
+#include <memory>  // std::unique_ptr
+#include <string>  // std::string
+
+#include "Vtop.h"
+#include "verilated.h"
+#include "verilated_vpi.h"
+
+#ifndef VM_TRACE_FST
+// emulate new verilator behavior for legacy versions
+#define VM_TRACE_FST 0
+#endif
+
+#if VM_TRACE
+#if VM_TRACE_FST
+#include <verilated_fst_c.h>
+#else
+#include <verilated_vcd_c.h>
+#endif
+#endif
+
+static vluint64_t main_time = 0;  // Current simulation time
+
+double sc_time_stamp() {  // Called by $time in Verilog
+    return main_time;     // converts to double, to match
+                          // what SystemC does
+}
+
+extern "C" {
+void vlog_startup_routines_bootstrap(void);
+}
+
+static inline bool settle_value_callbacks() {
+    bool cbs_called, again;
+
+    // Call Value Change callbacks
+    // These can modify signal values so we loop
+    // until there are no more changes
+    cbs_called = again = VerilatedVpi::callValueCbs();
+    while (again) {
+        again = VerilatedVpi::callValueCbs();
+    }
+
+    return cbs_called;
+}
+
+int main(int argc, char** argv) {
+    bool traceOn = false;
+#if VM_TRACE_FST
+    const char* traceFile = "dump.fst";
+#else
+    const char* traceFile = "dump.vcd";
+#endif
+
+    for (int i = 1; i < argc; i++) {
+        std::string arg = std::string(argv[i]);
+        if (arg == "--trace") {
+            traceOn = true;
+        } else if (arg == "--trace-file") {
+            if (++i < argc) {
+                traceFile = argv[i];
+            } else {
+                fprintf(stderr, "Error: --trace-file requires a parameter\n");
+                return -1;
+            }
+        } else if (arg == "--help") {
+            fprintf(stderr,
+                    "usage: %s [--trace] [--trace-file TRACEFILE]\n"
+                    "\n"
+                    "Cocotb + Verilator sim\n"
+                    "\n"
+                    "options:\n"
+                    "  --trace      Enables tracing (VCD or FST)\n"
+                    "  --trace-file Specifies the trace file name (%s by "
+                    "default)\n",
+                    basename(argv[0]), traceFile);
+            return 0;
+        }
+    }
+
+    Verilated::commandArgs(argc, argv);
+#ifdef VERILATOR_SIM_DEBUG
+    Verilated::debug(99);
+#endif
+    std::unique_ptr<Vtop> top(new Vtop(""));
+    Verilated::fatalOnVpiError(false);  // otherwise it will fail on systemtf
+
+#ifdef VERILATOR_SIM_DEBUG
+    Verilated::internalsDump();
+#endif
+
+    vlog_startup_routines_bootstrap();
+    VerilatedVpi::callCbs(cbStartOfSimulation);
+
+#if VM_TRACE
+#if VM_TRACE_FST
+    std::unique_ptr<VerilatedFstC> tfp(new VerilatedFstC);
+#else
+    std::unique_ptr<VerilatedVcdC> tfp(new VerilatedVcdC);
+#endif
+
+    if (traceOn) {
+        Verilated::traceEverOn(true);
+        top->trace(tfp.get(), 99);
+        tfp->open(traceFile);
+    }
+#endif
+
+    while (!Verilated::gotFinish()) {
+        // Call registered timed callbacks (e.g. clock timer)
+        // These are called at the beginning of the time step
+        // before the iterative regions (IEEE 1800-2012 4.4.1)
+        VerilatedVpi::callTimedCbs();
+
+        // Call Value Change callbacks triggered by Timer callbacks
+        // These can modify signal values
+        settle_value_callbacks();
+
+        // We must evaluate whole design until we process all 'events'
+        bool again = true;
+        while (again) {
+            // Evaluate design
+            top->eval_step();
+
+            // Call Value Change callbacks triggered by eval()
+            // These can modify signal values
+            again = settle_value_callbacks();
+
+            // Call registered ReadWrite callbacks
+            again |= VerilatedVpi::callCbs(cbReadWriteSynch);
+
+            // Call Value Change callbacks triggered by ReadWrite callbacks
+            // These can modify signal values
+            again |= settle_value_callbacks();
+        }
+        top->eval_end_step();
+
+        // Call ReadOnly callbacks
+        VerilatedVpi::callCbs(cbReadOnlySynch);
+
+#if VM_TRACE
+        if (traceOn) {
+            tfp->dump(main_time);
+        }
+#endif
+        // cocotb controls the clock inputs using cbAfterDelay so
+        // skip ahead to the next registered callback
+        const vluint64_t NO_TOP_EVENTS_PENDING = static_cast<vluint64_t>(~0ULL);
+        vluint64_t next_time_cocotb = VerilatedVpi::cbNextDeadline();
+        vluint64_t next_time_timing =
+            top->eventsPending() ? top->nextTimeSlot() : NO_TOP_EVENTS_PENDING;
+        vluint64_t next_time = std::min(next_time_cocotb, next_time_timing);
+
+        // If there are no more cbAfterDelay callbacks,
+        // the next deadline is max value, so end the simulation now
+        if (next_time == NO_TOP_EVENTS_PENDING) {
+            break;
+        } else {
+            main_time = next_time;
+        }
+
+        // Call registered NextSimTime
+        // It should be called in simulation cycle before everything else
+        // but not on first cycle
+        VerilatedVpi::callCbs(cbNextSimTime);
+
+        // Call Value Change callbacks triggered by NextTimeStep callbacks
+        // These can modify signal values
+        settle_value_callbacks();
+    }
+
+    VerilatedVpi::callCbs(cbEndOfSimulation);
+
+    top->final();
+
+#if VM_TRACE
+    if (traceOn) {
+        tfp->close();
+    }
+#endif
+
+// VM_COVERAGE is a define which is set if Verilator is
+// instructed to collect coverage (when compiling the simulation)
+#if VM_COVERAGE
+    VerilatedCov::write();  // Uses +verilator+coverage+file+<filename>,
+                            // defaults to coverage.dat
+#endif
+
+    return 0;
+}

cocotb/share/makefiles/Makefile.deprecations

@@ -0,0 +1,12 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+ifdef VERILATOR_TRACE
+    $(warning VERILATOR_TRACE is deprecated, see the "Simulator Support" section in the documentation.)
+endif
+
+ifeq ($(SIM_LOWERCASE),aldec)
+    $(warning Using SIM=aldec is deprecated, please use SIM=riviera instead.)
+    SIM_LOWERCASE := riviera
+endif

cocotb/share/makefiles/Makefile.inc

@@ -0,0 +1,176 @@
+###############################################################################
+# Copyright (c) 2013 Potential Ventures Ltd
+# Copyright (c) 2013 SolarFlare Communications Inc
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of Potential Ventures Ltd,
+#       SolarFlare Communications Inc nor the
+#       names of its contributors may be used to endorse or promote products
+#       derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+##############################################################################
+
+# Common makefile included by everything
+
+ifndef COCOTB_MAKEFILE_INC_INCLUDED # Protect against multiple includes
+COCOTB_MAKEFILE_INC_INCLUDED = 1
+
+# Default sim rule will force a re-run of the simulation (though the cocotb library
+# and RTL compilation phases are still evaluated by makefile dependencies)
+.PHONY: sim
+sim:
+	$(RM) $(COCOTB_RESULTS_FILE)
+	"$(MAKE)" -f $(firstword $(MAKEFILE_LIST)) $(COCOTB_RESULTS_FILE)
+
+# Make sure to use bash for the pipefail option used in many simulator Makefiles
+SHELL := bash
+
+# Directory containing the cocotb Python module
+COCOTB_PY_DIR := $(shell cocotb-config --prefix)
+
+# Directory containing all support files required to build cocotb-based
+# simulations: Makefile fragments, and the simulator libraries.
+COCOTB_SHARE_DIR := $(COCOTB_PY_DIR)/cocotb/share
+
+OS=$(shell uname)
+ifneq (, $(findstring MINGW, $(OS)))
+    OS := Msys
+else ifneq (, $(findstring MSYS, $(OS)))
+    OS := Msys
+endif
+export OS
+
+# Detects if Python is running in a virtual environment
+# https://docs.python.org/3/library/venv.html
+IS_VENV=$(shell $(shell cocotb-config --python-bin) -c 'import sys; print(sys.prefix != sys.base_prefix)')
+
+# this ensures we use the same python as the one cocotb was installed into
+PYTHON_BIN ?= $(shell cocotb-config --python-bin)
+
+include $(COCOTB_SHARE_DIR)/makefiles/Makefile.deprecations
+
+LIB_DIR=$(COCOTB_PY_DIR)/cocotb/libs
+
+PYTHON_ARCH := $(shell $(PYTHON_BIN) -c 'from platform import architecture; print(architecture()[0])')
+ifeq ($(filter $(PYTHON_ARCH),64bit 32bit),)
+    $(error Unknown Python architecture: $(PYTHON_ARCH))
+endif
+
+# Changing PYTHONHOME confuses virtual environments, so only set it when not using a venv
+ifeq ($(IS_VENV),False)
+    # Set PYTHONHOME to properly populate sys.path in embedded python interpreter
+    export PYTHONHOME := $(shell $(PYTHON_BIN) -c 'import sys; print(sys.prefix)')
+endif
+
+ifeq ($(OS),Msys)
+    to_tcl_path = $(shell cygpath -m $(1) )
+else
+    to_tcl_path = $(1)
+endif
+
+# Check that the COCOTB_RESULTS_FILE was created, since we can't set an exit code from cocotb.
+define check_for_results_file
+    @test -f $(COCOTB_RESULTS_FILE) || (echo "ERROR: $(COCOTB_RESULTS_FILE) was not written by the simulation!" >&2 && exit 1)
+endef
+
+SIM_BUILD ?= sim_build
+export SIM_BUILD
+
+COCOTB_RESULTS_FILE ?= results.xml
+COCOTB_HDL_TIMEUNIT ?= 1ns
+COCOTB_HDL_TIMEPRECISION ?= 1ps
+
+export COCOTB_RESULTS_FILE
+
+# Depend on all Python from the cocotb package. This triggers a
+# recompilation of the simulation if cocotb is updated.
+CUSTOM_SIM_DEPS += $(shell $(PYTHON_BIN) -c 'import glob; print(" ".join(glob.glob("$(COCOTB_PY_DIR)/cocotb/*.py")))')
+
+# This triggers a recompilation of the simulation if cocotb library is updated.
+CUSTOM_SIM_DEPS += $(shell $(PYTHON_BIN) -c 'import glob; print(" ".join(glob.glob("$(LIB_DIR)/*")))')
+
+
+$(SIM_BUILD):
+	mkdir -p $@
+
+# Regression rule uses Make dependencies to determine whether to run the simulation
+.PHONY: regression
+regression: $(COCOTB_RESULTS_FILE)
+
+# Attempt to detect TOPLEVEL_LANG based on available sources if not set
+ifeq ($(TOPLEVEL_LANG),)
+
+ifneq ($(VHDL_SOURCES),)
+ifeq ($(VERILOG_SOURCES),)
+	TOPLEVEL_LANG := vhdl
+endif
+else ifneq ($(VERILOG_SOURCES),)
+ifeq ($(VHDL_SOURCES),)
+	TOPLEVEL_LANG := verilog
+endif
+endif
+
+endif
+
+define find_libpython_errmsg =
+
+
+find_libpython was not able to find a libpython in the current Python environment. Ensure
+the Python development packages are installed. If they are installed and find_libpython
+is not finding the path to libpython, file an upstream bug in find_libpython; then
+manually override the LIBPYTHON_LOC make variable with the absolute path to libpython.so
+(or python.dll on Windows).
+
+endef
+
+ifndef LIBPYTHON_LOC
+
+# get the path to libpython and the return code from the script
+# adapted from https://stackoverflow.com/a/24658961/6614127
+FIND_LIBPYTHON_RES := $(shell cocotb-config --libpython; echo $$?)
+FIND_LIBPYTHON_RC := $(lastword $(FIND_LIBPYTHON_RES))
+LIBPYTHON_LOC := $(strip $(subst $(FIND_LIBPYTHON_RC)QQQQ,,$(FIND_LIBPYTHON_RES)QQQQ))
+
+# complain if libpython isn't found, and export otherwise
+ifneq ($(FIND_LIBPYTHON_RC),0)
+    $(error $(find_libpython_errmsg))
+endif
+
+endif
+
+export LIBPYTHON_LOC
+
+define check_vhdl_sources
+if [ "$(VHDL_SOURCES_$(LIB))" == "" ]; then \
+  >&2 echo "ERROR: VHDL_SOURCES_$(LIB) is empty or undefined, but '$(LIB)' is present in VHDL_LIB_ORDER."; \
+  exit 1; \
+fi;
+endef
+
+define check_lib_order
+  if [ "$(filter $(SOURCES_VAR:VHDL_SOURCES_%=%), $(VHDL_LIB_ORDER))" == "" ]; then \
+    >&2 echo "ERROR: $(SOURCES_VAR) defined, but library $(SOURCES_VAR:VHDL_SOURCES_%=%) not present in VHDL_LIB_ORDER."; \
+    exit 1; \
+  fi;
+endef
+
+else
+    $(warning Including Makefile.inc from a user makefile is a no-op and deprecated. Remove the Makefile.inc inclusion from your makefile, and only leave the Makefile.sim include.)
+endif # COCOTB_MAKEFILE_INC_INCLUDED

cocotb/share/makefiles/Makefile.sim

@@ -0,0 +1,113 @@
+###############################################################################
+# Copyright (c) 2013, 2018 Potential Ventures Ltd
+# Copyright (c) 2013 SolarFlare Communications Inc
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of Potential Ventures Ltd,
+#       SolarFlare Communications Inc nor the
+#       names of its contributors may be used to endorse or promote products
+#       derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+###############################################################################
+
+# This file includes an appropriate makefile depending on the SIM variable.
+
+.PHONY: all
+all: sim
+
+# NOTE: keep this at 80 chars.
+define help_targets =
+Targets
+=======
+sim                       Unconditionally re-run the simulator (default)
+regression                Run simulator when dependencies have changes
+clean                     Remove build and simulation artefacts
+help                      This help text
+
+endef
+
+# NOTE: keep this at 80 chars.
+define help_makevars =
+Variables
+=========
+
+The following variables are makefile variables:
+
+Makefile-based Test Scripts
+---------------------------
+GUI                       Set this to 1 to enable the GUI mode in the simulator
+SIM                       Selects which simulator Makefile to use
+WAVES                     Enable wave traces dump for Riviera-PRO and Questa
+VERILOG_SOURCES           A list of the Verilog source files to include
+VHDL_SOURCES              A list of the VHDL source files to include
+VHDL_SOURCES_<lib>        VHDL source files to include in *lib* (GHDL/NVC/ModelSim/Questa/Xcelium/Incisive/Riviera-PRO only)
+VHDL_LIB_ORDER            Compilation order of VHDL libraries (needed for NVC/ModelSim/Questa/Xcelium/Incisive/Riviera-PRO)
+SIM_CMD_PREFIX            Prefix for simulation command invocations
+COMPILE_ARGS              Arguments to pass to compile (analysis) stage of simulation
+SIM_ARGS                  Arguments to pass to execution of compiled simulation
+EXTRA_ARGS                Arguments for compile and execute phases
+PLUSARGS                  Plusargs to pass to the simulator
+COCOTB_HDL_TIMEUNIT       Default time unit for simulation
+COCOTB_HDL_TIMEPRECISION  Default time precision for simulation
+CUSTOM_COMPILE_DEPS       Add additional dependencies to the compilation target
+CUSTOM_SIM_DEPS           Add additional dependencies to the simulation target
+SIM_BUILD                 Define a scratch directory for use by the simulator
+SCRIPT_FILE               Simulator script to run (for e.g. wave traces)
+
+endef
+
+
+# NOTE: keep *two* empty lines between "define" and "endef":
+define newline
+
+
+endef
+
+# this cannot be a regular target because of the way Makefile.$(SIM) is included
+ifeq ($(MAKECMDGOALS),help)
+    $(info $(help_targets))
+    $(info $(help_makevars))
+    # hack to get newlines in output, see https://stackoverflow.com/a/54539610
+    # NOTE: the output of the command must not include a '%' sign, otherwise the formatting will break
+    help_envvars := $(subst %,${newline},$(shell cocotb-config --help-vars | tr \\n %))
+    $(info ${help_envvars})
+    # is there a cleaner way to exit here?
+    $(error Stopping after printing help)
+endif
+
+# Default to Icarus if no simulator is defined
+SIM ?= icarus
+
+# Maintain backwards compatibility by supporting upper and lower case SIM variable
+SIM_LOWERCASE := $(shell echo $(SIM) | tr A-Z a-z)
+
+# Directory containing the cocotb Makfiles
+COCOTB_MAKEFILES_DIR := $(shell cocotb-config --makefiles)
+
+include $(COCOTB_MAKEFILES_DIR)/Makefile.deprecations
+
+HAVE_SIMULATOR = $(shell if [ -f $(COCOTB_MAKEFILES_DIR)/simulators/Makefile.$(SIM_LOWERCASE) ]; then echo 1; else echo 0; fi;)
+AVAILABLE_SIMULATORS = $(patsubst .%,%,$(suffix $(wildcard $(COCOTB_MAKEFILES_DIR)/simulators/Makefile.*)))
+
+ifeq ($(HAVE_SIMULATOR),0)
+    $(error Couldn't find makefile for simulator: "$(SIM_LOWERCASE)"! Available simulators: $(AVAILABLE_SIMULATORS))
+endif
+
+include $(COCOTB_MAKEFILES_DIR)/simulators/Makefile.$(SIM_LOWERCASE)

cocotb/share/makefiles/simulators/Makefile.activehdl

@@ -0,0 +1,79 @@
+# Copyright cocotb contributors
+# Licensed under the Revised BSD License, see LICENSE for details.
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Common Makefile for the Aldec Active-HDL simulator
+
+include $(shell cocotb-config --makefiles)/Makefile.inc
+
+CMD_BIN := vsimsa
+
+ifdef ACTIVEHDL_BIN_DIR
+    CMD := $(shell :; command -v $(ACTIVEHDL_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+endif
+
+ALOG_ARGS += -timescale $(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION)
+
+# below allows for maintaining legacy syntax as well as enables using cross-simulator vars COMPILE_ARGS/SIM_ARGS
+ALOG_ARGS += $(COMPILE_ARGS)
+ACOM_ARGS += $(COMPILE_ARGS)
+ASIM_ARGS += $(SIM_ARGS)
+
+ALOG_ARGS += +define+COCOTB_SIM -dbg
+
+ifdef RTL_LIBRARY
+    $(warning Using RTL_LIBRARY is deprecated, please use TOPLEVEL_LIBRARY instead.)
+    TOPLEVEL_LIBRARY ?= $(RTL_LIBRARY)
+else
+    TOPLEVEL_LIBRARY ?= work
+endif
+
+ACOM_ARGS += -dbg
+
+GPI_EXTRA:=
+ifeq ($(TOPLEVEL_LANG),verilog)
+    # backslashes needed because we embed in `echo` below
+    GPI_ARGS = -pli \"$(shell cocotb-config --lib-name-path vpi activehdl)\"
+ifneq ($(VHDL_SOURCES),)
+    GPI_EXTRA = $(shell cocotb-config --lib-name-path vhpi activehdl):cocotbvhpi_entry_point
+endif
+
+else ifeq ($(TOPLEVEL_LANG),vhdl)
+    # backslashes needed because we embed in `echo` below
+    GPI_ARGS = -loadvhpi \"$(shell cocotb-config --lib-name-path vhpi activehdl):vhpi_startup_routines_bootstrap\"
+ifneq ($(VERILOG_SOURCES),)
+    GPI_EXTRA = $(shell cocotb-config --lib-name-path vpi activehdl):cocotbvpi_entry_point
+endif
+else
+   $(error A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG))
+endif
+
+# Create a DO script (Tcl-like but not fully compatible) based on the list of $(VERILOG_SOURCES)
+$(SIM_BUILD)/runsim.do : $(VERILOG_SOURCES) $(VHDL_SOURCES) | $(SIM_BUILD)
+	@echo "alib $(TOPLEVEL_LIBRARY)" > $@
+	@echo "set worklib $(TOPLEVEL_LIBRARY)" >> $@
+ifneq ($(VHDL_SOURCES),)
+	@echo "acom $(ACOM_ARGS) $(call to_tcl_path,$(VHDL_SOURCES))" >> $@
+endif
+ifneq ($(VERILOG_SOURCES),)
+	@echo "alog $(ALOG_ARGS) $(call to_tcl_path,$(VERILOG_SOURCES))" >> $@
+endif
+	@echo "asim $(ASIM_ARGS) $(PLUSARGS) +access +w_nets -interceptcoutput $(GPI_ARGS) $(TOPLEVEL) $(EXTRA_TOPS)" >> $@
+	@echo "run -all" >> $@
+	@echo "endsim" >> $@
+
+$(COCOTB_RESULTS_FILE): $(SIM_BUILD)/runsim.do $(CUSTOM_COMPILE_DEPS) $(CUSTOM_SIM_DEPS)
+	$(RM) $(COCOTB_RESULTS_FILE)
+
+	set -o pipefail; GPI_EXTRA=$(GPI_EXTRA) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	MODULE=$(MODULE) TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) $(SIM_CMD_PREFIX) $(CMD) $(RUN_ARGS) -do $(SIM_BUILD)/runsim.do $(SIM_CMD_SUFFIX)
+
+	$(call check_for_results_file)
+
+clean::
+	$(RM) -r $(SIM_BUILD)
+	$(RM) -r work
+	$(RM) -r wave.asdb

cocotb/share/makefiles/simulators/Makefile.cvc

@@ -0,0 +1,94 @@
+###############################################################################
+# Copyright (c) 2014 Potential Ventures Ltd
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of Potential Ventures Ltd, nor the
+#       names of its contributors may be used to endorse or promote products
+#       derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+###############################################################################
+
+include $(shell cocotb-config --makefiles)/Makefile.inc
+
+ifneq ($(VHDL_SOURCES),)
+
+$(COCOTB_RESULTS_FILE):
+	@echo "Skipping simulation as VHDL is not supported on simulator=$(SIM)"
+debug: $(COCOTB_RESULTS_FILE)
+clean::
+
+else
+
+CMD_BIN := cvc64
+
+ifdef CVC_BIN_DIR
+    CMD := $(shell :; command -v $(CVC_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell :; command -v $(CMD_BIN) 2>/dev/null)
+endif
+
+ifeq (, $(CMD))
+    $(error Unable to locate command >$(CMD_BIN)<)
+else
+    CVC_BIN_DIR := $(shell dirname $(CMD))
+    export CVC_BIN_DIR
+endif
+
+#only interpreted mode works for the moment
+CVC_ITERP ?= 1
+
+ifeq ($(CVC_ITERP),1)
+    CVC_ARGS    += +interp
+endif
+
+# Compilation phase
+$(SIM_BUILD)/sim.vvp: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)
+	MODULE=$(MODULE) \
+	TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        $(CMD) $(CVC_ARGS) +acc+2 -o $(SIM_BUILD)/sim.vvp +define+COCOTB_SIM=1 +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
+
+# Execution phase
+ifeq ($(CVC_ITERP),1)
+    $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp
+else
+    $(COCOTB_RESULTS_FILE): $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
+	MODULE=$(MODULE) \
+        TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        $(SIM_CMD_PREFIX) $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS) $(SIM_CMD_SUFFIX)
+endif
+
+# Execution phase
+ifeq ($(CVC_ITERP),1)
+    debug:  $(CUSTOM_SIM_DEPS)
+	MODULE=$(MODULE) \
+        TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        $(SIM_CMD_PREFIX) gdb --args $(CMD) $(CVC_ARGS) +acc+2 -o $(SIM_BUILD)/sim.vvp +define+COCOTB_SIM=1 +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES)
+else
+    debug: $(SIM_BUILD)/sim.vvp $(CUSTOM_SIM_DEPS)
+	MODULE=$(MODULE) \
+        TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+        gdb --args $(SIM_BUILD)/sim.vvp $(SIM_ARGS) $(EXTRA_ARGS) $(PLUSARGS)
+endif
+
+
+clean::
+	$(RM) -r $(SIM_BUILD)
+endif