cocotb 1.9.1__cp36-cp36m-win_amd64.whl → 2.0.0b1__cp36-cp36m-win_amd64.whl

cocotb/wavedrom.py

@@ -1,199 +0,0 @@
-# Copyright cocotb contributors
-# Copyright (c) 2014 Potential Ventures Ltd
-# Licensed under the Revised BSD License, see LICENSE for details.
-# SPDX-License-Identifier: BSD-3-Clause
-
-import json
-from collections import OrderedDict, defaultdict
-from collections.abc import Mapping
-
-import cocotb
-from cocotb.handle import SimHandleBase
-from cocotb.triggers import ReadOnly, RisingEdge
-
-try:
-    from cocotb_bus.bus import Bus
-except ImportError:
-    Bus = None
-
-
-class Wavedrom:
-    """Base class for a WaveDrom compatible tracer."""
-
-    def __init__(self, obj, name=""):
-        self._hdls = OrderedDict()
-        self._name = name
-        if isinstance(obj, Mapping):
-            self._hdls.update(obj)
-        elif isinstance(obj, SimHandleBase):
-            name = obj._name.split(".")[-1]
-            self._hdls[name] = obj
-            self._name = name
-        elif Bus is not None and isinstance(obj, Bus):
-            self._hdls.update(obj._signals)
-            self._name = obj._name
-        else:
-            raise TypeError(
-                "Cannot use {} with {} objects".format(
-                    type(self).__qualname__, type(obj).__name__
-                )
-            ) from None
-        self.clear()
-
-    def sample(self):
-        """Record a sample of the signal value at this point in time."""
-
-        def _lastval(samples):
-            for x in range(len(samples) - 1, -1, -1):
-                if samples[x] not in "=.|":
-                    return samples[x]
-            return None
-
-        for name, hdl in self._hdls.items():
-            val = hdl.value
-            valstr = val.binstr.lower()
-
-            # Decide what character to use to represent this signal
-            if len(valstr) == 1:
-                char = valstr
-            elif "x" in valstr:
-                char = "x"
-            elif "u" in valstr:
-                char = "u"
-            elif "z" in valstr:
-                char = "z"
-            else:
-                if (
-                    len(self._data[name])
-                    and self._data[name][-1] == int(val)
-                    and self._samples[name][-1] in "=."
-                ):
-                    char = "."
-                else:
-                    char = "="
-                    self._data[name].append(int(val))
-
-            # Detect if this is unchanged
-            if len(valstr) == 1 and char == _lastval(self._samples[name]):
-                char = "."
-            self._samples[name].append(char)
-
-    def clear(self):
-        """Delete all sampled data."""
-        self._samples = defaultdict(list)
-        self._data = defaultdict(list)
-
-    def gap(self):
-        for name, hdl in self._hdls.items():
-            self._samples[name].append("|")
-
-    def get(self, add_clock=True):
-        """Return the samples as a list suitable for use with WaveDrom."""
-        siglist = []
-        traces = []
-        for name in self._hdls.keys():
-            samples = self._samples[name]
-            traces.append({"name": name, "wave": "".join(samples)})
-            if name in self._data:
-                traces[-1]["data"] = " ".join([repr(s) for s in self._data[name]])
-
-        if len(traces) > 1:
-            traces.insert(0, self._name)
-            siglist.append(traces)
-        else:
-            siglist.append(traces[0])
-
-        if add_clock:
-            tracelen = len(traces[-1]["wave"])
-            siglist.insert(0, {"name": "clk", "wave": "p" + "." * (tracelen - 1)})
-
-        return siglist
-
-
-class trace:
-    """Context manager to enable tracing of signals.
-
-    Arguments are an arbitrary number of signals or buses to trace.
-    We also require a clock to sample on, passed in as a keyword argument.
-
-    Usage::
-
-        with trace(sig1, sig2, a_bus, clk=clk) as waves:
-            # Stuff happens, we trace it
-
-            # Dump to JSON format compatible with WaveDrom
-            j = waves.dumpj()
-    """
-
-    def __init__(self, *args, clk=None):
-        self._clock = clk
-        self._signals = []
-        for arg in args:
-            self._signals.append(Wavedrom(arg))
-        self._coro = None
-        self._clocks = 0
-        self._enabled = False
-
-        if self._clock is None:
-            raise ValueError("Trace requires a clock to sample")
-
-    async def _monitor(self):
-        self._clocks = 0
-        while True:
-            await RisingEdge(self._clock)
-            await ReadOnly()
-            if not self._enabled:
-                continue
-            self._clocks += 1
-            for sig in self._signals:
-                sig.sample()
-
-    def insert_gap(self):
-        self._clocks += 1
-        for sig in self._signals:
-            sig.gap()
-
-    def disable(self):
-        self._enabled = False
-
-    def enable(self):
-        self._enabled = True
-
-    def __enter__(self):
-        for sig in self._signals:
-            sig.clear()
-        self.enable()
-        self._coro = cocotb.start_soon(self._monitor())
-        return self
-
-    def __exit__(self, exc_type, exc_val, exc_tb):
-        self._coro.kill()
-        for sig in self._signals:
-            sig.clear()
-        self.disable()
-        return None
-
-    def write(self, filename, **kwargs):
-        with open(filename, "w") as f:
-            f.write(self.dumpj(**kwargs))
-
-    def dumpj(self, header="", footer="", config=""):
-        trace = {"signal": []}
-        trace["signal"].append(
-            {"name": "clock", "wave": "p" + "." * (self._clocks - 1)}
-        )
-        for sig in self._signals:
-            trace["signal"].extend(sig.get(add_clock=False))
-        if header:
-            if isinstance(header, dict):
-                trace["head"] = header
-            else:
-                trace["head"] = {"text": header}
-        if footer:
-            if isinstance(footer, dict):
-                trace["foot"] = footer
-            else:
-                trace["foot"] = {"text": footer}
-        if config:
-            trace["config"] = config
-        return json.dumps(trace, indent=4, sort_keys=False)

cocotb/xunit_reporter.py

@@ -1,80 +0,0 @@
-# Copyright (c) 2013 Potential Ventures Ltd
-# Copyright (c) 2013 SolarFlare Communications Inc
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#     * Redistributions of source code must retain the above copyright
-#       notice, this list of conditions and the following disclaimer.
-#     * Redistributions in binary form must reproduce the above copyright
-#       notice, this list of conditions and the following disclaimer in the
-#       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Potential Ventures Ltd,
-#       SolarFlare Communications Inc nor the
-#       names of its contributors may be used to endorse or promote products
-#       derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-import xml.etree.ElementTree as ET
-from xml.etree.ElementTree import Element, SubElement
-
-
-class XUnitReporter:
-    def __init__(self, filename="results.xml"):
-        self.results = Element("testsuites", name="results")
-        self.filename = filename
-
-    def add_testsuite(self, **kwargs):
-        self.last_testsuite = SubElement(self.results, "testsuite", **kwargs)
-        return self.last_testsuite
-
-    def add_testcase(self, testsuite=None, **kwargs):
-        if testsuite is None:
-            testsuite = self.last_testsuite
-        self.last_testcase = SubElement(testsuite, "testcase", **kwargs)
-        return self.last_testcase
-
-    def add_property(self, testsuite=None, **kwargs):
-        if testsuite is None:
-            testsuite = self.last_testsuite
-        self.last_property = SubElement(testsuite, "property", **kwargs)
-        return self.last_property
-
-    def add_failure(self, testcase=None, **kwargs):
-        if testcase is None:
-            testcase = self.last_testcase
-        SubElement(testcase, "failure", **kwargs)
-
-    def add_skipped(self, testcase=None, **kwargs):
-        if testcase is None:
-            testcase = self.last_testcase
-        SubElement(testcase, "skipped", **kwargs)
-
-    def indent(self, elem, level=0):
-        i = "\n" + level * "  "
-        if len(elem):
-            if not elem.text or not elem.text.strip():
-                elem.text = i + "  "
-            if not elem.tail or not elem.tail.strip():
-                elem.tail = i
-            for elem in elem:
-                self.indent(elem, level + 1)
-            if not elem.tail or not elem.tail.strip():
-                elem.tail = i
-        else:
-            if level and (not elem.tail or not elem.tail.strip()):
-                elem.tail = i
-
-    def write(self):
-        self.indent(self.results)
-        ET.ElementTree(self.results).write(self.filename, encoding="UTF-8")

cocotb-1.9.1.dist-info/METADATA

@@ -1,168 +0,0 @@
-Metadata-Version: 2.1
-Name: cocotb
-Version: 1.9.1
-Summary: cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
-Home-page: https://www.cocotb.org
-Author: Chris Higgs, Stuart Hodgson
-Maintainer: cocotb contributors
-Maintainer-email: cocotb@lists.librecores.org
-License: BSD
-Project-URL: Bug Tracker, https://github.com/cocotb/cocotb/issues
-Project-URL: Source Code, https://github.com/cocotb/cocotb
-Project-URL: Documentation, https://docs.cocotb.org
-Platform: any
-Classifier: Programming Language :: Python :: 3
-Classifier: Programming Language :: Python :: 3.6
-Classifier: Programming Language :: Python :: 3.7
-Classifier: Programming Language :: Python :: 3.8
-Classifier: Programming Language :: Python :: 3.9
-Classifier: Programming Language :: Python :: 3.10
-Classifier: Programming Language :: Python :: 3.11
-Classifier: License :: OSI Approved :: BSD License
-Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
-Classifier: Framework :: cocotb
-Requires-Python: >=3.6
-Description-Content-Type: text/markdown
-License-File: LICENSE
-Requires-Dist: find-libpython
-Provides-Extra: bus
-Requires-Dist: cocotb-bus ; extra == 'bus'
-
-**cocotb** is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
-
-[![Documentation Status](https://readthedocs.org/projects/cocotb/badge/?version=latest)](https://docs.cocotb.org/en/latest/)
-[![CI](https://github.com/cocotb/cocotb/actions/workflows/build-test-dev.yml/badge.svg?branch=master)](https://github.com/cocotb/cocotb/actions/workflows/build-test-dev.yml)
-[![PyPI](https://img.shields.io/pypi/dm/cocotb.svg?label=PyPI%20downloads)](https://pypi.org/project/cocotb/)
-[![Gitpod Ready-to-Code](https://img.shields.io/badge/Gitpod-ready--to--code-blue?logo=gitpod)](https://gitpod.io/#https://github.com/cocotb/cocotb)
-[![codecov](https://codecov.io/gh/cocotb/cocotb/branch/master/graph/badge.svg)](https://codecov.io/gh/cocotb/cocotb)
-
-* Read the [documentation](https://docs.cocotb.org)
-* Get involved:
-  * [Raise a bug / request an enhancement](https://github.com/cocotb/cocotb/issues/new) (Requires a GitHub account)
-  * [Join the Gitter chat room](https://gitter.im/cocotb/Lobby)
-
-## Installation
-
-The current stable version of cocotb requires:
-
-- Python 3.6+
-- GNU Make 3+
-- An HDL simulator (such as [Icarus Verilog](https://docs.cocotb.org/en/stable/simulator_support.html#icarus-verilog),
-[Verilator](https://docs.cocotb.org/en/stable/simulator_support.html#verilator),
-[GHDL](https://docs.cocotb.org/en/stable/simulator_support.html#ghdl) or
-[other simulator](https://docs.cocotb.org/en/stable/simulator_support.html))
-
-After installing these dependencies, the latest stable version 1.x of cocotb can be installed with pip.
-
-```command
-pip install 'cocotb == 1.*'
-```
-
-For more details on installation, including prerequisites,
-see [the documentation](https://docs.cocotb.org/en/stable/install.html).
-
-For details on how to install the *development* version of cocotb,
-see [the preliminary documentation of the future release](https://docs.cocotb.org/en/latest/install_devel.html#install-devel).
-
-**!!! Bus and Testbenching Components !!!**
-The reusable bus interfaces and testbenching components have recently been moved to the [cocotb-bus](https://github.com/cocotb/cocotb-bus) package.
-You can easily install these at the same time as cocotb by adding the `bus` extra install: `pip install cocotb[bus]`.
-
-## Usage
-
-As a first trivial introduction to cocotb, the following example "tests" a flip-flop.
-
-First, we need a hardware design which we can test. For this example, create a file `dff.sv` with SystemVerilog code for a simple [D flip-flop](https://en.wikipedia.org/wiki/Flip-flop_(electronics)#D_flip-flop). You could also use any other language a [cocotb-supported simulator](https://docs.cocotb.org/en/stable/simulator_support.html) understands, e.g. VHDL.
-
-```systemverilog
-// dff.sv
-
-`timescale 1us/1ns
-
-module dff (
-    output logic q,
-    input logic clk, d
-);
-
-always @(posedge clk) begin
-    q <= d;
-end
-
-endmodule
-```
-
-An example of a simple randomized cocotb testbench:
-
-```python
-# test_dff.py
-
-import random
-
-import cocotb
-from cocotb.clock import Clock
-from cocotb.triggers import RisingEdge
-from cocotb.types import LogicArray
-
-@cocotb.test()
-async def dff_simple_test(dut):
-    """Test that d propagates to q"""
-
-    # Assert initial output is unknown
-    assert LogicArray(dut.q.value) == LogicArray("X")
-    # Set initial input value to prevent it from floating
-    dut.d.value = 0
-
-    clock = Clock(dut.clk, 10, units="us")  # Create a 10us period clock on port clk
-    # Start the clock. Start it low to avoid issues on the first RisingEdge
-    cocotb.start_soon(clock.start(start_high=False))
-
-    # Synchronize with the clock. This will regisiter the initial `d` value
-    await RisingEdge(dut.clk)
-    expected_val = 0  # Matches initial input value
-    for i in range(10):
-        val = random.randint(0, 1)
-        dut.d.value = val  # Assign the random value val to the input port d
-        await RisingEdge(dut.clk)
-        assert dut.q.value == expected_val, f"output q was incorrect on the {i}th cycle"
-        expected_val = val # Save random value for next RisingEdge
-
-    # Check the final input on the next clock
-    await RisingEdge(dut.clk)
-    assert dut.q.value == expected_val, "output q was incorrect on the last cycle"
-```
-
-A simple Makefile:
-
-```make
-# Makefile
-
-TOPLEVEL_LANG = verilog
-VERILOG_SOURCES = $(shell pwd)/dff.sv
-TOPLEVEL = dff
-MODULE = test_dff
-
-include $(shell cocotb-config --makefiles)/Makefile.sim
-```
-
-In order to run the test with Icarus Verilog, execute:
-
-```command
-make SIM=icarus
-```
-
-[![asciicast](https://asciinema.org/a/317220.svg)](https://asciinema.org/a/317220)
-
-For more information please see the [cocotb documentation](https://docs.cocotb.org/)
-and [our wiki](https://github.com/cocotb/cocotb/wiki).
-
-## Tutorials, examples and related projects
-
-* the tutorial section [in the official documentation](https://docs.cocotb.org/)
-* [cocotb-bus](https://github.com/cocotb/cocotb-bus) for pre-packaged testbenching tools and reusable bus interfaces.
-* [cocotb-based USB 1.1 test suite](https://github.com/antmicro/usb-test-suite-build) for FPGA IP, with testbenches for a variety of open source USB cores
-* [`cocotb-coverage`](https://github.com/mciepluc/cocotb-coverage), an extension for Functional Coverage and Constrained Randomization
-* [`uvm-python`](https://github.com/tpoikela/uvm-python), an almost 1:1 port of UVM 1.2 to Python
-* our wiki [on extension modules](https://github.com/cocotb/cocotb/wiki/Further-Resources#extension-modules-cocotbext)
-* the list of [GitHub projects depending on cocotb](https://github.com/cocotb/cocotb/network/dependents)
-
-

cocotb-1.9.1.dist-info/RECORD

@@ -1,121 +0,0 @@
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cocotb-1.9.1.dist-info/entry_points.txt

@@ -1,3 +0,0 @@
-[console_scripts]
-cocotb-config = cocotb.config:main
-